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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip KSZ9477 switch driver main logic
0004  *
0005  * Copyright (C) 2017-2019 Microchip Technology Inc.
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/platform_data/microchip-ksz.h>
0012 #include <linux/phy.h>
0013 #include <linux/if_bridge.h>
0014 #include <linux/if_vlan.h>
0015 #include <net/dsa.h>
0016 #include <net/switchdev.h>
0017 
0018 #include "ksz9477_reg.h"
0019 #include "ksz_common.h"
0020 #include "ksz9477.h"
0021 
0022 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
0023 {
0024     regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
0025 }
0026 
0027 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
0028              bool set)
0029 {
0030     regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
0031                bits, set ? bits : 0);
0032 }
0033 
0034 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
0035 {
0036     regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
0037 }
0038 
0039 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
0040                    u32 bits, bool set)
0041 {
0042     regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
0043                bits, set ? bits : 0);
0044 }
0045 
0046 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu)
0047 {
0048     u16 frame_size, max_frame = 0;
0049     int i;
0050 
0051     frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
0052 
0053     /* Cache the per-port MTU setting */
0054     dev->ports[port].max_frame = frame_size;
0055 
0056     for (i = 0; i < dev->info->port_cnt; i++)
0057         max_frame = max(max_frame, dev->ports[i].max_frame);
0058 
0059     return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2,
0060                   REG_SW_MTU_MASK, max_frame);
0061 }
0062 
0063 int ksz9477_max_mtu(struct ksz_device *dev, int port)
0064 {
0065     return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
0066 }
0067 
0068 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
0069 {
0070     unsigned int val;
0071 
0072     return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
0073                     val, !(val & VLAN_START), 10, 1000);
0074 }
0075 
0076 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
0077                   u32 *vlan_table)
0078 {
0079     int ret;
0080 
0081     mutex_lock(&dev->vlan_mutex);
0082 
0083     ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
0084     ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
0085 
0086     /* wait to be cleared */
0087     ret = ksz9477_wait_vlan_ctrl_ready(dev);
0088     if (ret) {
0089         dev_dbg(dev->dev, "Failed to read vlan table\n");
0090         goto exit;
0091     }
0092 
0093     ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
0094     ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
0095     ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
0096 
0097     ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
0098 
0099 exit:
0100     mutex_unlock(&dev->vlan_mutex);
0101 
0102     return ret;
0103 }
0104 
0105 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
0106                   u32 *vlan_table)
0107 {
0108     int ret;
0109 
0110     mutex_lock(&dev->vlan_mutex);
0111 
0112     ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
0113     ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
0114     ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
0115 
0116     ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
0117     ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
0118 
0119     /* wait to be cleared */
0120     ret = ksz9477_wait_vlan_ctrl_ready(dev);
0121     if (ret) {
0122         dev_dbg(dev->dev, "Failed to write vlan table\n");
0123         goto exit;
0124     }
0125 
0126     ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
0127 
0128     /* update vlan cache table */
0129     dev->vlan_cache[vid].table[0] = vlan_table[0];
0130     dev->vlan_cache[vid].table[1] = vlan_table[1];
0131     dev->vlan_cache[vid].table[2] = vlan_table[2];
0132 
0133 exit:
0134     mutex_unlock(&dev->vlan_mutex);
0135 
0136     return ret;
0137 }
0138 
0139 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
0140 {
0141     ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
0142     ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
0143     ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
0144     ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
0145 }
0146 
0147 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
0148 {
0149     ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
0150     ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
0151     ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
0152     ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
0153 }
0154 
0155 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
0156 {
0157     unsigned int val;
0158 
0159     return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
0160                     val, !(val & ALU_START), 10, 1000);
0161 }
0162 
0163 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
0164 {
0165     unsigned int val;
0166 
0167     return regmap_read_poll_timeout(dev->regmap[2],
0168                     REG_SW_ALU_STAT_CTRL__4,
0169                     val, !(val & ALU_STAT_START),
0170                     10, 1000);
0171 }
0172 
0173 int ksz9477_reset_switch(struct ksz_device *dev)
0174 {
0175     u8 data8;
0176     u32 data32;
0177 
0178     /* reset switch */
0179     ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
0180 
0181     /* turn off SPI DO Edge select */
0182     regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
0183                SPI_AUTO_EDGE_DETECTION, 0);
0184 
0185     /* default configuration */
0186     ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
0187     data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
0188           SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
0189     ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
0190 
0191     /* disable interrupts */
0192     ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
0193     ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
0194     ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
0195 
0196     data8 = SW_ENABLE_REFCLKO;
0197     if (dev->synclko_disable)
0198         data8 = 0;
0199     else if (dev->synclko_125)
0200         data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
0201     ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8);
0202 
0203     return 0;
0204 }
0205 
0206 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
0207 {
0208     struct ksz_port *p = &dev->ports[port];
0209     unsigned int val;
0210     u32 data;
0211     int ret;
0212 
0213     /* retain the flush/freeze bit */
0214     data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
0215     data |= MIB_COUNTER_READ;
0216     data |= (addr << MIB_COUNTER_INDEX_S);
0217     ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
0218 
0219     ret = regmap_read_poll_timeout(dev->regmap[2],
0220             PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
0221             val, !(val & MIB_COUNTER_READ), 10, 1000);
0222     /* failed to read MIB. get out of loop */
0223     if (ret) {
0224         dev_dbg(dev->dev, "Failed to get MIB\n");
0225         return;
0226     }
0227 
0228     /* count resets upon read */
0229     ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
0230     *cnt += data;
0231 }
0232 
0233 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
0234                u64 *dropped, u64 *cnt)
0235 {
0236     addr = dev->info->mib_names[addr].index;
0237     ksz9477_r_mib_cnt(dev, port, addr, cnt);
0238 }
0239 
0240 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
0241 {
0242     u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
0243     struct ksz_port *p = &dev->ports[port];
0244 
0245     /* enable/disable the port for flush/freeze function */
0246     mutex_lock(&p->mib.cnt_mutex);
0247     ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
0248 
0249     /* used by MIB counter reading code to know freeze is enabled */
0250     p->freeze = freeze;
0251     mutex_unlock(&p->mib.cnt_mutex);
0252 }
0253 
0254 void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
0255 {
0256     struct ksz_port_mib *mib = &dev->ports[port].mib;
0257 
0258     /* flush all enabled port MIB counters */
0259     mutex_lock(&mib->cnt_mutex);
0260     ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
0261              MIB_COUNTER_FLUSH_FREEZE);
0262     ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
0263     ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
0264     mutex_unlock(&mib->cnt_mutex);
0265 }
0266 
0267 void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
0268 {
0269     u16 val = 0xffff;
0270 
0271     /* No real PHY after this. Simulate the PHY.
0272      * A fixed PHY can be setup in the device tree, but this function is
0273      * still called for that port during initialization.
0274      * For RGMII PHY there is no way to access it so the fixed PHY should
0275      * be used.  For SGMII PHY the supporting code will be added later.
0276      */
0277     if (addr >= dev->phy_port_cnt) {
0278         struct ksz_port *p = &dev->ports[addr];
0279 
0280         switch (reg) {
0281         case MII_BMCR:
0282             val = 0x1140;
0283             break;
0284         case MII_BMSR:
0285             val = 0x796d;
0286             break;
0287         case MII_PHYSID1:
0288             val = 0x0022;
0289             break;
0290         case MII_PHYSID2:
0291             val = 0x1631;
0292             break;
0293         case MII_ADVERTISE:
0294             val = 0x05e1;
0295             break;
0296         case MII_LPA:
0297             val = 0xc5e1;
0298             break;
0299         case MII_CTRL1000:
0300             val = 0x0700;
0301             break;
0302         case MII_STAT1000:
0303             if (p->phydev.speed == SPEED_1000)
0304                 val = 0x3800;
0305             else
0306                 val = 0;
0307             break;
0308         }
0309     } else {
0310         ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
0311     }
0312 
0313     *data = val;
0314 }
0315 
0316 void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
0317 {
0318     /* No real PHY after this. */
0319     if (addr >= dev->phy_port_cnt)
0320         return;
0321 
0322     /* No gigabit support.  Do not write to this register. */
0323     if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
0324         return;
0325 
0326     ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
0327 }
0328 
0329 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member)
0330 {
0331     ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
0332 }
0333 
0334 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
0335 {
0336     const u16 *regs = dev->info->regs;
0337     u8 data;
0338 
0339     regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
0340                SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
0341                SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
0342 
0343     if (port < dev->info->port_cnt) {
0344         /* flush individual port */
0345         ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
0346         if (!(data & PORT_LEARN_DISABLE))
0347             ksz_pwrite8(dev, port, regs[P_STP_CTRL],
0348                     data | PORT_LEARN_DISABLE);
0349         ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
0350         ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
0351     } else {
0352         /* flush all */
0353         ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
0354     }
0355 }
0356 
0357 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port,
0358                 bool flag, struct netlink_ext_ack *extack)
0359 {
0360     if (flag) {
0361         ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
0362                  PORT_VLAN_LOOKUP_VID_0, true);
0363         ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
0364     } else {
0365         ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
0366         ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
0367                  PORT_VLAN_LOOKUP_VID_0, false);
0368     }
0369 
0370     return 0;
0371 }
0372 
0373 int ksz9477_port_vlan_add(struct ksz_device *dev, int port,
0374               const struct switchdev_obj_port_vlan *vlan,
0375               struct netlink_ext_ack *extack)
0376 {
0377     u32 vlan_table[3];
0378     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
0379     int err;
0380 
0381     err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table);
0382     if (err) {
0383         NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table");
0384         return err;
0385     }
0386 
0387     vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M);
0388     if (untagged)
0389         vlan_table[1] |= BIT(port);
0390     else
0391         vlan_table[1] &= ~BIT(port);
0392     vlan_table[1] &= ~(BIT(dev->cpu_port));
0393 
0394     vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
0395 
0396     err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table);
0397     if (err) {
0398         NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table");
0399         return err;
0400     }
0401 
0402     /* change PVID */
0403     if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
0404         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid);
0405 
0406     return 0;
0407 }
0408 
0409 int ksz9477_port_vlan_del(struct ksz_device *dev, int port,
0410               const struct switchdev_obj_port_vlan *vlan)
0411 {
0412     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
0413     u32 vlan_table[3];
0414     u16 pvid;
0415 
0416     ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
0417     pvid = pvid & 0xFFF;
0418 
0419     if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
0420         dev_dbg(dev->dev, "Failed to get vlan table\n");
0421         return -ETIMEDOUT;
0422     }
0423 
0424     vlan_table[2] &= ~BIT(port);
0425 
0426     if (pvid == vlan->vid)
0427         pvid = 1;
0428 
0429     if (untagged)
0430         vlan_table[1] &= ~BIT(port);
0431 
0432     if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
0433         dev_dbg(dev->dev, "Failed to set vlan table\n");
0434         return -ETIMEDOUT;
0435     }
0436 
0437     ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
0438 
0439     return 0;
0440 }
0441 
0442 int ksz9477_fdb_add(struct ksz_device *dev, int port,
0443             const unsigned char *addr, u16 vid, struct dsa_db db)
0444 {
0445     u32 alu_table[4];
0446     u32 data;
0447     int ret = 0;
0448 
0449     mutex_lock(&dev->alu_mutex);
0450 
0451     /* find any entry with mac & vid */
0452     data = vid << ALU_FID_INDEX_S;
0453     data |= ((addr[0] << 8) | addr[1]);
0454     ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
0455 
0456     data = ((addr[2] << 24) | (addr[3] << 16));
0457     data |= ((addr[4] << 8) | addr[5]);
0458     ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
0459 
0460     /* start read operation */
0461     ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
0462 
0463     /* wait to be finished */
0464     ret = ksz9477_wait_alu_ready(dev);
0465     if (ret) {
0466         dev_dbg(dev->dev, "Failed to read ALU\n");
0467         goto exit;
0468     }
0469 
0470     /* read ALU entry */
0471     ksz9477_read_table(dev, alu_table);
0472 
0473     /* update ALU entry */
0474     alu_table[0] = ALU_V_STATIC_VALID;
0475     alu_table[1] |= BIT(port);
0476     if (vid)
0477         alu_table[1] |= ALU_V_USE_FID;
0478     alu_table[2] = (vid << ALU_V_FID_S);
0479     alu_table[2] |= ((addr[0] << 8) | addr[1]);
0480     alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
0481     alu_table[3] |= ((addr[4] << 8) | addr[5]);
0482 
0483     ksz9477_write_table(dev, alu_table);
0484 
0485     ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
0486 
0487     /* wait to be finished */
0488     ret = ksz9477_wait_alu_ready(dev);
0489     if (ret)
0490         dev_dbg(dev->dev, "Failed to write ALU\n");
0491 
0492 exit:
0493     mutex_unlock(&dev->alu_mutex);
0494 
0495     return ret;
0496 }
0497 
0498 int ksz9477_fdb_del(struct ksz_device *dev, int port,
0499             const unsigned char *addr, u16 vid, struct dsa_db db)
0500 {
0501     u32 alu_table[4];
0502     u32 data;
0503     int ret = 0;
0504 
0505     mutex_lock(&dev->alu_mutex);
0506 
0507     /* read any entry with mac & vid */
0508     data = vid << ALU_FID_INDEX_S;
0509     data |= ((addr[0] << 8) | addr[1]);
0510     ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
0511 
0512     data = ((addr[2] << 24) | (addr[3] << 16));
0513     data |= ((addr[4] << 8) | addr[5]);
0514     ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
0515 
0516     /* start read operation */
0517     ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
0518 
0519     /* wait to be finished */
0520     ret = ksz9477_wait_alu_ready(dev);
0521     if (ret) {
0522         dev_dbg(dev->dev, "Failed to read ALU\n");
0523         goto exit;
0524     }
0525 
0526     ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
0527     if (alu_table[0] & ALU_V_STATIC_VALID) {
0528         ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
0529         ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
0530         ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
0531 
0532         /* clear forwarding port */
0533         alu_table[2] &= ~BIT(port);
0534 
0535         /* if there is no port to forward, clear table */
0536         if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
0537             alu_table[0] = 0;
0538             alu_table[1] = 0;
0539             alu_table[2] = 0;
0540             alu_table[3] = 0;
0541         }
0542     } else {
0543         alu_table[0] = 0;
0544         alu_table[1] = 0;
0545         alu_table[2] = 0;
0546         alu_table[3] = 0;
0547     }
0548 
0549     ksz9477_write_table(dev, alu_table);
0550 
0551     ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
0552 
0553     /* wait to be finished */
0554     ret = ksz9477_wait_alu_ready(dev);
0555     if (ret)
0556         dev_dbg(dev->dev, "Failed to write ALU\n");
0557 
0558 exit:
0559     mutex_unlock(&dev->alu_mutex);
0560 
0561     return ret;
0562 }
0563 
0564 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
0565 {
0566     alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
0567     alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
0568     alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
0569     alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
0570             ALU_V_PRIO_AGE_CNT_M;
0571     alu->mstp = alu_table[0] & ALU_V_MSTP_M;
0572 
0573     alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
0574     alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
0575     alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
0576 
0577     alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
0578 
0579     alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
0580     alu->mac[1] = alu_table[2] & 0xFF;
0581     alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
0582     alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
0583     alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
0584     alu->mac[5] = alu_table[3] & 0xFF;
0585 }
0586 
0587 int ksz9477_fdb_dump(struct ksz_device *dev, int port,
0588              dsa_fdb_dump_cb_t *cb, void *data)
0589 {
0590     int ret = 0;
0591     u32 ksz_data;
0592     u32 alu_table[4];
0593     struct alu_struct alu;
0594     int timeout;
0595 
0596     mutex_lock(&dev->alu_mutex);
0597 
0598     /* start ALU search */
0599     ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
0600 
0601     do {
0602         timeout = 1000;
0603         do {
0604             ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
0605             if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
0606                 break;
0607             usleep_range(1, 10);
0608         } while (timeout-- > 0);
0609 
0610         if (!timeout) {
0611             dev_dbg(dev->dev, "Failed to search ALU\n");
0612             ret = -ETIMEDOUT;
0613             goto exit;
0614         }
0615 
0616         if (!(ksz_data & ALU_VALID))
0617             continue;
0618 
0619         /* read ALU table */
0620         ksz9477_read_table(dev, alu_table);
0621 
0622         ksz9477_convert_alu(&alu, alu_table);
0623 
0624         if (alu.port_forward & BIT(port)) {
0625             ret = cb(alu.mac, alu.fid, alu.is_static, data);
0626             if (ret)
0627                 goto exit;
0628         }
0629     } while (ksz_data & ALU_START);
0630 
0631 exit:
0632 
0633     /* stop ALU search */
0634     ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
0635 
0636     mutex_unlock(&dev->alu_mutex);
0637 
0638     return ret;
0639 }
0640 
0641 int ksz9477_mdb_add(struct ksz_device *dev, int port,
0642             const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
0643 {
0644     u32 static_table[4];
0645     const u8 *shifts;
0646     const u32 *masks;
0647     u32 data;
0648     int index;
0649     u32 mac_hi, mac_lo;
0650     int err = 0;
0651 
0652     shifts = dev->info->shifts;
0653     masks = dev->info->masks;
0654 
0655     mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
0656     mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
0657     mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
0658 
0659     mutex_lock(&dev->alu_mutex);
0660 
0661     for (index = 0; index < dev->info->num_statics; index++) {
0662         /* find empty slot first */
0663         data = (index << shifts[ALU_STAT_INDEX]) |
0664             masks[ALU_STAT_READ] | ALU_STAT_START;
0665         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
0666 
0667         /* wait to be finished */
0668         err = ksz9477_wait_alu_sta_ready(dev);
0669         if (err) {
0670             dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
0671             goto exit;
0672         }
0673 
0674         /* read ALU static table */
0675         ksz9477_read_table(dev, static_table);
0676 
0677         if (static_table[0] & ALU_V_STATIC_VALID) {
0678             /* check this has same vid & mac address */
0679             if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
0680                 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
0681                 static_table[3] == mac_lo) {
0682                 /* found matching one */
0683                 break;
0684             }
0685         } else {
0686             /* found empty one */
0687             break;
0688         }
0689     }
0690 
0691     /* no available entry */
0692     if (index == dev->info->num_statics) {
0693         err = -ENOSPC;
0694         goto exit;
0695     }
0696 
0697     /* add entry */
0698     static_table[0] = ALU_V_STATIC_VALID;
0699     static_table[1] |= BIT(port);
0700     if (mdb->vid)
0701         static_table[1] |= ALU_V_USE_FID;
0702     static_table[2] = (mdb->vid << ALU_V_FID_S);
0703     static_table[2] |= mac_hi;
0704     static_table[3] = mac_lo;
0705 
0706     ksz9477_write_table(dev, static_table);
0707 
0708     data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START;
0709     ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
0710 
0711     /* wait to be finished */
0712     if (ksz9477_wait_alu_sta_ready(dev))
0713         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
0714 
0715 exit:
0716     mutex_unlock(&dev->alu_mutex);
0717     return err;
0718 }
0719 
0720 int ksz9477_mdb_del(struct ksz_device *dev, int port,
0721             const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
0722 {
0723     u32 static_table[4];
0724     const u8 *shifts;
0725     const u32 *masks;
0726     u32 data;
0727     int index;
0728     int ret = 0;
0729     u32 mac_hi, mac_lo;
0730 
0731     shifts = dev->info->shifts;
0732     masks = dev->info->masks;
0733 
0734     mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
0735     mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
0736     mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
0737 
0738     mutex_lock(&dev->alu_mutex);
0739 
0740     for (index = 0; index < dev->info->num_statics; index++) {
0741         /* find empty slot first */
0742         data = (index << shifts[ALU_STAT_INDEX]) |
0743             masks[ALU_STAT_READ] | ALU_STAT_START;
0744         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
0745 
0746         /* wait to be finished */
0747         ret = ksz9477_wait_alu_sta_ready(dev);
0748         if (ret) {
0749             dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
0750             goto exit;
0751         }
0752 
0753         /* read ALU static table */
0754         ksz9477_read_table(dev, static_table);
0755 
0756         if (static_table[0] & ALU_V_STATIC_VALID) {
0757             /* check this has same vid & mac address */
0758 
0759             if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
0760                 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
0761                 static_table[3] == mac_lo) {
0762                 /* found matching one */
0763                 break;
0764             }
0765         }
0766     }
0767 
0768     /* no available entry */
0769     if (index == dev->info->num_statics)
0770         goto exit;
0771 
0772     /* clear port */
0773     static_table[1] &= ~BIT(port);
0774 
0775     if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
0776         /* delete entry */
0777         static_table[0] = 0;
0778         static_table[1] = 0;
0779         static_table[2] = 0;
0780         static_table[3] = 0;
0781     }
0782 
0783     ksz9477_write_table(dev, static_table);
0784 
0785     data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START;
0786     ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
0787 
0788     /* wait to be finished */
0789     ret = ksz9477_wait_alu_sta_ready(dev);
0790     if (ret)
0791         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
0792 
0793 exit:
0794     mutex_unlock(&dev->alu_mutex);
0795 
0796     return ret;
0797 }
0798 
0799 int ksz9477_port_mirror_add(struct ksz_device *dev, int port,
0800                 struct dsa_mall_mirror_tc_entry *mirror,
0801                 bool ingress, struct netlink_ext_ack *extack)
0802 {
0803     u8 data;
0804     int p;
0805 
0806     /* Limit to one sniffer port
0807      * Check if any of the port is already set for sniffing
0808      * If yes, instruct the user to remove the previous entry & exit
0809      */
0810     for (p = 0; p < dev->info->port_cnt; p++) {
0811         /* Skip the current sniffing port */
0812         if (p == mirror->to_local_port)
0813             continue;
0814 
0815         ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
0816 
0817         if (data & PORT_MIRROR_SNIFFER) {
0818             NL_SET_ERR_MSG_MOD(extack,
0819                        "Sniffer port is already configured, delete existing rules & retry");
0820             return -EBUSY;
0821         }
0822     }
0823 
0824     if (ingress)
0825         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
0826     else
0827         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
0828 
0829     /* configure mirror port */
0830     ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
0831              PORT_MIRROR_SNIFFER, true);
0832 
0833     ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
0834 
0835     return 0;
0836 }
0837 
0838 void ksz9477_port_mirror_del(struct ksz_device *dev, int port,
0839                  struct dsa_mall_mirror_tc_entry *mirror)
0840 {
0841     bool in_use = false;
0842     u8 data;
0843     int p;
0844 
0845     if (mirror->ingress)
0846         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
0847     else
0848         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
0849 
0850 
0851     /* Check if any of the port is still referring to sniffer port */
0852     for (p = 0; p < dev->info->port_cnt; p++) {
0853         ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
0854 
0855         if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) {
0856             in_use = true;
0857             break;
0858         }
0859     }
0860 
0861     /* delete sniffing if there are no other mirroring rules */
0862     if (!in_use)
0863         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
0864                  PORT_MIRROR_SNIFFER, false);
0865 }
0866 
0867 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
0868 {
0869     phy_interface_t interface;
0870     bool gbit;
0871 
0872     if (port < dev->phy_port_cnt)
0873         return PHY_INTERFACE_MODE_NA;
0874 
0875     gbit = ksz_get_gbit(dev, port);
0876 
0877     interface = ksz_get_xmii(dev, port, gbit);
0878 
0879     return interface;
0880 }
0881 
0882 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
0883                    u8 dev_addr, u16 reg_addr, u16 val)
0884 {
0885     ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
0886              MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
0887     ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
0888     ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
0889              MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
0890     ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
0891 }
0892 
0893 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
0894 {
0895     /* Apply PHY settings to address errata listed in
0896      * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
0897      * Silicon Errata and Data Sheet Clarification documents:
0898      *
0899      * Register settings are needed to improve PHY receive performance
0900      */
0901     ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
0902     ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
0903     ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
0904     ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
0905     ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
0906     ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
0907     ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
0908 
0909     /* Transmit waveform amplitude can be improved
0910      * (1000BASE-T, 100BASE-TX, 10BASE-Te)
0911      */
0912     ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
0913 
0914     /* Energy Efficient Ethernet (EEE) feature select must
0915      * be manually disabled (except on KSZ8565 which is 100Mbit)
0916      */
0917     if (dev->features & GBIT_SUPPORT)
0918         ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
0919 
0920     /* Register settings are required to meet data sheet
0921      * supply current specifications
0922      */
0923     ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
0924     ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
0925     ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
0926     ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
0927     ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
0928     ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
0929     ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
0930     ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
0931     ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
0932     ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
0933     ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
0934     ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
0935     ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
0936 }
0937 
0938 void ksz9477_get_caps(struct ksz_device *dev, int port,
0939               struct phylink_config *config)
0940 {
0941     config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
0942                    MAC_SYM_PAUSE;
0943 
0944     if (dev->features & GBIT_SUPPORT)
0945         config->mac_capabilities |= MAC_1000FD;
0946 }
0947 
0948 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
0949 {
0950     struct dsa_switch *ds = dev->ds;
0951     u16 data16;
0952     u8 member;
0953 
0954     /* enable tag tail for host port */
0955     if (cpu_port)
0956         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
0957                  true);
0958 
0959     ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
0960 
0961     /* set back pressure */
0962     ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
0963 
0964     /* enable broadcast storm limit */
0965     ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
0966 
0967     /* disable DiffServ priority */
0968     ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
0969 
0970     /* replace priority */
0971     ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
0972              false);
0973     ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
0974                MTI_PVID_REPLACE, false);
0975 
0976     /* enable 802.1p priority */
0977     ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
0978 
0979     if (port < dev->phy_port_cnt) {
0980         /* do not force flow control */
0981         ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
0982                  PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
0983                  false);
0984 
0985         if (dev->info->phy_errata_9477)
0986             ksz9477_phy_errata_setup(dev, port);
0987     } else {
0988         /* force flow control */
0989         ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
0990                  PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
0991                  true);
0992     }
0993 
0994     if (cpu_port)
0995         member = dsa_user_ports(ds);
0996     else
0997         member = BIT(dsa_upstream_port(ds, port));
0998 
0999     ksz9477_cfg_port_member(dev, port, member);
1000 
1001     /* clear pending interrupts */
1002     if (port < dev->phy_port_cnt)
1003         ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1004 }
1005 
1006 void ksz9477_config_cpu_port(struct dsa_switch *ds)
1007 {
1008     struct ksz_device *dev = ds->priv;
1009     struct ksz_port *p;
1010     int i;
1011 
1012     for (i = 0; i < dev->info->port_cnt; i++) {
1013         if (dsa_is_cpu_port(ds, i) &&
1014             (dev->info->cpu_ports & (1 << i))) {
1015             phy_interface_t interface;
1016             const char *prev_msg;
1017             const char *prev_mode;
1018 
1019             dev->cpu_port = i;
1020             p = &dev->ports[i];
1021 
1022             /* Read from XMII register to determine host port
1023              * interface.  If set specifically in device tree
1024              * note the difference to help debugging.
1025              */
1026             interface = ksz9477_get_interface(dev, i);
1027             if (!p->interface) {
1028                 if (dev->compat_interface) {
1029                     dev_warn(dev->dev,
1030                          "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1031                          "Please update your device tree.\n",
1032                          i);
1033                     p->interface = dev->compat_interface;
1034                 } else {
1035                     p->interface = interface;
1036                 }
1037             }
1038             if (interface && interface != p->interface) {
1039                 prev_msg = " instead of ";
1040                 prev_mode = phy_modes(interface);
1041             } else {
1042                 prev_msg = "";
1043                 prev_mode = "";
1044             }
1045             dev_info(dev->dev,
1046                  "Port%d: using phy mode %s%s%s\n",
1047                  i,
1048                  phy_modes(p->interface),
1049                  prev_msg,
1050                  prev_mode);
1051 
1052             /* enable cpu port */
1053             ksz9477_port_setup(dev, i, true);
1054             p->on = 1;
1055         }
1056     }
1057 
1058     for (i = 0; i < dev->info->port_cnt; i++) {
1059         if (i == dev->cpu_port)
1060             continue;
1061         p = &dev->ports[i];
1062 
1063         ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1064         p->on = 1;
1065         if (i < dev->phy_port_cnt)
1066             p->phy = 1;
1067         if (dev->chip_id == 0x00947700 && i == 6) {
1068             p->sgmii = 1;
1069 
1070             /* SGMII PHY detection code is not implemented yet. */
1071             p->phy = 0;
1072         }
1073     }
1074 }
1075 
1076 int ksz9477_enable_stp_addr(struct ksz_device *dev)
1077 {
1078     const u32 *masks;
1079     u32 data;
1080     int ret;
1081 
1082     masks = dev->info->masks;
1083 
1084     /* Enable Reserved multicast table */
1085     ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true);
1086 
1087     /* Set the Override bit for forwarding BPDU packet to CPU */
1088     ret = ksz_write32(dev, REG_SW_ALU_VAL_B,
1089               ALU_V_OVERRIDE | BIT(dev->cpu_port));
1090     if (ret < 0)
1091         return ret;
1092 
1093     data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE];
1094 
1095     ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
1096     if (ret < 0)
1097         return ret;
1098 
1099     /* wait to be finished */
1100     ret = ksz9477_wait_alu_sta_ready(dev);
1101     if (ret < 0) {
1102         dev_err(dev->dev, "Failed to update Reserved Multicast table\n");
1103         return ret;
1104     }
1105 
1106     return 0;
1107 }
1108 
1109 int ksz9477_setup(struct dsa_switch *ds)
1110 {
1111     struct ksz_device *dev = ds->priv;
1112     int ret = 0;
1113 
1114     /* Required for port partitioning. */
1115     ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1116               true);
1117 
1118     /* Do not work correctly with tail tagging. */
1119     ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1120 
1121     /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */
1122     ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true);
1123 
1124     /* Now we can configure default MTU value */
1125     ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK,
1126                  VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1127     if (ret)
1128         return ret;
1129 
1130     /* queue based egress rate limit */
1131     ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1132 
1133     /* enable global MIB counter freeze function */
1134     ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1135 
1136     return 0;
1137 }
1138 
1139 u32 ksz9477_get_port_addr(int port, int offset)
1140 {
1141     return PORT_CTRL_ADDR(port, offset);
1142 }
1143 
1144 int ksz9477_switch_init(struct ksz_device *dev)
1145 {
1146     u8 data8;
1147     int ret;
1148 
1149     dev->port_mask = (1 << dev->info->port_cnt) - 1;
1150 
1151     /* turn off SPI DO Edge select */
1152     ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1153     if (ret)
1154         return ret;
1155 
1156     data8 &= ~SPI_AUTO_EDGE_DETECTION;
1157     ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1158     if (ret)
1159         return ret;
1160 
1161     ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1162     if (ret)
1163         return ret;
1164 
1165     /* Number of ports can be reduced depending on chip. */
1166     dev->phy_port_cnt = 5;
1167 
1168     /* Default capability is gigabit capable. */
1169     dev->features = GBIT_SUPPORT;
1170 
1171     if (dev->chip_id == KSZ9893_CHIP_ID) {
1172         dev->features |= IS_9893;
1173 
1174         /* Chip does not support gigabit. */
1175         if (data8 & SW_QW_ABLE)
1176             dev->features &= ~GBIT_SUPPORT;
1177         dev->phy_port_cnt = 2;
1178     } else {
1179         /* Chip does not support gigabit. */
1180         if (!(data8 & SW_GIGABIT_ABLE))
1181             dev->features &= ~GBIT_SUPPORT;
1182     }
1183 
1184     return 0;
1185 }
1186 
1187 void ksz9477_switch_exit(struct ksz_device *dev)
1188 {
1189     ksz9477_reset_switch(dev);
1190 }
1191 
1192 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1193 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1194 MODULE_LICENSE("GPL");
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