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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip KSZ8795 switch driver
0004  *
0005  * Copyright (C) 2017 Microchip Technology Inc.
0006  *  Tristram Ha <Tristram.Ha@microchip.com>
0007  */
0008 
0009 #include <linux/bitfield.h>
0010 #include <linux/delay.h>
0011 #include <linux/export.h>
0012 #include <linux/gpio.h>
0013 #include <linux/if_vlan.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_data/microchip-ksz.h>
0017 #include <linux/phy.h>
0018 #include <linux/etherdevice.h>
0019 #include <linux/if_bridge.h>
0020 #include <linux/micrel_phy.h>
0021 #include <net/dsa.h>
0022 #include <net/switchdev.h>
0023 #include <linux/phylink.h>
0024 
0025 #include "ksz_common.h"
0026 #include "ksz8795_reg.h"
0027 #include "ksz8.h"
0028 
0029 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
0030 {
0031     regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
0032 }
0033 
0034 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
0035              bool set)
0036 {
0037     regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
0038                bits, set ? bits : 0);
0039 }
0040 
0041 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
0042 {
0043     const u16 *regs;
0044     u16 ctrl_addr;
0045     int ret = 0;
0046 
0047     regs = dev->info->regs;
0048 
0049     mutex_lock(&dev->alu_mutex);
0050 
0051     ctrl_addr = IND_ACC_TABLE(table) | addr;
0052     ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
0053     if (!ret)
0054         ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0055 
0056     mutex_unlock(&dev->alu_mutex);
0057 
0058     return ret;
0059 }
0060 
0061 int ksz8_reset_switch(struct ksz_device *dev)
0062 {
0063     if (ksz_is_ksz88x3(dev)) {
0064         /* reset switch */
0065         ksz_cfg(dev, KSZ8863_REG_SW_RESET,
0066             KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
0067         ksz_cfg(dev, KSZ8863_REG_SW_RESET,
0068             KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
0069     } else {
0070         /* reset switch */
0071         ksz_write8(dev, REG_POWER_MANAGEMENT_1,
0072                SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
0073         ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
0074     }
0075 
0076     return 0;
0077 }
0078 
0079 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
0080 {
0081     u8 hi, lo;
0082 
0083     /* Number of queues can only be 1, 2, or 4. */
0084     switch (queue) {
0085     case 4:
0086     case 3:
0087         queue = PORT_QUEUE_SPLIT_4;
0088         break;
0089     case 2:
0090         queue = PORT_QUEUE_SPLIT_2;
0091         break;
0092     default:
0093         queue = PORT_QUEUE_SPLIT_1;
0094     }
0095     ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
0096     ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
0097     lo &= ~PORT_QUEUE_SPLIT_L;
0098     if (queue & PORT_QUEUE_SPLIT_2)
0099         lo |= PORT_QUEUE_SPLIT_L;
0100     hi &= ~PORT_QUEUE_SPLIT_H;
0101     if (queue & PORT_QUEUE_SPLIT_4)
0102         hi |= PORT_QUEUE_SPLIT_H;
0103     ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
0104     ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
0105 
0106     /* Default is port based for egress rate limit. */
0107     if (queue != PORT_QUEUE_SPLIT_1)
0108         ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
0109             true);
0110 }
0111 
0112 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
0113 {
0114     const u32 *masks;
0115     const u16 *regs;
0116     u16 ctrl_addr;
0117     u32 data;
0118     u8 check;
0119     int loop;
0120 
0121     masks = dev->info->masks;
0122     regs = dev->info->regs;
0123 
0124     ctrl_addr = addr + dev->info->reg_mib_cnt * port;
0125     ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
0126 
0127     mutex_lock(&dev->alu_mutex);
0128     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0129 
0130     /* It is almost guaranteed to always read the valid bit because of
0131      * slow SPI speed.
0132      */
0133     for (loop = 2; loop > 0; loop--) {
0134         ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
0135 
0136         if (check & masks[MIB_COUNTER_VALID]) {
0137             ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
0138             if (check & masks[MIB_COUNTER_OVERFLOW])
0139                 *cnt += MIB_COUNTER_VALUE + 1;
0140             *cnt += data & MIB_COUNTER_VALUE;
0141             break;
0142         }
0143     }
0144     mutex_unlock(&dev->alu_mutex);
0145 }
0146 
0147 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
0148                   u64 *dropped, u64 *cnt)
0149 {
0150     const u32 *masks;
0151     const u16 *regs;
0152     u16 ctrl_addr;
0153     u32 data;
0154     u8 check;
0155     int loop;
0156 
0157     masks = dev->info->masks;
0158     regs = dev->info->regs;
0159 
0160     addr -= dev->info->reg_mib_cnt;
0161     ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
0162     ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
0163     ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
0164 
0165     mutex_lock(&dev->alu_mutex);
0166     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0167 
0168     /* It is almost guaranteed to always read the valid bit because of
0169      * slow SPI speed.
0170      */
0171     for (loop = 2; loop > 0; loop--) {
0172         ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
0173 
0174         if (check & masks[MIB_COUNTER_VALID]) {
0175             ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
0176             if (addr < 2) {
0177                 u64 total;
0178 
0179                 total = check & MIB_TOTAL_BYTES_H;
0180                 total <<= 32;
0181                 *cnt += total;
0182                 *cnt += data;
0183                 if (check & masks[MIB_COUNTER_OVERFLOW]) {
0184                     total = MIB_TOTAL_BYTES_H + 1;
0185                     total <<= 32;
0186                     *cnt += total;
0187                 }
0188             } else {
0189                 if (check & masks[MIB_COUNTER_OVERFLOW])
0190                     *cnt += MIB_PACKET_DROPPED + 1;
0191                 *cnt += data & MIB_PACKET_DROPPED;
0192             }
0193             break;
0194         }
0195     }
0196     mutex_unlock(&dev->alu_mutex);
0197 }
0198 
0199 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
0200                   u64 *dropped, u64 *cnt)
0201 {
0202     u32 *last = (u32 *)dropped;
0203     const u16 *regs;
0204     u16 ctrl_addr;
0205     u32 data;
0206     u32 cur;
0207 
0208     regs = dev->info->regs;
0209 
0210     addr -= dev->info->reg_mib_cnt;
0211     ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
0212                KSZ8863_MIB_PACKET_DROPPED_RX_0;
0213     ctrl_addr += port;
0214     ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
0215 
0216     mutex_lock(&dev->alu_mutex);
0217     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0218     ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
0219     mutex_unlock(&dev->alu_mutex);
0220 
0221     data &= MIB_PACKET_DROPPED;
0222     cur = last[addr];
0223     if (data != cur) {
0224         last[addr] = data;
0225         if (data < cur)
0226             data += MIB_PACKET_DROPPED + 1;
0227         data -= cur;
0228         *cnt += data;
0229     }
0230 }
0231 
0232 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
0233             u64 *dropped, u64 *cnt)
0234 {
0235     if (ksz_is_ksz88x3(dev))
0236         ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
0237     else
0238         ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
0239 }
0240 
0241 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
0242 {
0243     if (ksz_is_ksz88x3(dev))
0244         return;
0245 
0246     /* enable the port for flush/freeze function */
0247     if (freeze)
0248         ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
0249     ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
0250 
0251     /* disable the port after freeze is done */
0252     if (!freeze)
0253         ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
0254 }
0255 
0256 void ksz8_port_init_cnt(struct ksz_device *dev, int port)
0257 {
0258     struct ksz_port_mib *mib = &dev->ports[port].mib;
0259     u64 *dropped;
0260 
0261     if (!ksz_is_ksz88x3(dev)) {
0262         /* flush all enabled port MIB counters */
0263         ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
0264         ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
0265         ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
0266     }
0267 
0268     mib->cnt_ptr = 0;
0269 
0270     /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
0271     while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
0272         dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
0273                     &mib->counters[mib->cnt_ptr]);
0274         ++mib->cnt_ptr;
0275     }
0276 
0277     /* last one in storage */
0278     dropped = &mib->counters[dev->info->mib_cnt];
0279 
0280     /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
0281     while (mib->cnt_ptr < dev->info->mib_cnt) {
0282         dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
0283                     dropped, &mib->counters[mib->cnt_ptr]);
0284         ++mib->cnt_ptr;
0285     }
0286 }
0287 
0288 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
0289 {
0290     const u16 *regs;
0291     u16 ctrl_addr;
0292 
0293     regs = dev->info->regs;
0294 
0295     ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
0296 
0297     mutex_lock(&dev->alu_mutex);
0298     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0299     ksz_read64(dev, regs[REG_IND_DATA_HI], data);
0300     mutex_unlock(&dev->alu_mutex);
0301 }
0302 
0303 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
0304 {
0305     const u16 *regs;
0306     u16 ctrl_addr;
0307 
0308     regs = dev->info->regs;
0309 
0310     ctrl_addr = IND_ACC_TABLE(table) | addr;
0311 
0312     mutex_lock(&dev->alu_mutex);
0313     ksz_write64(dev, regs[REG_IND_DATA_HI], data);
0314     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0315     mutex_unlock(&dev->alu_mutex);
0316 }
0317 
0318 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
0319 {
0320     int timeout = 100;
0321     const u32 *masks;
0322     const u16 *regs;
0323 
0324     masks = dev->info->masks;
0325     regs = dev->info->regs;
0326 
0327     do {
0328         ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
0329         timeout--;
0330     } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
0331 
0332     /* Entry is not ready for accessing. */
0333     if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
0334         return -EAGAIN;
0335     /* Entry is ready for accessing. */
0336     } else {
0337         ksz_read8(dev, regs[REG_IND_DATA_8], data);
0338 
0339         /* There is no valid entry in the table. */
0340         if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
0341             return -ENXIO;
0342     }
0343     return 0;
0344 }
0345 
0346 int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
0347              u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries)
0348 {
0349     u32 data_hi, data_lo;
0350     const u8 *shifts;
0351     const u32 *masks;
0352     const u16 *regs;
0353     u16 ctrl_addr;
0354     u8 data;
0355     int rc;
0356 
0357     shifts = dev->info->shifts;
0358     masks = dev->info->masks;
0359     regs = dev->info->regs;
0360 
0361     ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
0362 
0363     mutex_lock(&dev->alu_mutex);
0364     ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
0365 
0366     rc = ksz8_valid_dyn_entry(dev, &data);
0367     if (rc == -EAGAIN) {
0368         if (addr == 0)
0369             *entries = 0;
0370     } else if (rc == -ENXIO) {
0371         *entries = 0;
0372     /* At least one valid entry in the table. */
0373     } else {
0374         u64 buf = 0;
0375         int cnt;
0376 
0377         ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
0378         data_hi = (u32)(buf >> 32);
0379         data_lo = (u32)buf;
0380 
0381         /* Check out how many valid entry in the table. */
0382         cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
0383         cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
0384         cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
0385             shifts[DYNAMIC_MAC_ENTRIES];
0386         *entries = cnt + 1;
0387 
0388         *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
0389             shifts[DYNAMIC_MAC_FID];
0390         *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
0391             shifts[DYNAMIC_MAC_SRC_PORT];
0392         *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
0393             shifts[DYNAMIC_MAC_TIMESTAMP];
0394 
0395         mac_addr[5] = (u8)data_lo;
0396         mac_addr[4] = (u8)(data_lo >> 8);
0397         mac_addr[3] = (u8)(data_lo >> 16);
0398         mac_addr[2] = (u8)(data_lo >> 24);
0399 
0400         mac_addr[1] = (u8)data_hi;
0401         mac_addr[0] = (u8)(data_hi >> 8);
0402         rc = 0;
0403     }
0404     mutex_unlock(&dev->alu_mutex);
0405 
0406     return rc;
0407 }
0408 
0409 int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
0410              struct alu_struct *alu)
0411 {
0412     u32 data_hi, data_lo;
0413     const u8 *shifts;
0414     const u32 *masks;
0415     u64 data;
0416 
0417     shifts = dev->info->shifts;
0418     masks = dev->info->masks;
0419 
0420     ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
0421     data_hi = data >> 32;
0422     data_lo = (u32)data;
0423     if (data_hi & (masks[STATIC_MAC_TABLE_VALID] |
0424             masks[STATIC_MAC_TABLE_OVERRIDE])) {
0425         alu->mac[5] = (u8)data_lo;
0426         alu->mac[4] = (u8)(data_lo >> 8);
0427         alu->mac[3] = (u8)(data_lo >> 16);
0428         alu->mac[2] = (u8)(data_lo >> 24);
0429         alu->mac[1] = (u8)data_hi;
0430         alu->mac[0] = (u8)(data_hi >> 8);
0431         alu->port_forward =
0432             (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
0433                 shifts[STATIC_MAC_FWD_PORTS];
0434         alu->is_override =
0435             (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
0436         data_hi >>= 1;
0437         alu->is_static = true;
0438         alu->is_use_fid =
0439             (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
0440         alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
0441                 shifts[STATIC_MAC_FID];
0442         return 0;
0443     }
0444     return -ENXIO;
0445 }
0446 
0447 void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
0448               struct alu_struct *alu)
0449 {
0450     u32 data_hi, data_lo;
0451     const u8 *shifts;
0452     const u32 *masks;
0453     u64 data;
0454 
0455     shifts = dev->info->shifts;
0456     masks = dev->info->masks;
0457 
0458     data_lo = ((u32)alu->mac[2] << 24) |
0459         ((u32)alu->mac[3] << 16) |
0460         ((u32)alu->mac[4] << 8) | alu->mac[5];
0461     data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
0462     data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
0463 
0464     if (alu->is_override)
0465         data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
0466     if (alu->is_use_fid) {
0467         data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
0468         data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
0469     }
0470     if (alu->is_static)
0471         data_hi |= masks[STATIC_MAC_TABLE_VALID];
0472     else
0473         data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
0474 
0475     data = (u64)data_hi << 32 | data_lo;
0476     ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
0477 }
0478 
0479 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
0480                u8 *member, u8 *valid)
0481 {
0482     const u8 *shifts;
0483     const u32 *masks;
0484 
0485     shifts = dev->info->shifts;
0486     masks = dev->info->masks;
0487 
0488     *fid = vlan & masks[VLAN_TABLE_FID];
0489     *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
0490             shifts[VLAN_TABLE_MEMBERSHIP_S];
0491     *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
0492 }
0493 
0494 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
0495              u16 *vlan)
0496 {
0497     const u8 *shifts;
0498     const u32 *masks;
0499 
0500     shifts = dev->info->shifts;
0501     masks = dev->info->masks;
0502 
0503     *vlan = fid;
0504     *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
0505     if (valid)
0506         *vlan |= masks[VLAN_TABLE_VALID];
0507 }
0508 
0509 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
0510 {
0511     const u8 *shifts;
0512     u64 data;
0513     int i;
0514 
0515     shifts = dev->info->shifts;
0516 
0517     ksz8_r_table(dev, TABLE_VLAN, addr, &data);
0518     addr *= 4;
0519     for (i = 0; i < 4; i++) {
0520         dev->vlan_cache[addr + i].table[0] = (u16)data;
0521         data >>= shifts[VLAN_TABLE];
0522     }
0523 }
0524 
0525 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
0526 {
0527     int index;
0528     u16 *data;
0529     u16 addr;
0530     u64 buf;
0531 
0532     data = (u16 *)&buf;
0533     addr = vid / 4;
0534     index = vid & 3;
0535     ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
0536     *vlan = data[index];
0537 }
0538 
0539 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
0540 {
0541     int index;
0542     u16 *data;
0543     u16 addr;
0544     u64 buf;
0545 
0546     data = (u16 *)&buf;
0547     addr = vid / 4;
0548     index = vid & 3;
0549     ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
0550     data[index] = vlan;
0551     dev->vlan_cache[vid].table[0] = vlan;
0552     ksz8_w_table(dev, TABLE_VLAN, addr, buf);
0553 }
0554 
0555 void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
0556 {
0557     u8 restart, speed, ctrl, link;
0558     int processed = true;
0559     const u16 *regs;
0560     u8 val1, val2;
0561     u16 data = 0;
0562     u8 p = phy;
0563 
0564     regs = dev->info->regs;
0565 
0566     switch (reg) {
0567     case MII_BMCR:
0568         ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
0569         ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
0570         ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
0571         if (restart & PORT_PHY_LOOPBACK)
0572             data |= BMCR_LOOPBACK;
0573         if (ctrl & PORT_FORCE_100_MBIT)
0574             data |= BMCR_SPEED100;
0575         if (ksz_is_ksz88x3(dev)) {
0576             if ((ctrl & PORT_AUTO_NEG_ENABLE))
0577                 data |= BMCR_ANENABLE;
0578         } else {
0579             if (!(ctrl & PORT_AUTO_NEG_DISABLE))
0580                 data |= BMCR_ANENABLE;
0581         }
0582         if (restart & PORT_POWER_DOWN)
0583             data |= BMCR_PDOWN;
0584         if (restart & PORT_AUTO_NEG_RESTART)
0585             data |= BMCR_ANRESTART;
0586         if (ctrl & PORT_FORCE_FULL_DUPLEX)
0587             data |= BMCR_FULLDPLX;
0588         if (speed & PORT_HP_MDIX)
0589             data |= KSZ886X_BMCR_HP_MDIX;
0590         if (restart & PORT_FORCE_MDIX)
0591             data |= KSZ886X_BMCR_FORCE_MDI;
0592         if (restart & PORT_AUTO_MDIX_DISABLE)
0593             data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
0594         if (restart & PORT_TX_DISABLE)
0595             data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
0596         if (restart & PORT_LED_OFF)
0597             data |= KSZ886X_BMCR_DISABLE_LED;
0598         break;
0599     case MII_BMSR:
0600         ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
0601         data = BMSR_100FULL |
0602                BMSR_100HALF |
0603                BMSR_10FULL |
0604                BMSR_10HALF |
0605                BMSR_ANEGCAPABLE;
0606         if (link & PORT_AUTO_NEG_COMPLETE)
0607             data |= BMSR_ANEGCOMPLETE;
0608         if (link & PORT_STAT_LINK_GOOD)
0609             data |= BMSR_LSTATUS;
0610         break;
0611     case MII_PHYSID1:
0612         data = KSZ8795_ID_HI;
0613         break;
0614     case MII_PHYSID2:
0615         if (ksz_is_ksz88x3(dev))
0616             data = KSZ8863_ID_LO;
0617         else
0618             data = KSZ8795_ID_LO;
0619         break;
0620     case MII_ADVERTISE:
0621         ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
0622         data = ADVERTISE_CSMA;
0623         if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
0624             data |= ADVERTISE_PAUSE_CAP;
0625         if (ctrl & PORT_AUTO_NEG_100BTX_FD)
0626             data |= ADVERTISE_100FULL;
0627         if (ctrl & PORT_AUTO_NEG_100BTX)
0628             data |= ADVERTISE_100HALF;
0629         if (ctrl & PORT_AUTO_NEG_10BT_FD)
0630             data |= ADVERTISE_10FULL;
0631         if (ctrl & PORT_AUTO_NEG_10BT)
0632             data |= ADVERTISE_10HALF;
0633         break;
0634     case MII_LPA:
0635         ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
0636         data = LPA_SLCT;
0637         if (link & PORT_REMOTE_SYM_PAUSE)
0638             data |= LPA_PAUSE_CAP;
0639         if (link & PORT_REMOTE_100BTX_FD)
0640             data |= LPA_100FULL;
0641         if (link & PORT_REMOTE_100BTX)
0642             data |= LPA_100HALF;
0643         if (link & PORT_REMOTE_10BT_FD)
0644             data |= LPA_10FULL;
0645         if (link & PORT_REMOTE_10BT)
0646             data |= LPA_10HALF;
0647         if (data & ~LPA_SLCT)
0648             data |= LPA_LPACK;
0649         break;
0650     case PHY_REG_LINK_MD:
0651         ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
0652         ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
0653         if (val1 & PORT_START_CABLE_DIAG)
0654             data |= PHY_START_CABLE_DIAG;
0655 
0656         if (val1 & PORT_CABLE_10M_SHORT)
0657             data |= PHY_CABLE_10M_SHORT;
0658 
0659         data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
0660                 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
0661 
0662         data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
0663                 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
0664                 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
0665         break;
0666     case PHY_REG_PHY_CTRL:
0667         ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
0668         if (link & PORT_MDIX_STATUS)
0669             data |= KSZ886X_CTRL_MDIX_STAT;
0670         break;
0671     default:
0672         processed = false;
0673         break;
0674     }
0675     if (processed)
0676         *val = data;
0677 }
0678 
0679 void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
0680 {
0681     u8 restart, speed, ctrl, data;
0682     const u16 *regs;
0683     u8 p = phy;
0684 
0685     regs = dev->info->regs;
0686 
0687     switch (reg) {
0688     case MII_BMCR:
0689 
0690         /* Do not support PHY reset function. */
0691         if (val & BMCR_RESET)
0692             break;
0693         ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
0694         data = speed;
0695         if (val & KSZ886X_BMCR_HP_MDIX)
0696             data |= PORT_HP_MDIX;
0697         else
0698             data &= ~PORT_HP_MDIX;
0699         if (data != speed)
0700             ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
0701         ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
0702         data = ctrl;
0703         if (ksz_is_ksz88x3(dev)) {
0704             if ((val & BMCR_ANENABLE))
0705                 data |= PORT_AUTO_NEG_ENABLE;
0706             else
0707                 data &= ~PORT_AUTO_NEG_ENABLE;
0708         } else {
0709             if (!(val & BMCR_ANENABLE))
0710                 data |= PORT_AUTO_NEG_DISABLE;
0711             else
0712                 data &= ~PORT_AUTO_NEG_DISABLE;
0713 
0714             /* Fiber port does not support auto-negotiation. */
0715             if (dev->ports[p].fiber)
0716                 data |= PORT_AUTO_NEG_DISABLE;
0717         }
0718 
0719         if (val & BMCR_SPEED100)
0720             data |= PORT_FORCE_100_MBIT;
0721         else
0722             data &= ~PORT_FORCE_100_MBIT;
0723         if (val & BMCR_FULLDPLX)
0724             data |= PORT_FORCE_FULL_DUPLEX;
0725         else
0726             data &= ~PORT_FORCE_FULL_DUPLEX;
0727         if (data != ctrl)
0728             ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
0729         ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
0730         data = restart;
0731         if (val & KSZ886X_BMCR_DISABLE_LED)
0732             data |= PORT_LED_OFF;
0733         else
0734             data &= ~PORT_LED_OFF;
0735         if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
0736             data |= PORT_TX_DISABLE;
0737         else
0738             data &= ~PORT_TX_DISABLE;
0739         if (val & BMCR_ANRESTART)
0740             data |= PORT_AUTO_NEG_RESTART;
0741         else
0742             data &= ~(PORT_AUTO_NEG_RESTART);
0743         if (val & BMCR_PDOWN)
0744             data |= PORT_POWER_DOWN;
0745         else
0746             data &= ~PORT_POWER_DOWN;
0747         if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
0748             data |= PORT_AUTO_MDIX_DISABLE;
0749         else
0750             data &= ~PORT_AUTO_MDIX_DISABLE;
0751         if (val & KSZ886X_BMCR_FORCE_MDI)
0752             data |= PORT_FORCE_MDIX;
0753         else
0754             data &= ~PORT_FORCE_MDIX;
0755         if (val & BMCR_LOOPBACK)
0756             data |= PORT_PHY_LOOPBACK;
0757         else
0758             data &= ~PORT_PHY_LOOPBACK;
0759         if (data != restart)
0760             ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data);
0761         break;
0762     case MII_ADVERTISE:
0763         ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
0764         data = ctrl;
0765         data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
0766               PORT_AUTO_NEG_100BTX_FD |
0767               PORT_AUTO_NEG_100BTX |
0768               PORT_AUTO_NEG_10BT_FD |
0769               PORT_AUTO_NEG_10BT);
0770         if (val & ADVERTISE_PAUSE_CAP)
0771             data |= PORT_AUTO_NEG_SYM_PAUSE;
0772         if (val & ADVERTISE_100FULL)
0773             data |= PORT_AUTO_NEG_100BTX_FD;
0774         if (val & ADVERTISE_100HALF)
0775             data |= PORT_AUTO_NEG_100BTX;
0776         if (val & ADVERTISE_10FULL)
0777             data |= PORT_AUTO_NEG_10BT_FD;
0778         if (val & ADVERTISE_10HALF)
0779             data |= PORT_AUTO_NEG_10BT;
0780         if (data != ctrl)
0781             ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
0782         break;
0783     case PHY_REG_LINK_MD:
0784         if (val & PHY_START_CABLE_DIAG)
0785             ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
0786         break;
0787     default:
0788         break;
0789     }
0790 }
0791 
0792 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
0793 {
0794     u8 data;
0795 
0796     ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
0797     data &= ~PORT_VLAN_MEMBERSHIP;
0798     data |= (member & dev->port_mask);
0799     ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
0800 }
0801 
0802 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
0803 {
0804     u8 learn[DSA_MAX_PORTS];
0805     int first, index, cnt;
0806     struct ksz_port *p;
0807     const u16 *regs;
0808 
0809     regs = dev->info->regs;
0810 
0811     if ((uint)port < dev->info->port_cnt) {
0812         first = port;
0813         cnt = port + 1;
0814     } else {
0815         /* Flush all ports. */
0816         first = 0;
0817         cnt = dev->info->port_cnt;
0818     }
0819     for (index = first; index < cnt; index++) {
0820         p = &dev->ports[index];
0821         if (!p->on)
0822             continue;
0823         ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
0824         if (!(learn[index] & PORT_LEARN_DISABLE))
0825             ksz_pwrite8(dev, index, regs[P_STP_CTRL],
0826                     learn[index] | PORT_LEARN_DISABLE);
0827     }
0828     ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
0829     for (index = first; index < cnt; index++) {
0830         p = &dev->ports[index];
0831         if (!p->on)
0832             continue;
0833         if (!(learn[index] & PORT_LEARN_DISABLE))
0834             ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
0835     }
0836 }
0837 
0838 int ksz8_fdb_dump(struct ksz_device *dev, int port,
0839           dsa_fdb_dump_cb_t *cb, void *data)
0840 {
0841     int ret = 0;
0842     u16 i = 0;
0843     u16 entries = 0;
0844     u8 timestamp = 0;
0845     u8 fid;
0846     u8 member;
0847     struct alu_struct alu;
0848 
0849     do {
0850         alu.is_static = false;
0851         ret = ksz8_r_dyn_mac_table(dev, i, alu.mac, &fid, &member,
0852                        &timestamp, &entries);
0853         if (!ret && (member & BIT(port))) {
0854             ret = cb(alu.mac, alu.fid, alu.is_static, data);
0855             if (ret)
0856                 break;
0857         }
0858         i++;
0859     } while (i < entries);
0860     if (i >= entries)
0861         ret = 0;
0862 
0863     return ret;
0864 }
0865 
0866 int ksz8_mdb_add(struct ksz_device *dev, int port,
0867          const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
0868 {
0869     struct alu_struct alu;
0870     int index;
0871     int empty = 0;
0872 
0873     alu.port_forward = 0;
0874     for (index = 0; index < dev->info->num_statics; index++) {
0875         if (!ksz8_r_sta_mac_table(dev, index, &alu)) {
0876             /* Found one already in static MAC table. */
0877             if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) &&
0878                 alu.fid == mdb->vid)
0879                 break;
0880         /* Remember the first empty entry. */
0881         } else if (!empty) {
0882             empty = index + 1;
0883         }
0884     }
0885 
0886     /* no available entry */
0887     if (index == dev->info->num_statics && !empty)
0888         return -ENOSPC;
0889 
0890     /* add entry */
0891     if (index == dev->info->num_statics) {
0892         index = empty - 1;
0893         memset(&alu, 0, sizeof(alu));
0894         memcpy(alu.mac, mdb->addr, ETH_ALEN);
0895         alu.is_static = true;
0896     }
0897     alu.port_forward |= BIT(port);
0898     if (mdb->vid) {
0899         alu.is_use_fid = true;
0900 
0901         /* Need a way to map VID to FID. */
0902         alu.fid = mdb->vid;
0903     }
0904     ksz8_w_sta_mac_table(dev, index, &alu);
0905 
0906     return 0;
0907 }
0908 
0909 int ksz8_mdb_del(struct ksz_device *dev, int port,
0910          const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
0911 {
0912     struct alu_struct alu;
0913     int index;
0914 
0915     for (index = 0; index < dev->info->num_statics; index++) {
0916         if (!ksz8_r_sta_mac_table(dev, index, &alu)) {
0917             /* Found one already in static MAC table. */
0918             if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) &&
0919                 alu.fid == mdb->vid)
0920                 break;
0921         }
0922     }
0923 
0924     /* no available entry */
0925     if (index == dev->info->num_statics)
0926         goto exit;
0927 
0928     /* clear port */
0929     alu.port_forward &= ~BIT(port);
0930     if (!alu.port_forward)
0931         alu.is_static = false;
0932     ksz8_w_sta_mac_table(dev, index, &alu);
0933 
0934 exit:
0935     return 0;
0936 }
0937 
0938 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
0939                  struct netlink_ext_ack *extack)
0940 {
0941     if (ksz_is_ksz88x3(dev))
0942         return -ENOTSUPP;
0943 
0944     /* Discard packets with VID not enabled on the switch */
0945     ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
0946 
0947     /* Discard packets with VID not enabled on the ingress port */
0948     for (port = 0; port < dev->phy_port_cnt; ++port)
0949         ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
0950                  flag);
0951 
0952     return 0;
0953 }
0954 
0955 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
0956 {
0957     if (ksz_is_ksz88x3(dev)) {
0958         ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
0959             0x03 << (4 - 2 * port), state);
0960     } else {
0961         ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
0962     }
0963 }
0964 
0965 int ksz8_port_vlan_add(struct ksz_device *dev, int port,
0966                const struct switchdev_obj_port_vlan *vlan,
0967                struct netlink_ext_ack *extack)
0968 {
0969     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
0970     struct ksz_port *p = &dev->ports[port];
0971     u16 data, new_pvid = 0;
0972     u8 fid, member, valid;
0973 
0974     if (ksz_is_ksz88x3(dev))
0975         return -ENOTSUPP;
0976 
0977     /* If a VLAN is added with untagged flag different from the
0978      * port's Remove Tag flag, we need to change the latter.
0979      * Ignore VID 0, which is always untagged.
0980      * Ignore CPU port, which will always be tagged.
0981      */
0982     if (untagged != p->remove_tag && vlan->vid != 0 &&
0983         port != dev->cpu_port) {
0984         unsigned int vid;
0985 
0986         /* Reject attempts to add a VLAN that requires the
0987          * Remove Tag flag to be changed, unless there are no
0988          * other VLANs currently configured.
0989          */
0990         for (vid = 1; vid < dev->info->num_vlans; ++vid) {
0991             /* Skip the VID we are going to add or reconfigure */
0992             if (vid == vlan->vid)
0993                 continue;
0994 
0995             ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
0996                        &fid, &member, &valid);
0997             if (valid && (member & BIT(port)))
0998                 return -EINVAL;
0999         }
1000 
1001         ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1002         p->remove_tag = untagged;
1003     }
1004 
1005     ksz8_r_vlan_table(dev, vlan->vid, &data);
1006     ksz8_from_vlan(dev, data, &fid, &member, &valid);
1007 
1008     /* First time to setup the VLAN entry. */
1009     if (!valid) {
1010         /* Need to find a way to map VID to FID. */
1011         fid = 1;
1012         valid = 1;
1013     }
1014     member |= BIT(port);
1015 
1016     ksz8_to_vlan(dev, fid, member, valid, &data);
1017     ksz8_w_vlan_table(dev, vlan->vid, data);
1018 
1019     /* change PVID */
1020     if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1021         new_pvid = vlan->vid;
1022 
1023     if (new_pvid) {
1024         u16 vid;
1025 
1026         ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1027         vid &= ~VLAN_VID_MASK;
1028         vid |= new_pvid;
1029         ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1030 
1031         ksz8_port_enable_pvid(dev, port, true);
1032     }
1033 
1034     return 0;
1035 }
1036 
1037 int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1038                const struct switchdev_obj_port_vlan *vlan)
1039 {
1040     u16 data, pvid;
1041     u8 fid, member, valid;
1042 
1043     if (ksz_is_ksz88x3(dev))
1044         return -ENOTSUPP;
1045 
1046     ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1047     pvid = pvid & 0xFFF;
1048 
1049     ksz8_r_vlan_table(dev, vlan->vid, &data);
1050     ksz8_from_vlan(dev, data, &fid, &member, &valid);
1051 
1052     member &= ~BIT(port);
1053 
1054     /* Invalidate the entry if no more member. */
1055     if (!member) {
1056         fid = 0;
1057         valid = 0;
1058     }
1059 
1060     ksz8_to_vlan(dev, fid, member, valid, &data);
1061     ksz8_w_vlan_table(dev, vlan->vid, data);
1062 
1063     if (pvid == vlan->vid)
1064         ksz8_port_enable_pvid(dev, port, false);
1065 
1066     return 0;
1067 }
1068 
1069 int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1070              struct dsa_mall_mirror_tc_entry *mirror,
1071              bool ingress, struct netlink_ext_ack *extack)
1072 {
1073     if (ingress) {
1074         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1075         dev->mirror_rx |= BIT(port);
1076     } else {
1077         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1078         dev->mirror_tx |= BIT(port);
1079     }
1080 
1081     ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1082 
1083     /* configure mirror port */
1084     if (dev->mirror_rx || dev->mirror_tx)
1085         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1086                  PORT_MIRROR_SNIFFER, true);
1087 
1088     return 0;
1089 }
1090 
1091 void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1092               struct dsa_mall_mirror_tc_entry *mirror)
1093 {
1094     u8 data;
1095 
1096     if (mirror->ingress) {
1097         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1098         dev->mirror_rx &= ~BIT(port);
1099     } else {
1100         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1101         dev->mirror_tx &= ~BIT(port);
1102     }
1103 
1104     ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1105 
1106     if (!dev->mirror_rx && !dev->mirror_tx)
1107         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1108                  PORT_MIRROR_SNIFFER, false);
1109 }
1110 
1111 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1112 {
1113     struct ksz_port *p = &dev->ports[port];
1114 
1115     if (!p->interface && dev->compat_interface) {
1116         dev_warn(dev->dev,
1117              "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1118              "Please update your device tree.\n",
1119              port);
1120         p->interface = dev->compat_interface;
1121     }
1122 }
1123 
1124 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1125 {
1126     struct dsa_switch *ds = dev->ds;
1127     const u32 *masks;
1128     u8 member;
1129 
1130     masks = dev->info->masks;
1131 
1132     /* enable broadcast storm limit */
1133     ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1134 
1135     if (!ksz_is_ksz88x3(dev))
1136         ksz8795_set_prio_queue(dev, port, 4);
1137 
1138     /* disable DiffServ priority */
1139     ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1140 
1141     /* replace priority */
1142     ksz_port_cfg(dev, port, P_802_1P_CTRL,
1143              masks[PORT_802_1P_REMAPPING], false);
1144 
1145     /* enable 802.1p priority */
1146     ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1147 
1148     if (cpu_port) {
1149         if (!ksz_is_ksz88x3(dev))
1150             ksz8795_cpu_interface_select(dev, port);
1151 
1152         member = dsa_user_ports(ds);
1153     } else {
1154         member = BIT(dsa_upstream_port(ds, port));
1155     }
1156 
1157     ksz8_cfg_port_member(dev, port, member);
1158 }
1159 
1160 void ksz8_config_cpu_port(struct dsa_switch *ds)
1161 {
1162     struct ksz_device *dev = ds->priv;
1163     struct ksz_port *p;
1164     const u32 *masks;
1165     const u16 *regs;
1166     u8 remote;
1167     int i;
1168 
1169     masks = dev->info->masks;
1170     regs = dev->info->regs;
1171 
1172     /* Switch marks the maximum frame with extra byte as oversize. */
1173     ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1174     ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1175 
1176     p = &dev->ports[dev->cpu_port];
1177     p->on = 1;
1178 
1179     ksz8_port_setup(dev, dev->cpu_port, true);
1180 
1181     for (i = 0; i < dev->phy_port_cnt; i++) {
1182         p = &dev->ports[i];
1183 
1184         ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1185 
1186         /* Last port may be disabled. */
1187         if (i == dev->phy_port_cnt)
1188             break;
1189         p->on = 1;
1190         p->phy = 1;
1191     }
1192     for (i = 0; i < dev->phy_port_cnt; i++) {
1193         p = &dev->ports[i];
1194         if (!p->on)
1195             continue;
1196         if (!ksz_is_ksz88x3(dev)) {
1197             ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1198             if (remote & KSZ8_PORT_FIBER_MODE)
1199                 p->fiber = 1;
1200         }
1201         if (p->fiber)
1202             ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1203                      PORT_FORCE_FLOW_CTRL, true);
1204         else
1205             ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1206                      PORT_FORCE_FLOW_CTRL, false);
1207     }
1208 }
1209 
1210 static int ksz8_handle_global_errata(struct dsa_switch *ds)
1211 {
1212     struct ksz_device *dev = ds->priv;
1213     int ret = 0;
1214 
1215     /* KSZ87xx Errata DS80000687C.
1216      * Module 2: Link drops with some EEE link partners.
1217      *   An issue with the EEE next page exchange between the
1218      *   KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1219      *   the link dropping.
1220      */
1221     if (dev->info->ksz87xx_eee_link_erratum)
1222         ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1223 
1224     return ret;
1225 }
1226 
1227 int ksz8_enable_stp_addr(struct ksz_device *dev)
1228 {
1229     struct alu_struct alu;
1230 
1231     /* Setup STP address for STP operation. */
1232     memset(&alu, 0, sizeof(alu));
1233     ether_addr_copy(alu.mac, eth_stp_addr);
1234     alu.is_static = true;
1235     alu.is_override = true;
1236     alu.port_forward = dev->info->cpu_ports;
1237 
1238     ksz8_w_sta_mac_table(dev, 0, &alu);
1239 
1240     return 0;
1241 }
1242 
1243 int ksz8_setup(struct dsa_switch *ds)
1244 {
1245     struct ksz_device *dev = ds->priv;
1246     int i;
1247 
1248     ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1249 
1250     /* Enable automatic fast aging when link changed detected. */
1251     ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1252 
1253     /* Enable aggressive back off algorithm in half duplex mode. */
1254     regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1255                SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1256 
1257     /*
1258      * Make sure unicast VLAN boundary is set as default and
1259      * enable no excessive collision drop.
1260      */
1261     regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1262                UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1263                UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1264 
1265     ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1266 
1267     ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1268 
1269     if (!ksz_is_ksz88x3(dev))
1270         ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1271 
1272     for (i = 0; i < (dev->info->num_vlans / 4); i++)
1273         ksz8_r_vlan_entries(dev, i);
1274 
1275     return ksz8_handle_global_errata(ds);
1276 }
1277 
1278 void ksz8_get_caps(struct ksz_device *dev, int port,
1279            struct phylink_config *config)
1280 {
1281     config->mac_capabilities = MAC_10 | MAC_100;
1282 
1283     /* Silicon Errata Sheet (DS80000830A):
1284      * "Port 1 does not respond to received flow control PAUSE frames"
1285      * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1286      * switches.
1287      */
1288     if (!ksz_is_ksz88x3(dev) || port)
1289         config->mac_capabilities |= MAC_SYM_PAUSE;
1290 
1291     /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1292     if (!ksz_is_ksz88x3(dev))
1293         config->mac_capabilities |= MAC_ASYM_PAUSE;
1294 }
1295 
1296 u32 ksz8_get_port_addr(int port, int offset)
1297 {
1298     return PORT_CTRL_ADDR(port, offset);
1299 }
1300 
1301 int ksz8_switch_init(struct ksz_device *dev)
1302 {
1303     dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1304     dev->phy_port_cnt = dev->info->port_cnt - 1;
1305     dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1306 
1307     /* We rely on software untagging on the CPU port, so that we
1308      * can support both tagged and untagged VLANs
1309      */
1310     dev->ds->untag_bridge_pvid = true;
1311 
1312     /* VLAN filtering is partly controlled by the global VLAN
1313      * Enable flag
1314      */
1315     dev->ds->vlan_filtering_is_global = true;
1316 
1317     return 0;
1318 }
1319 
1320 void ksz8_switch_exit(struct ksz_device *dev)
1321 {
1322     ksz8_reset_switch(dev);
1323 }
1324 
1325 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1326 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1327 MODULE_LICENSE("GPL");
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