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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Broadcom Starfighter 2 DSA switch driver
0004  *
0005  * Copyright (C) 2014, Broadcom Corporation
0006  */
0007 
0008 #include <linux/list.h>
0009 #include <linux/module.h>
0010 #include <linux/netdevice.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/phy.h>
0014 #include <linux/phy_fixed.h>
0015 #include <linux/phylink.h>
0016 #include <linux/mii.h>
0017 #include <linux/clk.h>
0018 #include <linux/of.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_address.h>
0021 #include <linux/of_net.h>
0022 #include <linux/of_mdio.h>
0023 #include <net/dsa.h>
0024 #include <linux/ethtool.h>
0025 #include <linux/if_bridge.h>
0026 #include <linux/brcmphy.h>
0027 #include <linux/etherdevice.h>
0028 #include <linux/platform_data/b53.h>
0029 
0030 #include "bcm_sf2.h"
0031 #include "bcm_sf2_regs.h"
0032 #include "b53/b53_priv.h"
0033 #include "b53/b53_regs.h"
0034 
0035 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
0036 {
0037     switch (priv->type) {
0038     case BCM4908_DEVICE_ID:
0039         switch (port) {
0040         case 7:
0041             return REG_RGMII_11_CNTRL;
0042         default:
0043             break;
0044         }
0045         break;
0046     default:
0047         switch (port) {
0048         case 0:
0049             return REG_RGMII_0_CNTRL;
0050         case 1:
0051             return REG_RGMII_1_CNTRL;
0052         case 2:
0053             return REG_RGMII_2_CNTRL;
0054         default:
0055             break;
0056         }
0057     }
0058 
0059     WARN_ONCE(1, "Unsupported port %d\n", port);
0060 
0061     /* RO fallback reg */
0062     return REG_SWITCH_STATUS;
0063 }
0064 
0065 static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
0066 {
0067     switch (port) {
0068     case 0:
0069         return REG_LED_0_CNTRL;
0070     case 1:
0071         return REG_LED_1_CNTRL;
0072     case 2:
0073         return REG_LED_2_CNTRL;
0074     }
0075 
0076     switch (priv->type) {
0077     case BCM4908_DEVICE_ID:
0078         switch (port) {
0079         case 3:
0080             return REG_LED_3_CNTRL;
0081         case 7:
0082             return REG_LED_4_CNTRL;
0083         default:
0084             break;
0085         }
0086         break;
0087     default:
0088         break;
0089     }
0090 
0091     WARN_ONCE(1, "Unsupported port %d\n", port);
0092 
0093     /* RO fallback reg */
0094     return REG_SWITCH_STATUS;
0095 }
0096 
0097 /* Return the number of active ports, not counting the IMP (CPU) port */
0098 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
0099 {
0100     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0101     unsigned int port, count = 0;
0102 
0103     for (port = 0; port < ds->num_ports; port++) {
0104         if (dsa_is_cpu_port(ds, port))
0105             continue;
0106         if (priv->port_sts[port].enabled)
0107             count++;
0108     }
0109 
0110     return count;
0111 }
0112 
0113 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
0114 {
0115     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0116     unsigned long new_rate;
0117     unsigned int ports_active;
0118     /* Frequenty in Mhz */
0119     static const unsigned long rate_table[] = {
0120         59220000,
0121         60820000,
0122         62500000,
0123         62500000,
0124     };
0125 
0126     ports_active = bcm_sf2_num_active_ports(ds);
0127     if (ports_active == 0 || !priv->clk_mdiv)
0128         return;
0129 
0130     /* If we overflow our table, just use the recommended operational
0131      * frequency
0132      */
0133     if (ports_active > ARRAY_SIZE(rate_table))
0134         new_rate = 90000000;
0135     else
0136         new_rate = rate_table[ports_active - 1];
0137     clk_set_rate(priv->clk_mdiv, new_rate);
0138 }
0139 
0140 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
0141 {
0142     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0143     unsigned int i;
0144     u32 reg, offset;
0145 
0146     /* Enable the port memories */
0147     reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
0148     reg &= ~P_TXQ_PSM_VDD(port);
0149     core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
0150 
0151     /* Enable forwarding */
0152     core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
0153 
0154     /* Enable IMP port in dumb mode */
0155     reg = core_readl(priv, CORE_SWITCH_CTRL);
0156     reg |= MII_DUMB_FWDG_EN;
0157     core_writel(priv, reg, CORE_SWITCH_CTRL);
0158 
0159     /* Configure Traffic Class to QoS mapping, allow each priority to map
0160      * to a different queue number
0161      */
0162     reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
0163     for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
0164         reg |= i << (PRT_TO_QID_SHIFT * i);
0165     core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
0166 
0167     b53_brcm_hdr_setup(ds, port);
0168 
0169     if (port == 8) {
0170         if (priv->type == BCM4908_DEVICE_ID ||
0171             priv->type == BCM7445_DEVICE_ID)
0172             offset = CORE_STS_OVERRIDE_IMP;
0173         else
0174             offset = CORE_STS_OVERRIDE_IMP2;
0175 
0176         /* Force link status for IMP port */
0177         reg = core_readl(priv, offset);
0178         reg |= (MII_SW_OR | LINK_STS);
0179         if (priv->type == BCM4908_DEVICE_ID)
0180             reg |= GMII_SPEED_UP_2G;
0181         else
0182             reg &= ~GMII_SPEED_UP_2G;
0183         core_writel(priv, reg, offset);
0184 
0185         /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
0186         reg = core_readl(priv, CORE_IMP_CTL);
0187         reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
0188         reg &= ~(RX_DIS | TX_DIS);
0189         core_writel(priv, reg, CORE_IMP_CTL);
0190     } else {
0191         reg = core_readl(priv, CORE_G_PCTL_PORT(port));
0192         reg &= ~(RX_DIS | TX_DIS);
0193         core_writel(priv, reg, CORE_G_PCTL_PORT(port));
0194     }
0195 
0196     priv->port_sts[port].enabled = true;
0197 }
0198 
0199 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
0200 {
0201     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0202     u32 reg;
0203 
0204     reg = reg_readl(priv, REG_SPHY_CNTRL);
0205     if (enable) {
0206         reg |= PHY_RESET;
0207         reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
0208         reg_writel(priv, reg, REG_SPHY_CNTRL);
0209         udelay(21);
0210         reg = reg_readl(priv, REG_SPHY_CNTRL);
0211         reg &= ~PHY_RESET;
0212     } else {
0213         reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
0214         reg_writel(priv, reg, REG_SPHY_CNTRL);
0215         mdelay(1);
0216         reg |= CK25_DIS;
0217     }
0218     reg_writel(priv, reg, REG_SPHY_CNTRL);
0219 
0220     /* Use PHY-driven LED signaling */
0221     if (!enable) {
0222         u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
0223 
0224         if (priv->type == BCM7278_DEVICE_ID ||
0225             priv->type == BCM7445_DEVICE_ID) {
0226             reg = reg_led_readl(priv, led_ctrl, 0);
0227             reg |= LED_CNTRL_SPDLNK_SRC_SEL;
0228             reg_led_writel(priv, reg, led_ctrl, 0);
0229         }
0230     }
0231 }
0232 
0233 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
0234                         int port)
0235 {
0236     unsigned int off;
0237 
0238     switch (port) {
0239     case 7:
0240         off = P7_IRQ_OFF;
0241         break;
0242     case 0:
0243         /* Port 0 interrupts are located on the first bank */
0244         intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
0245         return;
0246     default:
0247         off = P_IRQ_OFF(port);
0248         break;
0249     }
0250 
0251     intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
0252 }
0253 
0254 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
0255                          int port)
0256 {
0257     unsigned int off;
0258 
0259     switch (port) {
0260     case 7:
0261         off = P7_IRQ_OFF;
0262         break;
0263     case 0:
0264         /* Port 0 interrupts are located on the first bank */
0265         intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
0266         intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
0267         return;
0268     default:
0269         off = P_IRQ_OFF(port);
0270         break;
0271     }
0272 
0273     intrl2_1_mask_set(priv, P_IRQ_MASK(off));
0274     intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
0275 }
0276 
0277 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
0278                   struct phy_device *phy)
0279 {
0280     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0281     unsigned int i;
0282     u32 reg;
0283 
0284     if (!dsa_is_user_port(ds, port))
0285         return 0;
0286 
0287     priv->port_sts[port].enabled = true;
0288 
0289     bcm_sf2_recalc_clock(ds);
0290 
0291     /* Clear the memory power down */
0292     reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
0293     reg &= ~P_TXQ_PSM_VDD(port);
0294     core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
0295 
0296     /* Enable Broadcom tags for that port if requested */
0297     if (priv->brcm_tag_mask & BIT(port))
0298         b53_brcm_hdr_setup(ds, port);
0299 
0300     /* Configure Traffic Class to QoS mapping, allow each priority to map
0301      * to a different queue number
0302      */
0303     reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
0304     for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
0305         reg |= i << (PRT_TO_QID_SHIFT * i);
0306     core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
0307 
0308     /* Re-enable the GPHY and re-apply workarounds */
0309     if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
0310         bcm_sf2_gphy_enable_set(ds, true);
0311         if (phy) {
0312             /* if phy_stop() has been called before, phy
0313              * will be in halted state, and phy_start()
0314              * will call resume.
0315              *
0316              * the resume path does not configure back
0317              * autoneg settings, and since we hard reset
0318              * the phy manually here, we need to reset the
0319              * state machine also.
0320              */
0321             phy->state = PHY_READY;
0322             phy_init_hw(phy);
0323         }
0324     }
0325 
0326     /* Enable MoCA port interrupts to get notified */
0327     if (port == priv->moca_port)
0328         bcm_sf2_port_intr_enable(priv, port);
0329 
0330     /* Set per-queue pause threshold to 32 */
0331     core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
0332 
0333     /* Set ACB threshold to 24 */
0334     for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
0335         reg = acb_readl(priv, ACB_QUEUE_CFG(port *
0336                             SF2_NUM_EGRESS_QUEUES + i));
0337         reg &= ~XOFF_THRESHOLD_MASK;
0338         reg |= 24;
0339         acb_writel(priv, reg, ACB_QUEUE_CFG(port *
0340                             SF2_NUM_EGRESS_QUEUES + i));
0341     }
0342 
0343     return b53_enable_port(ds, port, phy);
0344 }
0345 
0346 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
0347 {
0348     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0349     u32 reg;
0350 
0351     /* Disable learning while in WoL mode */
0352     if (priv->wol_ports_mask & (1 << port)) {
0353         reg = core_readl(priv, CORE_DIS_LEARN);
0354         reg |= BIT(port);
0355         core_writel(priv, reg, CORE_DIS_LEARN);
0356         return;
0357     }
0358 
0359     if (port == priv->moca_port)
0360         bcm_sf2_port_intr_disable(priv, port);
0361 
0362     if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
0363         bcm_sf2_gphy_enable_set(ds, false);
0364 
0365     b53_disable_port(ds, port);
0366 
0367     /* Power down the port memory */
0368     reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
0369     reg |= P_TXQ_PSM_VDD(port);
0370     core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
0371 
0372     priv->port_sts[port].enabled = false;
0373 
0374     bcm_sf2_recalc_clock(ds);
0375 }
0376 
0377 
0378 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
0379                    int regnum, u16 val)
0380 {
0381     int ret = 0;
0382     u32 reg;
0383 
0384     reg = reg_readl(priv, REG_SWITCH_CNTRL);
0385     reg |= MDIO_MASTER_SEL;
0386     reg_writel(priv, reg, REG_SWITCH_CNTRL);
0387 
0388     /* Page << 8 | offset */
0389     reg = 0x70;
0390     reg <<= 2;
0391     core_writel(priv, addr, reg);
0392 
0393     /* Page << 8 | offset */
0394     reg = 0x80 << 8 | regnum << 1;
0395     reg <<= 2;
0396 
0397     if (op)
0398         ret = core_readl(priv, reg);
0399     else
0400         core_writel(priv, val, reg);
0401 
0402     reg = reg_readl(priv, REG_SWITCH_CNTRL);
0403     reg &= ~MDIO_MASTER_SEL;
0404     reg_writel(priv, reg, REG_SWITCH_CNTRL);
0405 
0406     return ret & 0xffff;
0407 }
0408 
0409 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
0410 {
0411     struct bcm_sf2_priv *priv = bus->priv;
0412 
0413     /* Intercept reads from Broadcom pseudo-PHY address, else, send
0414      * them to our master MDIO bus controller
0415      */
0416     if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
0417         return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
0418     else
0419         return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
0420 }
0421 
0422 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
0423                  u16 val)
0424 {
0425     struct bcm_sf2_priv *priv = bus->priv;
0426 
0427     /* Intercept writes to the Broadcom pseudo-PHY address, else,
0428      * send them to our master MDIO bus controller
0429      */
0430     if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
0431         return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
0432     else
0433         return mdiobus_write_nested(priv->master_mii_bus, addr,
0434                 regnum, val);
0435 }
0436 
0437 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
0438 {
0439     struct dsa_switch *ds = dev_id;
0440     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0441 
0442     priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
0443                 ~priv->irq0_mask;
0444     intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
0445 
0446     return IRQ_HANDLED;
0447 }
0448 
0449 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
0450 {
0451     struct dsa_switch *ds = dev_id;
0452     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0453 
0454     priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
0455                 ~priv->irq1_mask;
0456     intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
0457 
0458     if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
0459         priv->port_sts[7].link = true;
0460         dsa_port_phylink_mac_change(ds, 7, true);
0461     }
0462     if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
0463         priv->port_sts[7].link = false;
0464         dsa_port_phylink_mac_change(ds, 7, false);
0465     }
0466 
0467     return IRQ_HANDLED;
0468 }
0469 
0470 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
0471 {
0472     unsigned int timeout = 1000;
0473     u32 reg;
0474     int ret;
0475 
0476     /* The watchdog reset does not work on 7278, we need to hit the
0477      * "external" reset line through the reset controller.
0478      */
0479     if (priv->type == BCM7278_DEVICE_ID) {
0480         ret = reset_control_assert(priv->rcdev);
0481         if (ret)
0482             return ret;
0483 
0484         return reset_control_deassert(priv->rcdev);
0485     }
0486 
0487     reg = core_readl(priv, CORE_WATCHDOG_CTRL);
0488     reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
0489     core_writel(priv, reg, CORE_WATCHDOG_CTRL);
0490 
0491     do {
0492         reg = core_readl(priv, CORE_WATCHDOG_CTRL);
0493         if (!(reg & SOFTWARE_RESET))
0494             break;
0495 
0496         usleep_range(1000, 2000);
0497     } while (timeout-- > 0);
0498 
0499     if (timeout == 0)
0500         return -ETIMEDOUT;
0501 
0502     return 0;
0503 }
0504 
0505 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
0506 {
0507     struct device *dev = priv->dev->ds->dev;
0508     int shift;
0509     u32 mask;
0510     u32 reg;
0511     int i;
0512 
0513     mask = BIT(priv->num_crossbar_int_ports) - 1;
0514 
0515     reg = reg_readl(priv, REG_CROSSBAR);
0516     switch (priv->type) {
0517     case BCM4908_DEVICE_ID:
0518         shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
0519         reg &= ~(mask << shift);
0520         if (0) /* FIXME */
0521             reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
0522         else if (priv->int_phy_mask & BIT(7))
0523             reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
0524         else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
0525             reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
0526         else if (WARN(1, "Invalid port mode\n"))
0527             return;
0528         break;
0529     default:
0530         return;
0531     }
0532     reg_writel(priv, reg, REG_CROSSBAR);
0533 
0534     reg = reg_readl(priv, REG_CROSSBAR);
0535     for (i = 0; i < priv->num_crossbar_int_ports; i++) {
0536         shift = i * priv->num_crossbar_int_ports;
0537 
0538         dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
0539             (reg >> shift) & mask);
0540     }
0541 }
0542 
0543 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
0544 {
0545     intrl2_0_mask_set(priv, 0xffffffff);
0546     intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
0547     intrl2_1_mask_set(priv, 0xffffffff);
0548     intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
0549 }
0550 
0551 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
0552                    struct device_node *dn)
0553 {
0554     struct device *dev = priv->dev->ds->dev;
0555     struct bcm_sf2_port_status *port_st;
0556     struct device_node *port;
0557     unsigned int port_num;
0558     struct property *prop;
0559     int err;
0560 
0561     priv->moca_port = -1;
0562 
0563     for_each_available_child_of_node(dn, port) {
0564         if (of_property_read_u32(port, "reg", &port_num))
0565             continue;
0566 
0567         if (port_num >= DSA_MAX_PORTS) {
0568             dev_err(dev, "Invalid port number %d\n", port_num);
0569             continue;
0570         }
0571 
0572         port_st = &priv->port_sts[port_num];
0573 
0574         /* Internal PHYs get assigned a specific 'phy-mode' property
0575          * value: "internal" to help flag them before MDIO probing
0576          * has completed, since they might be turned off at that
0577          * time
0578          */
0579         err = of_get_phy_mode(port, &port_st->mode);
0580         if (err)
0581             continue;
0582 
0583         if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
0584             priv->int_phy_mask |= 1 << port_num;
0585 
0586         if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
0587             priv->moca_port = port_num;
0588 
0589         if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
0590             priv->brcm_tag_mask |= 1 << port_num;
0591 
0592         /* Ensure that port 5 is not picked up as a DSA CPU port
0593          * flavour but a regular port instead. We should be using
0594          * devlink to be able to set the port flavour.
0595          */
0596         if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
0597             prop = of_find_property(port, "ethernet", NULL);
0598             if (prop)
0599                 of_remove_property(port, prop);
0600         }
0601     }
0602 }
0603 
0604 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
0605 {
0606     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0607     struct device_node *dn, *child;
0608     struct phy_device *phydev;
0609     struct property *prop;
0610     static int index;
0611     int err, reg;
0612 
0613     /* Find our integrated MDIO bus node */
0614     dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
0615     priv->master_mii_bus = of_mdio_find_bus(dn);
0616     if (!priv->master_mii_bus) {
0617         of_node_put(dn);
0618         return -EPROBE_DEFER;
0619     }
0620 
0621     get_device(&priv->master_mii_bus->dev);
0622     priv->master_mii_dn = dn;
0623 
0624     priv->slave_mii_bus = mdiobus_alloc();
0625     if (!priv->slave_mii_bus) {
0626         of_node_put(dn);
0627         return -ENOMEM;
0628     }
0629 
0630     priv->slave_mii_bus->priv = priv;
0631     priv->slave_mii_bus->name = "sf2 slave mii";
0632     priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
0633     priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
0634     snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
0635          index++);
0636     priv->slave_mii_bus->dev.of_node = dn;
0637 
0638     /* Include the pseudo-PHY address to divert reads towards our
0639      * workaround. This is only required for 7445D0, since 7445E0
0640      * disconnects the internal switch pseudo-PHY such that we can use the
0641      * regular SWITCH_MDIO master controller instead.
0642      *
0643      * Here we flag the pseudo PHY as needing special treatment and would
0644      * otherwise make all other PHY read/writes go to the master MDIO bus
0645      * controller that comes with this switch backed by the "mdio-unimac"
0646      * driver.
0647      */
0648     if (of_machine_is_compatible("brcm,bcm7445d0"))
0649         priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
0650     else
0651         priv->indir_phy_mask = 0;
0652 
0653     ds->phys_mii_mask = priv->indir_phy_mask;
0654     ds->slave_mii_bus = priv->slave_mii_bus;
0655     priv->slave_mii_bus->parent = ds->dev->parent;
0656     priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
0657 
0658     /* We need to make sure that of_phy_connect() will not work by
0659      * removing the 'phandle' and 'linux,phandle' properties and
0660      * unregister the existing PHY device that was already registered.
0661      */
0662     for_each_available_child_of_node(dn, child) {
0663         if (of_property_read_u32(child, "reg", &reg) ||
0664             reg >= PHY_MAX_ADDR)
0665             continue;
0666 
0667         if (!(priv->indir_phy_mask & BIT(reg)))
0668             continue;
0669 
0670         prop = of_find_property(child, "phandle", NULL);
0671         if (prop)
0672             of_remove_property(child, prop);
0673 
0674         prop = of_find_property(child, "linux,phandle", NULL);
0675         if (prop)
0676             of_remove_property(child, prop);
0677 
0678         phydev = of_phy_find_device(child);
0679         if (phydev)
0680             phy_device_remove(phydev);
0681     }
0682 
0683     err = mdiobus_register(priv->slave_mii_bus);
0684     if (err && dn) {
0685         mdiobus_free(priv->slave_mii_bus);
0686         of_node_put(dn);
0687     }
0688 
0689     return err;
0690 }
0691 
0692 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
0693 {
0694     mdiobus_unregister(priv->slave_mii_bus);
0695     mdiobus_free(priv->slave_mii_bus);
0696     of_node_put(priv->master_mii_dn);
0697 }
0698 
0699 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
0700 {
0701     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0702 
0703     /* The BCM7xxx PHY driver expects to find the integrated PHY revision
0704      * in bits 15:8 and the patch level in bits 7:0 which is exactly what
0705      * the REG_PHY_REVISION register layout is.
0706      */
0707     if (priv->int_phy_mask & BIT(port))
0708         return priv->hw_params.gphy_rev;
0709     else
0710         return PHY_BRCM_AUTO_PWRDWN_ENABLE |
0711                PHY_BRCM_DIS_TXCRXC_NOENRGY |
0712                PHY_BRCM_IDDQ_SUSPEND;
0713 }
0714 
0715 static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
0716                 struct phylink_config *config)
0717 {
0718     unsigned long *interfaces = config->supported_interfaces;
0719     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0720 
0721     if (priv->int_phy_mask & BIT(port)) {
0722         __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
0723     } else if (priv->moca_port == port) {
0724         __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces);
0725     } else {
0726         __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
0727         __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
0728         __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
0729         phy_interface_set_rgmii(interfaces);
0730     }
0731 
0732     config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
0733         MAC_10 | MAC_100 | MAC_1000;
0734 }
0735 
0736 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
0737                   unsigned int mode,
0738                   const struct phylink_link_state *state)
0739 {
0740     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0741     u32 id_mode_dis = 0, port_mode;
0742     u32 reg_rgmii_ctrl;
0743     u32 reg;
0744 
0745     if (port == core_readl(priv, CORE_IMP0_PRT_ID))
0746         return;
0747 
0748     switch (state->interface) {
0749     case PHY_INTERFACE_MODE_RGMII:
0750         id_mode_dis = 1;
0751         fallthrough;
0752     case PHY_INTERFACE_MODE_RGMII_TXID:
0753         port_mode = EXT_GPHY;
0754         break;
0755     case PHY_INTERFACE_MODE_MII:
0756         port_mode = EXT_EPHY;
0757         break;
0758     case PHY_INTERFACE_MODE_REVMII:
0759         port_mode = EXT_REVMII;
0760         break;
0761     default:
0762         /* Nothing required for all other PHYs: internal and MoCA */
0763         return;
0764     }
0765 
0766     reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
0767 
0768     /* Clear id_mode_dis bit, and the existing port mode, let
0769      * RGMII_MODE_EN bet set by mac_link_{up,down}
0770      */
0771     reg = reg_readl(priv, reg_rgmii_ctrl);
0772     reg &= ~ID_MODE_DIS;
0773     reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
0774 
0775     reg |= port_mode;
0776     if (id_mode_dis)
0777         reg |= ID_MODE_DIS;
0778 
0779     reg_writel(priv, reg, reg_rgmii_ctrl);
0780 }
0781 
0782 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
0783                     phy_interface_t interface, bool link)
0784 {
0785     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0786     u32 reg_rgmii_ctrl;
0787     u32 reg;
0788 
0789     if (!phy_interface_mode_is_rgmii(interface) &&
0790         interface != PHY_INTERFACE_MODE_MII &&
0791         interface != PHY_INTERFACE_MODE_REVMII)
0792         return;
0793 
0794     reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
0795 
0796     /* If the link is down, just disable the interface to conserve power */
0797     reg = reg_readl(priv, reg_rgmii_ctrl);
0798     if (link)
0799         reg |= RGMII_MODE_EN;
0800     else
0801         reg &= ~RGMII_MODE_EN;
0802     reg_writel(priv, reg, reg_rgmii_ctrl);
0803 }
0804 
0805 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
0806                      unsigned int mode,
0807                      phy_interface_t interface)
0808 {
0809     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0810     u32 reg, offset;
0811 
0812     if (priv->wol_ports_mask & BIT(port))
0813         return;
0814 
0815     if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
0816         if (priv->type == BCM4908_DEVICE_ID ||
0817             priv->type == BCM7445_DEVICE_ID)
0818             offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
0819         else
0820             offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
0821 
0822         reg = core_readl(priv, offset);
0823         reg &= ~LINK_STS;
0824         core_writel(priv, reg, offset);
0825     }
0826 
0827     bcm_sf2_sw_mac_link_set(ds, port, interface, false);
0828 }
0829 
0830 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
0831                    unsigned int mode,
0832                    phy_interface_t interface,
0833                    struct phy_device *phydev,
0834                    int speed, int duplex,
0835                    bool tx_pause, bool rx_pause)
0836 {
0837     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0838     struct ethtool_eee *p = &priv->dev->ports[port].eee;
0839 
0840     bcm_sf2_sw_mac_link_set(ds, port, interface, true);
0841 
0842     if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
0843         u32 reg_rgmii_ctrl = 0;
0844         u32 reg, offset;
0845 
0846         if (priv->type == BCM4908_DEVICE_ID ||
0847             priv->type == BCM7445_DEVICE_ID)
0848             offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
0849         else
0850             offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
0851 
0852         if (interface == PHY_INTERFACE_MODE_RGMII ||
0853             interface == PHY_INTERFACE_MODE_RGMII_TXID ||
0854             interface == PHY_INTERFACE_MODE_MII ||
0855             interface == PHY_INTERFACE_MODE_REVMII) {
0856             reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
0857             reg = reg_readl(priv, reg_rgmii_ctrl);
0858             reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
0859 
0860             if (tx_pause)
0861                 reg |= TX_PAUSE_EN;
0862             if (rx_pause)
0863                 reg |= RX_PAUSE_EN;
0864 
0865             reg_writel(priv, reg, reg_rgmii_ctrl);
0866         }
0867 
0868         reg = SW_OVERRIDE | LINK_STS;
0869         switch (speed) {
0870         case SPEED_1000:
0871             reg |= SPDSTS_1000 << SPEED_SHIFT;
0872             break;
0873         case SPEED_100:
0874             reg |= SPDSTS_100 << SPEED_SHIFT;
0875             break;
0876         }
0877 
0878         if (duplex == DUPLEX_FULL)
0879             reg |= DUPLX_MODE;
0880 
0881         if (tx_pause)
0882             reg |= TXFLOW_CNTL;
0883         if (rx_pause)
0884             reg |= RXFLOW_CNTL;
0885 
0886         core_writel(priv, reg, offset);
0887     }
0888 
0889     if (mode == MLO_AN_PHY && phydev)
0890         p->eee_enabled = b53_eee_init(ds, port, phydev);
0891 }
0892 
0893 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
0894                    struct phylink_link_state *status)
0895 {
0896     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0897 
0898     status->link = false;
0899 
0900     /* MoCA port is special as we do not get link status from CORE_LNKSTS,
0901      * which means that we need to force the link at the port override
0902      * level to get the data to flow. We do use what the interrupt handler
0903      * did determine before.
0904      *
0905      * For the other ports, we just force the link status, since this is
0906      * a fixed PHY device.
0907      */
0908     if (port == priv->moca_port) {
0909         status->link = priv->port_sts[port].link;
0910         /* For MoCA interfaces, also force a link down notification
0911          * since some version of the user-space daemon (mocad) use
0912          * cmd->autoneg to force the link, which messes up the PHY
0913          * state machine and make it go in PHY_FORCING state instead.
0914          */
0915         if (!status->link)
0916             netif_carrier_off(dsa_to_port(ds, port)->slave);
0917         status->duplex = DUPLEX_FULL;
0918     } else {
0919         status->link = true;
0920     }
0921 }
0922 
0923 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
0924 {
0925     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0926     u32 reg;
0927 
0928     /* Enable ACB globally */
0929     reg = acb_readl(priv, ACB_CONTROL);
0930     reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
0931     acb_writel(priv, reg, ACB_CONTROL);
0932     reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
0933     reg |= ACB_EN | ACB_ALGORITHM;
0934     acb_writel(priv, reg, ACB_CONTROL);
0935 }
0936 
0937 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
0938 {
0939     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0940     unsigned int port;
0941 
0942     bcm_sf2_intr_disable(priv);
0943 
0944     /* Disable all ports physically present including the IMP
0945      * port, the other ones have already been disabled during
0946      * bcm_sf2_sw_setup
0947      */
0948     for (port = 0; port < ds->num_ports; port++) {
0949         if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
0950             bcm_sf2_port_disable(ds, port);
0951     }
0952 
0953     if (!priv->wol_ports_mask)
0954         clk_disable_unprepare(priv->clk);
0955 
0956     return 0;
0957 }
0958 
0959 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
0960 {
0961     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0962     int ret;
0963 
0964     if (!priv->wol_ports_mask)
0965         clk_prepare_enable(priv->clk);
0966 
0967     ret = bcm_sf2_sw_rst(priv);
0968     if (ret) {
0969         pr_err("%s: failed to software reset switch\n", __func__);
0970         return ret;
0971     }
0972 
0973     bcm_sf2_crossbar_setup(priv);
0974 
0975     ret = bcm_sf2_cfp_resume(ds);
0976     if (ret)
0977         return ret;
0978 
0979     if (priv->hw_params.num_gphy == 1)
0980         bcm_sf2_gphy_enable_set(ds, true);
0981 
0982     ds->ops->setup(ds);
0983 
0984     return 0;
0985 }
0986 
0987 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
0988                    struct ethtool_wolinfo *wol)
0989 {
0990     struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
0991     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0992     struct ethtool_wolinfo pwol = { };
0993 
0994     /* Get the parent device WoL settings */
0995     if (p->ethtool_ops->get_wol)
0996         p->ethtool_ops->get_wol(p, &pwol);
0997 
0998     /* Advertise the parent device supported settings */
0999     wol->supported = pwol.supported;
1000     memset(&wol->sopass, 0, sizeof(wol->sopass));
1001 
1002     if (pwol.wolopts & WAKE_MAGICSECURE)
1003         memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1004 
1005     if (priv->wol_ports_mask & (1 << port))
1006         wol->wolopts = pwol.wolopts;
1007     else
1008         wol->wolopts = 0;
1009 }
1010 
1011 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1012                   struct ethtool_wolinfo *wol)
1013 {
1014     struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
1015     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1016     s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1017     struct ethtool_wolinfo pwol =  { };
1018 
1019     if (p->ethtool_ops->get_wol)
1020         p->ethtool_ops->get_wol(p, &pwol);
1021     if (wol->wolopts & ~pwol.supported)
1022         return -EINVAL;
1023 
1024     if (wol->wolopts)
1025         priv->wol_ports_mask |= (1 << port);
1026     else
1027         priv->wol_ports_mask &= ~(1 << port);
1028 
1029     /* If we have at least one port enabled, make sure the CPU port
1030      * is also enabled. If the CPU port is the last one enabled, we disable
1031      * it since this configuration does not make sense.
1032      */
1033     if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1034         priv->wol_ports_mask |= (1 << cpu_port);
1035     else
1036         priv->wol_ports_mask &= ~(1 << cpu_port);
1037 
1038     return p->ethtool_ops->set_wol(p, wol);
1039 }
1040 
1041 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1042 {
1043     struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1044     unsigned int port;
1045 
1046     /* Enable all valid ports and disable those unused */
1047     for (port = 0; port < priv->hw_params.num_ports; port++) {
1048         /* IMP port receives special treatment */
1049         if (dsa_is_user_port(ds, port))
1050             bcm_sf2_port_setup(ds, port, NULL);
1051         else if (dsa_is_cpu_port(ds, port))
1052             bcm_sf2_imp_setup(ds, port);
1053         else
1054             bcm_sf2_port_disable(ds, port);
1055     }
1056 
1057     b53_configure_vlan(ds);
1058     bcm_sf2_enable_acb(ds);
1059 
1060     return b53_setup_devlink_resources(ds);
1061 }
1062 
1063 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1064 {
1065     dsa_devlink_resources_unregister(ds);
1066 }
1067 
1068 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
1069  * register basis so we need to translate that into an address that the
1070  * bus-glue understands.
1071  */
1072 #define SF2_PAGE_REG_MKADDR(page, reg)  ((page) << 10 | (reg) << 2)
1073 
1074 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1075                   u8 *val)
1076 {
1077     struct bcm_sf2_priv *priv = dev->priv;
1078 
1079     *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1080 
1081     return 0;
1082 }
1083 
1084 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1085                    u16 *val)
1086 {
1087     struct bcm_sf2_priv *priv = dev->priv;
1088 
1089     *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1090 
1091     return 0;
1092 }
1093 
1094 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1095                    u32 *val)
1096 {
1097     struct bcm_sf2_priv *priv = dev->priv;
1098 
1099     *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1100 
1101     return 0;
1102 }
1103 
1104 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1105                    u64 *val)
1106 {
1107     struct bcm_sf2_priv *priv = dev->priv;
1108 
1109     *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1110 
1111     return 0;
1112 }
1113 
1114 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1115                    u8 value)
1116 {
1117     struct bcm_sf2_priv *priv = dev->priv;
1118 
1119     core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1120 
1121     return 0;
1122 }
1123 
1124 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1125                 u16 value)
1126 {
1127     struct bcm_sf2_priv *priv = dev->priv;
1128 
1129     core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1130 
1131     return 0;
1132 }
1133 
1134 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1135                 u32 value)
1136 {
1137     struct bcm_sf2_priv *priv = dev->priv;
1138 
1139     core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1140 
1141     return 0;
1142 }
1143 
1144 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1145                 u64 value)
1146 {
1147     struct bcm_sf2_priv *priv = dev->priv;
1148 
1149     core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1150 
1151     return 0;
1152 }
1153 
1154 static const struct b53_io_ops bcm_sf2_io_ops = {
1155     .read8  = bcm_sf2_core_read8,
1156     .read16 = bcm_sf2_core_read16,
1157     .read32 = bcm_sf2_core_read32,
1158     .read48 = bcm_sf2_core_read64,
1159     .read64 = bcm_sf2_core_read64,
1160     .write8 = bcm_sf2_core_write8,
1161     .write16 = bcm_sf2_core_write16,
1162     .write32 = bcm_sf2_core_write32,
1163     .write48 = bcm_sf2_core_write64,
1164     .write64 = bcm_sf2_core_write64,
1165 };
1166 
1167 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1168                    u32 stringset, uint8_t *data)
1169 {
1170     int cnt = b53_get_sset_count(ds, port, stringset);
1171 
1172     b53_get_strings(ds, port, stringset, data);
1173     bcm_sf2_cfp_get_strings(ds, port, stringset,
1174                 data + cnt * ETH_GSTRING_LEN);
1175 }
1176 
1177 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1178                      uint64_t *data)
1179 {
1180     int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1181 
1182     b53_get_ethtool_stats(ds, port, data);
1183     bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1184 }
1185 
1186 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1187                      int sset)
1188 {
1189     int cnt = b53_get_sset_count(ds, port, sset);
1190 
1191     if (cnt < 0)
1192         return cnt;
1193 
1194     cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1195 
1196     return cnt;
1197 }
1198 
1199 static const struct dsa_switch_ops bcm_sf2_ops = {
1200     .get_tag_protocol   = b53_get_tag_protocol,
1201     .setup          = bcm_sf2_sw_setup,
1202     .teardown       = bcm_sf2_sw_teardown,
1203     .get_strings        = bcm_sf2_sw_get_strings,
1204     .get_ethtool_stats  = bcm_sf2_sw_get_ethtool_stats,
1205     .get_sset_count     = bcm_sf2_sw_get_sset_count,
1206     .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1207     .get_phy_flags      = bcm_sf2_sw_get_phy_flags,
1208     .phylink_get_caps   = bcm_sf2_sw_get_caps,
1209     .phylink_mac_config = bcm_sf2_sw_mac_config,
1210     .phylink_mac_link_down  = bcm_sf2_sw_mac_link_down,
1211     .phylink_mac_link_up    = bcm_sf2_sw_mac_link_up,
1212     .phylink_fixed_state    = bcm_sf2_sw_fixed_state,
1213     .suspend        = bcm_sf2_sw_suspend,
1214     .resume         = bcm_sf2_sw_resume,
1215     .get_wol        = bcm_sf2_sw_get_wol,
1216     .set_wol        = bcm_sf2_sw_set_wol,
1217     .port_enable        = bcm_sf2_port_setup,
1218     .port_disable       = bcm_sf2_port_disable,
1219     .get_mac_eee        = b53_get_mac_eee,
1220     .set_mac_eee        = b53_set_mac_eee,
1221     .port_bridge_join   = b53_br_join,
1222     .port_bridge_leave  = b53_br_leave,
1223     .port_pre_bridge_flags  = b53_br_flags_pre,
1224     .port_bridge_flags  = b53_br_flags,
1225     .port_stp_state_set = b53_br_set_stp_state,
1226     .port_fast_age      = b53_br_fast_age,
1227     .port_vlan_filtering    = b53_vlan_filtering,
1228     .port_vlan_add      = b53_vlan_add,
1229     .port_vlan_del      = b53_vlan_del,
1230     .port_fdb_dump      = b53_fdb_dump,
1231     .port_fdb_add       = b53_fdb_add,
1232     .port_fdb_del       = b53_fdb_del,
1233     .get_rxnfc      = bcm_sf2_get_rxnfc,
1234     .set_rxnfc      = bcm_sf2_set_rxnfc,
1235     .port_mirror_add    = b53_mirror_add,
1236     .port_mirror_del    = b53_mirror_del,
1237     .port_mdb_add       = b53_mdb_add,
1238     .port_mdb_del       = b53_mdb_del,
1239 };
1240 
1241 struct bcm_sf2_of_data {
1242     u32 type;
1243     const u16 *reg_offsets;
1244     unsigned int core_reg_align;
1245     unsigned int num_cfp_rules;
1246     unsigned int num_crossbar_int_ports;
1247 };
1248 
1249 static const u16 bcm_sf2_4908_reg_offsets[] = {
1250     [REG_SWITCH_CNTRL]  = 0x00,
1251     [REG_SWITCH_STATUS] = 0x04,
1252     [REG_DIR_DATA_WRITE]    = 0x08,
1253     [REG_DIR_DATA_READ] = 0x0c,
1254     [REG_SWITCH_REVISION]   = 0x10,
1255     [REG_PHY_REVISION]  = 0x14,
1256     [REG_SPHY_CNTRL]    = 0x24,
1257     [REG_CROSSBAR]      = 0xc8,
1258     [REG_RGMII_11_CNTRL]    = 0x014c,
1259     [REG_LED_0_CNTRL]       = 0x40,
1260     [REG_LED_1_CNTRL]       = 0x4c,
1261     [REG_LED_2_CNTRL]       = 0x58,
1262     [REG_LED_3_CNTRL]       = 0x64,
1263     [REG_LED_4_CNTRL]       = 0x88,
1264     [REG_LED_5_CNTRL]       = 0xa0,
1265     [REG_LED_AGGREGATE_CTRL]    = 0xb8,
1266 
1267 };
1268 
1269 static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1270     .type       = BCM4908_DEVICE_ID,
1271     .core_reg_align = 0,
1272     .reg_offsets    = bcm_sf2_4908_reg_offsets,
1273     .num_cfp_rules  = 256,
1274     .num_crossbar_int_ports = 2,
1275 };
1276 
1277 /* Register offsets for the SWITCH_REG_* block */
1278 static const u16 bcm_sf2_7445_reg_offsets[] = {
1279     [REG_SWITCH_CNTRL]  = 0x00,
1280     [REG_SWITCH_STATUS] = 0x04,
1281     [REG_DIR_DATA_WRITE]    = 0x08,
1282     [REG_DIR_DATA_READ] = 0x0C,
1283     [REG_SWITCH_REVISION]   = 0x18,
1284     [REG_PHY_REVISION]  = 0x1C,
1285     [REG_SPHY_CNTRL]    = 0x2C,
1286     [REG_RGMII_0_CNTRL] = 0x34,
1287     [REG_RGMII_1_CNTRL] = 0x40,
1288     [REG_RGMII_2_CNTRL] = 0x4c,
1289     [REG_LED_0_CNTRL]   = 0x90,
1290     [REG_LED_1_CNTRL]   = 0x94,
1291     [REG_LED_2_CNTRL]   = 0x98,
1292 };
1293 
1294 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1295     .type       = BCM7445_DEVICE_ID,
1296     .core_reg_align = 0,
1297     .reg_offsets    = bcm_sf2_7445_reg_offsets,
1298     .num_cfp_rules  = 256,
1299 };
1300 
1301 static const u16 bcm_sf2_7278_reg_offsets[] = {
1302     [REG_SWITCH_CNTRL]  = 0x00,
1303     [REG_SWITCH_STATUS] = 0x04,
1304     [REG_DIR_DATA_WRITE]    = 0x08,
1305     [REG_DIR_DATA_READ] = 0x0c,
1306     [REG_SWITCH_REVISION]   = 0x10,
1307     [REG_PHY_REVISION]  = 0x14,
1308     [REG_SPHY_CNTRL]    = 0x24,
1309     [REG_RGMII_0_CNTRL] = 0xe0,
1310     [REG_RGMII_1_CNTRL] = 0xec,
1311     [REG_RGMII_2_CNTRL] = 0xf8,
1312     [REG_LED_0_CNTRL]   = 0x40,
1313     [REG_LED_1_CNTRL]   = 0x4c,
1314     [REG_LED_2_CNTRL]   = 0x58,
1315 };
1316 
1317 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1318     .type       = BCM7278_DEVICE_ID,
1319     .core_reg_align = 1,
1320     .reg_offsets    = bcm_sf2_7278_reg_offsets,
1321     .num_cfp_rules  = 128,
1322 };
1323 
1324 static const struct of_device_id bcm_sf2_of_match[] = {
1325     { .compatible = "brcm,bcm4908-switch",
1326       .data = &bcm_sf2_4908_data
1327     },
1328     { .compatible = "brcm,bcm7445-switch-v4.0",
1329       .data = &bcm_sf2_7445_data
1330     },
1331     { .compatible = "brcm,bcm7278-switch-v4.0",
1332       .data = &bcm_sf2_7278_data
1333     },
1334     { .compatible = "brcm,bcm7278-switch-v4.8",
1335       .data = &bcm_sf2_7278_data
1336     },
1337     { /* sentinel */ },
1338 };
1339 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1340 
1341 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1342 {
1343     const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1344     struct device_node *dn = pdev->dev.of_node;
1345     const struct of_device_id *of_id = NULL;
1346     const struct bcm_sf2_of_data *data;
1347     struct b53_platform_data *pdata;
1348     struct dsa_switch_ops *ops;
1349     struct device_node *ports;
1350     struct bcm_sf2_priv *priv;
1351     struct b53_device *dev;
1352     struct dsa_switch *ds;
1353     void __iomem **base;
1354     unsigned int i;
1355     u32 reg, rev;
1356     int ret;
1357 
1358     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1359     if (!priv)
1360         return -ENOMEM;
1361 
1362     ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1363     if (!ops)
1364         return -ENOMEM;
1365 
1366     dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1367     if (!dev)
1368         return -ENOMEM;
1369 
1370     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1371     if (!pdata)
1372         return -ENOMEM;
1373 
1374     of_id = of_match_node(bcm_sf2_of_match, dn);
1375     if (!of_id || !of_id->data)
1376         return -EINVAL;
1377 
1378     data = of_id->data;
1379 
1380     /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1381     priv->type = data->type;
1382     priv->reg_offsets = data->reg_offsets;
1383     priv->core_reg_align = data->core_reg_align;
1384     priv->num_cfp_rules = data->num_cfp_rules;
1385     priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1386 
1387     priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1388                                 "switch");
1389     if (IS_ERR(priv->rcdev))
1390         return PTR_ERR(priv->rcdev);
1391 
1392     /* Auto-detection using standard registers will not work, so
1393      * provide an indication of what kind of device we are for
1394      * b53_common to work with
1395      */
1396     pdata->chip_id = priv->type;
1397     dev->pdata = pdata;
1398 
1399     priv->dev = dev;
1400     ds = dev->ds;
1401     ds->ops = &bcm_sf2_ops;
1402 
1403     /* Advertise the 8 egress queues */
1404     ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1405 
1406     dev_set_drvdata(&pdev->dev, priv);
1407 
1408     spin_lock_init(&priv->indir_lock);
1409     mutex_init(&priv->cfp.lock);
1410     INIT_LIST_HEAD(&priv->cfp.rules_list);
1411 
1412     /* CFP rule #0 cannot be used for specific classifications, flag it as
1413      * permanently used
1414      */
1415     set_bit(0, priv->cfp.used);
1416     set_bit(0, priv->cfp.unique);
1417 
1418     /* Balance of_node_put() done by of_find_node_by_name() */
1419     of_node_get(dn);
1420     ports = of_find_node_by_name(dn, "ports");
1421     if (ports) {
1422         bcm_sf2_identify_ports(priv, ports);
1423         of_node_put(ports);
1424     }
1425 
1426     priv->irq0 = irq_of_parse_and_map(dn, 0);
1427     priv->irq1 = irq_of_parse_and_map(dn, 1);
1428 
1429     base = &priv->core;
1430     for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1431         *base = devm_platform_ioremap_resource(pdev, i);
1432         if (IS_ERR(*base)) {
1433             pr_err("unable to find register: %s\n", reg_names[i]);
1434             return PTR_ERR(*base);
1435         }
1436         base++;
1437     }
1438 
1439     priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1440     if (IS_ERR(priv->clk))
1441         return PTR_ERR(priv->clk);
1442 
1443     clk_prepare_enable(priv->clk);
1444 
1445     priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1446     if (IS_ERR(priv->clk_mdiv)) {
1447         ret = PTR_ERR(priv->clk_mdiv);
1448         goto out_clk;
1449     }
1450 
1451     clk_prepare_enable(priv->clk_mdiv);
1452 
1453     ret = bcm_sf2_sw_rst(priv);
1454     if (ret) {
1455         pr_err("unable to software reset switch: %d\n", ret);
1456         goto out_clk_mdiv;
1457     }
1458 
1459     bcm_sf2_crossbar_setup(priv);
1460 
1461     bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1462 
1463     ret = bcm_sf2_mdio_register(ds);
1464     if (ret) {
1465         pr_err("failed to register MDIO bus\n");
1466         goto out_clk_mdiv;
1467     }
1468 
1469     bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1470 
1471     ret = bcm_sf2_cfp_rst(priv);
1472     if (ret) {
1473         pr_err("failed to reset CFP\n");
1474         goto out_mdio;
1475     }
1476 
1477     /* Disable all interrupts and request them */
1478     bcm_sf2_intr_disable(priv);
1479 
1480     ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1481                    "switch_0", ds);
1482     if (ret < 0) {
1483         pr_err("failed to request switch_0 IRQ\n");
1484         goto out_mdio;
1485     }
1486 
1487     ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1488                    "switch_1", ds);
1489     if (ret < 0) {
1490         pr_err("failed to request switch_1 IRQ\n");
1491         goto out_mdio;
1492     }
1493 
1494     /* Reset the MIB counters */
1495     reg = core_readl(priv, CORE_GMNCFGCFG);
1496     reg |= RST_MIB_CNT;
1497     core_writel(priv, reg, CORE_GMNCFGCFG);
1498     reg &= ~RST_MIB_CNT;
1499     core_writel(priv, reg, CORE_GMNCFGCFG);
1500 
1501     /* Get the maximum number of ports for this switch */
1502     priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1503     if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1504         priv->hw_params.num_ports = DSA_MAX_PORTS;
1505 
1506     /* Assume a single GPHY setup if we can't read that property */
1507     if (of_property_read_u32(dn, "brcm,num-gphy",
1508                  &priv->hw_params.num_gphy))
1509         priv->hw_params.num_gphy = 1;
1510 
1511     rev = reg_readl(priv, REG_SWITCH_REVISION);
1512     priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1513                     SWITCH_TOP_REV_MASK;
1514     priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1515 
1516     rev = reg_readl(priv, REG_PHY_REVISION);
1517     priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1518 
1519     ret = b53_switch_register(dev);
1520     if (ret)
1521         goto out_mdio;
1522 
1523     dev_info(&pdev->dev,
1524          "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1525          priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1526          priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1527          priv->irq0, priv->irq1);
1528 
1529     return 0;
1530 
1531 out_mdio:
1532     bcm_sf2_mdio_unregister(priv);
1533 out_clk_mdiv:
1534     clk_disable_unprepare(priv->clk_mdiv);
1535 out_clk:
1536     clk_disable_unprepare(priv->clk);
1537     return ret;
1538 }
1539 
1540 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1541 {
1542     struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1543 
1544     if (!priv)
1545         return 0;
1546 
1547     priv->wol_ports_mask = 0;
1548     /* Disable interrupts */
1549     bcm_sf2_intr_disable(priv);
1550     dsa_unregister_switch(priv->dev->ds);
1551     bcm_sf2_cfp_exit(priv->dev->ds);
1552     bcm_sf2_mdio_unregister(priv);
1553     clk_disable_unprepare(priv->clk_mdiv);
1554     clk_disable_unprepare(priv->clk);
1555     if (priv->type == BCM7278_DEVICE_ID)
1556         reset_control_assert(priv->rcdev);
1557 
1558     platform_set_drvdata(pdev, NULL);
1559 
1560     return 0;
1561 }
1562 
1563 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1564 {
1565     struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1566 
1567     if (!priv)
1568         return;
1569 
1570     /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1571      * successful MDIO bus scan to occur. If we did turn off the GPHY
1572      * before (e.g: port_disable), this will also power it back on.
1573      *
1574      * Do not rely on kexec_in_progress, just power the PHY on.
1575      */
1576     if (priv->hw_params.num_gphy == 1)
1577         bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1578 
1579     dsa_switch_shutdown(priv->dev->ds);
1580 
1581     platform_set_drvdata(pdev, NULL);
1582 }
1583 
1584 #ifdef CONFIG_PM_SLEEP
1585 static int bcm_sf2_suspend(struct device *dev)
1586 {
1587     struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1588 
1589     return dsa_switch_suspend(priv->dev->ds);
1590 }
1591 
1592 static int bcm_sf2_resume(struct device *dev)
1593 {
1594     struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1595 
1596     return dsa_switch_resume(priv->dev->ds);
1597 }
1598 #endif /* CONFIG_PM_SLEEP */
1599 
1600 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1601              bcm_sf2_suspend, bcm_sf2_resume);
1602 
1603 
1604 static struct platform_driver bcm_sf2_driver = {
1605     .probe  = bcm_sf2_sw_probe,
1606     .remove = bcm_sf2_sw_remove,
1607     .shutdown = bcm_sf2_sw_shutdown,
1608     .driver = {
1609         .name = "brcm-sf2",
1610         .of_match_table = bcm_sf2_of_match,
1611         .pm = &bcm_sf2_pm_ops,
1612     },
1613 };
1614 module_platform_driver(bcm_sf2_driver);
1615 
1616 MODULE_AUTHOR("Broadcom Corporation");
1617 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1618 MODULE_LICENSE("GPL");
1619 MODULE_ALIAS("platform:brcm-sf2");
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