Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * B53 register access through Switch Register Access Bridge Registers
0003  *
0004  * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
0005  *
0006  * Permission to use, copy, modify, and/or distribute this software for any
0007  * purpose with or without fee is hereby granted, provided that the above
0008  * copyright notice and this permission notice appear in all copies.
0009  *
0010  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0011  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0012  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0013  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0014  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0015  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0016  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/delay.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/platform_data/b53.h>
0025 #include <linux/of.h>
0026 
0027 #include "b53_priv.h"
0028 #include "b53_serdes.h"
0029 
0030 /* command and status register of the SRAB */
0031 #define B53_SRAB_CMDSTAT        0x2c
0032 #define  B53_SRAB_CMDSTAT_RST       BIT(2)
0033 #define  B53_SRAB_CMDSTAT_WRITE     BIT(1)
0034 #define  B53_SRAB_CMDSTAT_GORDYN    BIT(0)
0035 #define  B53_SRAB_CMDSTAT_PAGE      24
0036 #define  B53_SRAB_CMDSTAT_REG       16
0037 
0038 /* high order word of write data to switch registe */
0039 #define B53_SRAB_WD_H           0x30
0040 
0041 /* low order word of write data to switch registe */
0042 #define B53_SRAB_WD_L           0x34
0043 
0044 /* high order word of read data from switch register */
0045 #define B53_SRAB_RD_H           0x38
0046 
0047 /* low order word of read data from switch register */
0048 #define B53_SRAB_RD_L           0x3c
0049 
0050 /* command and status register of the SRAB */
0051 #define B53_SRAB_CTRLS          0x40
0052 #define  B53_SRAB_CTRLS_HOST_INTR   BIT(1)
0053 #define  B53_SRAB_CTRLS_RCAREQ      BIT(3)
0054 #define  B53_SRAB_CTRLS_RCAGNT      BIT(4)
0055 #define  B53_SRAB_CTRLS_SW_INIT_DONE    BIT(6)
0056 
0057 /* the register captures interrupt pulses from the switch */
0058 #define B53_SRAB_INTR           0x44
0059 #define  B53_SRAB_INTR_P(x)     BIT(x)
0060 #define  B53_SRAB_SWITCH_PHY        BIT(8)
0061 #define  B53_SRAB_1588_SYNC     BIT(9)
0062 #define  B53_SRAB_IMP1_SLEEP_TIMER  BIT(10)
0063 #define  B53_SRAB_P7_SLEEP_TIMER    BIT(11)
0064 #define  B53_SRAB_IMP0_SLEEP_TIMER  BIT(12)
0065 
0066 /* Port mux configuration registers */
0067 #define B53_MUX_CONFIG_P5       0x00
0068 #define  MUX_CONFIG_SGMII       0
0069 #define  MUX_CONFIG_MII_LITE        1
0070 #define  MUX_CONFIG_RGMII       2
0071 #define  MUX_CONFIG_GMII        3
0072 #define  MUX_CONFIG_GPHY        4
0073 #define  MUX_CONFIG_INTERNAL        5
0074 #define  MUX_CONFIG_MASK        0x7
0075 #define B53_MUX_CONFIG_P4       0x04
0076 
0077 struct b53_srab_port_priv {
0078     int irq;
0079     bool irq_enabled;
0080     struct b53_device *dev;
0081     unsigned int num;
0082     phy_interface_t mode;
0083 };
0084 
0085 struct b53_srab_priv {
0086     void __iomem *regs;
0087     void __iomem *mux_config;
0088     struct b53_srab_port_priv port_intrs[B53_N_PORTS];
0089 };
0090 
0091 static int b53_srab_request_grant(struct b53_device *dev)
0092 {
0093     struct b53_srab_priv *priv = dev->priv;
0094     u8 __iomem *regs = priv->regs;
0095     u32 ctrls;
0096     int i;
0097 
0098     ctrls = readl(regs + B53_SRAB_CTRLS);
0099     ctrls |= B53_SRAB_CTRLS_RCAREQ;
0100     writel(ctrls, regs + B53_SRAB_CTRLS);
0101 
0102     for (i = 0; i < 20; i++) {
0103         ctrls = readl(regs + B53_SRAB_CTRLS);
0104         if (ctrls & B53_SRAB_CTRLS_RCAGNT)
0105             break;
0106         usleep_range(10, 100);
0107     }
0108     if (WARN_ON(i == 5))
0109         return -EIO;
0110 
0111     return 0;
0112 }
0113 
0114 static void b53_srab_release_grant(struct b53_device *dev)
0115 {
0116     struct b53_srab_priv *priv = dev->priv;
0117     u8 __iomem *regs = priv->regs;
0118     u32 ctrls;
0119 
0120     ctrls = readl(regs + B53_SRAB_CTRLS);
0121     ctrls &= ~B53_SRAB_CTRLS_RCAREQ;
0122     writel(ctrls, regs + B53_SRAB_CTRLS);
0123 }
0124 
0125 static int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op)
0126 {
0127     struct b53_srab_priv *priv = dev->priv;
0128     u8 __iomem *regs = priv->regs;
0129     int i;
0130     u32 cmdstat;
0131 
0132     /* set register address */
0133     cmdstat = (page << B53_SRAB_CMDSTAT_PAGE) |
0134           (reg << B53_SRAB_CMDSTAT_REG) |
0135           B53_SRAB_CMDSTAT_GORDYN |
0136           op;
0137     writel(cmdstat, regs + B53_SRAB_CMDSTAT);
0138 
0139     /* check if operation completed */
0140     for (i = 0; i < 5; ++i) {
0141         cmdstat = readl(regs + B53_SRAB_CMDSTAT);
0142         if (!(cmdstat & B53_SRAB_CMDSTAT_GORDYN))
0143             break;
0144         usleep_range(10, 100);
0145     }
0146 
0147     if (WARN_ON(i == 5))
0148         return -EIO;
0149 
0150     return 0;
0151 }
0152 
0153 static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)
0154 {
0155     struct b53_srab_priv *priv = dev->priv;
0156     u8 __iomem *regs = priv->regs;
0157     int ret = 0;
0158 
0159     ret = b53_srab_request_grant(dev);
0160     if (ret)
0161         goto err;
0162 
0163     ret = b53_srab_op(dev, page, reg, 0);
0164     if (ret)
0165         goto err;
0166 
0167     *val = readl(regs + B53_SRAB_RD_L) & 0xff;
0168 
0169 err:
0170     b53_srab_release_grant(dev);
0171 
0172     return ret;
0173 }
0174 
0175 static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)
0176 {
0177     struct b53_srab_priv *priv = dev->priv;
0178     u8 __iomem *regs = priv->regs;
0179     int ret = 0;
0180 
0181     ret = b53_srab_request_grant(dev);
0182     if (ret)
0183         goto err;
0184 
0185     ret = b53_srab_op(dev, page, reg, 0);
0186     if (ret)
0187         goto err;
0188 
0189     *val = readl(regs + B53_SRAB_RD_L) & 0xffff;
0190 
0191 err:
0192     b53_srab_release_grant(dev);
0193 
0194     return ret;
0195 }
0196 
0197 static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)
0198 {
0199     struct b53_srab_priv *priv = dev->priv;
0200     u8 __iomem *regs = priv->regs;
0201     int ret = 0;
0202 
0203     ret = b53_srab_request_grant(dev);
0204     if (ret)
0205         goto err;
0206 
0207     ret = b53_srab_op(dev, page, reg, 0);
0208     if (ret)
0209         goto err;
0210 
0211     *val = readl(regs + B53_SRAB_RD_L);
0212 
0213 err:
0214     b53_srab_release_grant(dev);
0215 
0216     return ret;
0217 }
0218 
0219 static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)
0220 {
0221     struct b53_srab_priv *priv = dev->priv;
0222     u8 __iomem *regs = priv->regs;
0223     int ret = 0;
0224 
0225     ret = b53_srab_request_grant(dev);
0226     if (ret)
0227         goto err;
0228 
0229     ret = b53_srab_op(dev, page, reg, 0);
0230     if (ret)
0231         goto err;
0232 
0233     *val = readl(regs + B53_SRAB_RD_L);
0234     *val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32;
0235 
0236 err:
0237     b53_srab_release_grant(dev);
0238 
0239     return ret;
0240 }
0241 
0242 static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)
0243 {
0244     struct b53_srab_priv *priv = dev->priv;
0245     u8 __iomem *regs = priv->regs;
0246     int ret = 0;
0247 
0248     ret = b53_srab_request_grant(dev);
0249     if (ret)
0250         goto err;
0251 
0252     ret = b53_srab_op(dev, page, reg, 0);
0253     if (ret)
0254         goto err;
0255 
0256     *val = readl(regs + B53_SRAB_RD_L);
0257     *val += (u64)readl(regs + B53_SRAB_RD_H) << 32;
0258 
0259 err:
0260     b53_srab_release_grant(dev);
0261 
0262     return ret;
0263 }
0264 
0265 static int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)
0266 {
0267     struct b53_srab_priv *priv = dev->priv;
0268     u8 __iomem *regs = priv->regs;
0269     int ret = 0;
0270 
0271     ret = b53_srab_request_grant(dev);
0272     if (ret)
0273         goto err;
0274 
0275     writel(value, regs + B53_SRAB_WD_L);
0276 
0277     ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
0278 
0279 err:
0280     b53_srab_release_grant(dev);
0281 
0282     return ret;
0283 }
0284 
0285 static int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg,
0286                 u16 value)
0287 {
0288     struct b53_srab_priv *priv = dev->priv;
0289     u8 __iomem *regs = priv->regs;
0290     int ret = 0;
0291 
0292     ret = b53_srab_request_grant(dev);
0293     if (ret)
0294         goto err;
0295 
0296     writel(value, regs + B53_SRAB_WD_L);
0297 
0298     ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
0299 
0300 err:
0301     b53_srab_release_grant(dev);
0302 
0303     return ret;
0304 }
0305 
0306 static int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg,
0307                 u32 value)
0308 {
0309     struct b53_srab_priv *priv = dev->priv;
0310     u8 __iomem *regs = priv->regs;
0311     int ret = 0;
0312 
0313     ret = b53_srab_request_grant(dev);
0314     if (ret)
0315         goto err;
0316 
0317     writel(value, regs + B53_SRAB_WD_L);
0318 
0319     ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
0320 
0321 err:
0322     b53_srab_release_grant(dev);
0323 
0324     return ret;
0325 }
0326 
0327 static int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg,
0328                 u64 value)
0329 {
0330     struct b53_srab_priv *priv = dev->priv;
0331     u8 __iomem *regs = priv->regs;
0332     int ret = 0;
0333 
0334     ret = b53_srab_request_grant(dev);
0335     if (ret)
0336         goto err;
0337 
0338     writel((u32)value, regs + B53_SRAB_WD_L);
0339     writel((u16)(value >> 32), regs + B53_SRAB_WD_H);
0340 
0341     ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
0342 
0343 err:
0344     b53_srab_release_grant(dev);
0345 
0346     return ret;
0347 }
0348 
0349 static int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg,
0350                 u64 value)
0351 {
0352     struct b53_srab_priv *priv = dev->priv;
0353     u8 __iomem *regs = priv->regs;
0354     int ret = 0;
0355 
0356     ret = b53_srab_request_grant(dev);
0357     if (ret)
0358         goto err;
0359 
0360     writel((u32)value, regs + B53_SRAB_WD_L);
0361     writel((u32)(value >> 32), regs + B53_SRAB_WD_H);
0362 
0363     ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
0364 
0365 err:
0366     b53_srab_release_grant(dev);
0367 
0368     return ret;
0369 }
0370 
0371 static irqreturn_t b53_srab_port_thread(int irq, void *dev_id)
0372 {
0373     struct b53_srab_port_priv *port = dev_id;
0374     struct b53_device *dev = port->dev;
0375 
0376     if (port->mode == PHY_INTERFACE_MODE_SGMII)
0377         b53_port_event(dev->ds, port->num);
0378 
0379     return IRQ_HANDLED;
0380 }
0381 
0382 static irqreturn_t b53_srab_port_isr(int irq, void *dev_id)
0383 {
0384     struct b53_srab_port_priv *port = dev_id;
0385     struct b53_device *dev = port->dev;
0386     struct b53_srab_priv *priv = dev->priv;
0387 
0388     /* Acknowledge the interrupt */
0389     writel(BIT(port->num), priv->regs + B53_SRAB_INTR);
0390 
0391     return IRQ_WAKE_THREAD;
0392 }
0393 
0394 #if IS_ENABLED(CONFIG_B53_SERDES)
0395 static u8 b53_srab_serdes_map_lane(struct b53_device *dev, int port)
0396 {
0397     struct b53_srab_priv *priv = dev->priv;
0398     struct b53_srab_port_priv *p = &priv->port_intrs[port];
0399 
0400     if (p->mode != PHY_INTERFACE_MODE_SGMII)
0401         return B53_INVALID_LANE;
0402 
0403     switch (port) {
0404     case 5:
0405         return 0;
0406     case 4:
0407         return 1;
0408     default:
0409         return B53_INVALID_LANE;
0410     }
0411 }
0412 #endif
0413 
0414 static int b53_srab_irq_enable(struct b53_device *dev, int port)
0415 {
0416     struct b53_srab_priv *priv = dev->priv;
0417     struct b53_srab_port_priv *p = &priv->port_intrs[port];
0418     int ret = 0;
0419 
0420     /* Interrupt is optional and was not specified, do not make
0421      * this fatal
0422      */
0423     if (p->irq == -ENXIO)
0424         return ret;
0425 
0426     ret = request_threaded_irq(p->irq, b53_srab_port_isr,
0427                    b53_srab_port_thread, 0,
0428                    dev_name(dev->dev), p);
0429     if (!ret)
0430         p->irq_enabled = true;
0431 
0432     return ret;
0433 }
0434 
0435 static void b53_srab_irq_disable(struct b53_device *dev, int port)
0436 {
0437     struct b53_srab_priv *priv = dev->priv;
0438     struct b53_srab_port_priv *p = &priv->port_intrs[port];
0439 
0440     if (p->irq_enabled) {
0441         free_irq(p->irq, p);
0442         p->irq_enabled = false;
0443     }
0444 }
0445 
0446 static void b53_srab_phylink_get_caps(struct b53_device *dev, int port,
0447                       struct phylink_config *config)
0448 {
0449     struct b53_srab_priv *priv = dev->priv;
0450     struct b53_srab_port_priv *p = &priv->port_intrs[port];
0451 
0452     switch (p->mode) {
0453     case PHY_INTERFACE_MODE_SGMII:
0454 #if IS_ENABLED(CONFIG_B53_SERDES)
0455         /* If p->mode indicates SGMII mode, that essentially means we
0456          * are using a serdes. As the serdes for the capabilities.
0457          */
0458         b53_serdes_phylink_get_caps(dev, port, config);
0459 #endif
0460         break;
0461 
0462     case PHY_INTERFACE_MODE_NA:
0463         break;
0464 
0465     case PHY_INTERFACE_MODE_RGMII:
0466         /* If we support RGMII, support all RGMII modes, since
0467          * that dictates the PHY delay settings.
0468          */
0469         phy_interface_set_rgmii(config->supported_interfaces);
0470         break;
0471 
0472     default:
0473         /* Some other mode (e.g. MII, GMII etc) */
0474         __set_bit(p->mode, config->supported_interfaces);
0475         break;
0476     }
0477 }
0478 
0479 static const struct b53_io_ops b53_srab_ops = {
0480     .read8 = b53_srab_read8,
0481     .read16 = b53_srab_read16,
0482     .read32 = b53_srab_read32,
0483     .read48 = b53_srab_read48,
0484     .read64 = b53_srab_read64,
0485     .write8 = b53_srab_write8,
0486     .write16 = b53_srab_write16,
0487     .write32 = b53_srab_write32,
0488     .write48 = b53_srab_write48,
0489     .write64 = b53_srab_write64,
0490     .irq_enable = b53_srab_irq_enable,
0491     .irq_disable = b53_srab_irq_disable,
0492     .phylink_get_caps = b53_srab_phylink_get_caps,
0493 #if IS_ENABLED(CONFIG_B53_SERDES)
0494     .phylink_mac_select_pcs = b53_serdes_phylink_mac_select_pcs,
0495     .serdes_map_lane = b53_srab_serdes_map_lane,
0496     .serdes_link_set = b53_serdes_link_set,
0497 #endif
0498 };
0499 
0500 static const struct of_device_id b53_srab_of_match[] = {
0501     { .compatible = "brcm,bcm53010-srab" },
0502     { .compatible = "brcm,bcm53011-srab" },
0503     { .compatible = "brcm,bcm53012-srab" },
0504     { .compatible = "brcm,bcm53018-srab" },
0505     { .compatible = "brcm,bcm53019-srab" },
0506     { .compatible = "brcm,bcm5301x-srab" },
0507     { .compatible = "brcm,bcm11360-srab", .data = (void *)BCM583XX_DEVICE_ID },
0508     { .compatible = "brcm,bcm58522-srab", .data = (void *)BCM58XX_DEVICE_ID },
0509     { .compatible = "brcm,bcm58525-srab", .data = (void *)BCM58XX_DEVICE_ID },
0510     { .compatible = "brcm,bcm58535-srab", .data = (void *)BCM58XX_DEVICE_ID },
0511     { .compatible = "brcm,bcm58622-srab", .data = (void *)BCM58XX_DEVICE_ID },
0512     { .compatible = "brcm,bcm58623-srab", .data = (void *)BCM58XX_DEVICE_ID },
0513     { .compatible = "brcm,bcm58625-srab", .data = (void *)BCM58XX_DEVICE_ID },
0514     { .compatible = "brcm,bcm88312-srab", .data = (void *)BCM58XX_DEVICE_ID },
0515     { .compatible = "brcm,cygnus-srab", .data = (void *)BCM583XX_DEVICE_ID },
0516     { .compatible = "brcm,nsp-srab", .data = (void *)BCM58XX_DEVICE_ID },
0517     { .compatible = "brcm,omega-srab", .data = (void *)BCM583XX_DEVICE_ID },
0518     { /* sentinel */ },
0519 };
0520 MODULE_DEVICE_TABLE(of, b53_srab_of_match);
0521 
0522 static void b53_srab_intr_set(struct b53_srab_priv *priv, bool set)
0523 {
0524     u32 reg;
0525 
0526     reg = readl(priv->regs + B53_SRAB_CTRLS);
0527     if (set)
0528         reg |= B53_SRAB_CTRLS_HOST_INTR;
0529     else
0530         reg &= ~B53_SRAB_CTRLS_HOST_INTR;
0531     writel(reg, priv->regs + B53_SRAB_CTRLS);
0532 }
0533 
0534 static void b53_srab_prepare_irq(struct platform_device *pdev)
0535 {
0536     struct b53_device *dev = platform_get_drvdata(pdev);
0537     struct b53_srab_priv *priv = dev->priv;
0538     struct b53_srab_port_priv *port;
0539     unsigned int i;
0540     char *name;
0541 
0542     /* Clear all pending interrupts */
0543     writel(0xffffffff, priv->regs + B53_SRAB_INTR);
0544 
0545     for (i = 0; i < B53_N_PORTS; i++) {
0546         port = &priv->port_intrs[i];
0547 
0548         /* There is no port 6 */
0549         if (i == 6)
0550             continue;
0551 
0552         name = kasprintf(GFP_KERNEL, "link_state_p%d", i);
0553         if (!name)
0554             return;
0555 
0556         port->num = i;
0557         port->dev = dev;
0558         port->irq = platform_get_irq_byname_optional(pdev, name);
0559         kfree(name);
0560     }
0561 
0562     b53_srab_intr_set(priv, true);
0563 }
0564 
0565 static void b53_srab_mux_init(struct platform_device *pdev)
0566 {
0567     struct b53_device *dev = platform_get_drvdata(pdev);
0568     struct b53_srab_priv *priv = dev->priv;
0569     struct b53_srab_port_priv *p;
0570     unsigned int port;
0571     u32 reg, off = 0;
0572     int ret;
0573 
0574     if (dev->pdata && dev->pdata->chip_id != BCM58XX_DEVICE_ID)
0575         return;
0576 
0577     priv->mux_config = devm_platform_ioremap_resource(pdev, 1);
0578     if (IS_ERR(priv->mux_config))
0579         return;
0580 
0581     /* Obtain the port mux configuration so we know which lanes
0582      * actually map to SerDes lanes
0583      */
0584     for (port = 5; port > 3; port--, off += 4) {
0585         p = &priv->port_intrs[port];
0586 
0587         reg = readl(priv->mux_config + B53_MUX_CONFIG_P5 + off);
0588         switch (reg & MUX_CONFIG_MASK) {
0589         case MUX_CONFIG_SGMII:
0590             p->mode = PHY_INTERFACE_MODE_SGMII;
0591             ret = b53_serdes_init(dev, port);
0592             if (ret)
0593                 continue;
0594             break;
0595         case MUX_CONFIG_MII_LITE:
0596             p->mode = PHY_INTERFACE_MODE_MII;
0597             break;
0598         case MUX_CONFIG_GMII:
0599             p->mode = PHY_INTERFACE_MODE_GMII;
0600             break;
0601         case MUX_CONFIG_RGMII:
0602             p->mode = PHY_INTERFACE_MODE_RGMII;
0603             break;
0604         case MUX_CONFIG_INTERNAL:
0605             p->mode = PHY_INTERFACE_MODE_INTERNAL;
0606             break;
0607         default:
0608             p->mode = PHY_INTERFACE_MODE_NA;
0609             break;
0610         }
0611 
0612         if (p->mode != PHY_INTERFACE_MODE_NA)
0613             dev_info(&pdev->dev, "Port %d mode: %s\n",
0614                  port, phy_modes(p->mode));
0615     }
0616 }
0617 
0618 static int b53_srab_probe(struct platform_device *pdev)
0619 {
0620     struct b53_platform_data *pdata = pdev->dev.platform_data;
0621     struct device_node *dn = pdev->dev.of_node;
0622     const struct of_device_id *of_id = NULL;
0623     struct b53_srab_priv *priv;
0624     struct b53_device *dev;
0625 
0626     if (dn)
0627         of_id = of_match_node(b53_srab_of_match, dn);
0628 
0629     if (of_id) {
0630         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0631         if (!pdata)
0632             return -ENOMEM;
0633 
0634         pdata->chip_id = (u32)(unsigned long)of_id->data;
0635     }
0636 
0637     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0638     if (!priv)
0639         return -ENOMEM;
0640 
0641     priv->regs = devm_platform_ioremap_resource(pdev, 0);
0642     if (IS_ERR(priv->regs))
0643         return PTR_ERR(priv->regs);
0644 
0645     dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, priv);
0646     if (!dev)
0647         return -ENOMEM;
0648 
0649     if (pdata)
0650         dev->pdata = pdata;
0651 
0652     platform_set_drvdata(pdev, dev);
0653 
0654     b53_srab_prepare_irq(pdev);
0655     b53_srab_mux_init(pdev);
0656 
0657     return b53_switch_register(dev);
0658 }
0659 
0660 static int b53_srab_remove(struct platform_device *pdev)
0661 {
0662     struct b53_device *dev = platform_get_drvdata(pdev);
0663 
0664     if (!dev)
0665         return 0;
0666 
0667     b53_srab_intr_set(dev->priv, false);
0668     b53_switch_remove(dev);
0669 
0670     platform_set_drvdata(pdev, NULL);
0671 
0672     return 0;
0673 }
0674 
0675 static void b53_srab_shutdown(struct platform_device *pdev)
0676 {
0677     struct b53_device *dev = platform_get_drvdata(pdev);
0678 
0679     if (!dev)
0680         return;
0681 
0682     b53_switch_shutdown(dev);
0683 
0684     platform_set_drvdata(pdev, NULL);
0685 }
0686 
0687 static struct platform_driver b53_srab_driver = {
0688     .probe = b53_srab_probe,
0689     .remove = b53_srab_remove,
0690     .shutdown = b53_srab_shutdown,
0691     .driver = {
0692         .name = "b53-srab-switch",
0693         .of_match_table = b53_srab_of_match,
0694     },
0695 };
0696 
0697 module_platform_driver(b53_srab_driver);
0698 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
0699 MODULE_DESCRIPTION("B53 Switch Register Access Bridge Registers (SRAB) access driver");
0700 MODULE_LICENSE("Dual BSD/GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!