dsa/b53/b53_serdes.h

0001 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
0002 /*
0003  * Northstar Plus switch SerDes/SGMII PHY definitions
0004  *
0005  * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
0006  */
0007
0008 #include <linux/phy.h>
0009 #include <linux/types.h>
0010
0011 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
0012 #define B53_SERDES_PAGE         0x16
0013 #define B53_SERDES_BLKADDR      0x3e
0014 #define B53_SERDES_LANE         0x3c
0015
0016 #define B53_SERDES_ID0          0x20
0017 #define  SERDES_ID0_MODEL_MASK      0x3f
0018 #define  SERDES_ID0_REV_NUM_SHIFT   11
0019 #define  SERDES_ID0_REV_NUM_MASK    0x7
0020 #define  SERDES_ID0_REV_LETTER_SHIFT    14
0021
0022 #define B53_SERDES_MII_REG(x)       (0x20 + (x) * 2)
0023 #define B53_SERDES_DIGITAL_CONTROL(x)   (0x1e + (x) * 2)
0024 #define B53_SERDES_DIGITAL_STATUS   0x28
0025
0026 /* SERDES_DIGITAL_CONTROL1 */
0027 #define  FIBER_MODE_1000X       BIT(0)
0028 #define  TBI_INTERFACE          BIT(1)
0029 #define  SIGNAL_DETECT_EN       BIT(2)
0030 #define  INVERT_SIGNAL_DETECT       BIT(3)
0031 #define  AUTODET_EN         BIT(4)
0032 #define  SGMII_MASTER_MODE      BIT(5)
0033 #define  DISABLE_DLL_PWRDOWN        BIT(6)
0034 #define  CRC_CHECKER_DIS        BIT(7)
0035 #define  COMMA_DET_EN           BIT(8)
0036 #define  ZERO_COMMA_DET_EN      BIT(9)
0037 #define  REMOTE_LOOPBACK        BIT(10)
0038 #define  SEL_RX_PKTS_FOR_CNTR       BIT(11)
0039 #define  MASTER_MDIO_PHY_SEL        BIT(13)
0040 #define  DISABLE_SIGNAL_DETECT_FLT  BIT(14)
0041
0042 /* SERDES_DIGITAL_CONTROL2 */
0043 #define  EN_PARALLEL_DET        BIT(0)
0044 #define  DIS_FALSE_LINK         BIT(1)
0045 #define  FLT_FORCE_LINK         BIT(2)
0046 #define  EN_AUTONEG_ERR_TIMER       BIT(3)
0047 #define  DIS_REMOTE_FAULT_SENSING   BIT(4)
0048 #define  FORCE_XMIT_DATA        BIT(5)
0049 #define  AUTONEG_FAST_TIMERS        BIT(6)
0050 #define  DIS_CARRIER_EXTEND     BIT(7)
0051 #define  DIS_TRRR_GENERATION        BIT(8)
0052 #define  BYPASS_PCS_RX          BIT(9)
0053 #define  BYPASS_PCS_TX          BIT(10)
0054 #define  TEST_CNTR_EN           BIT(11)
0055 #define  TX_PACKET_SEQ_TEST     BIT(12)
0056 #define  TX_IDLE_JAM_SEQ_TEST       BIT(13)
0057 #define  CLR_BER_CNTR           BIT(14)
0058
0059 /* SERDES_DIGITAL_CONTROL3 */
0060 #define  TX_FIFO_RST            BIT(0)
0061 #define  FIFO_ELAST_TX_RX_SHIFT     1
0062 #define  FIFO_ELAST_TX_RX_5K        0
0063 #define  FIFO_ELAST_TX_RX_10K       1
0064 #define  FIFO_ELAST_TX_RX_13_5K     2
0065 #define  FIFO_ELAST_TX_RX_18_5K     3
0066 #define  BLOCK_TXEN_MODE        BIT(9)
0067 #define  JAM_FALSE_CARRIER_MODE     BIT(10)
0068 #define  EXT_PHY_CRS_MODE       BIT(11)
0069 #define  INVERT_EXT_PHY_CRS     BIT(12)
0070 #define  DISABLE_TX_CRS         BIT(13)
0071
0072 /* SERDES_DIGITAL_STATUS */
0073 #define  SGMII_MODE         BIT(0)
0074 #define  LINK_STATUS            BIT(1)
0075 #define  DUPLEX_STATUS          BIT(2)
0076 #define  SPEED_STATUS_SHIFT     3
0077 #define  SPEED_STATUS_10        0
0078 #define  SPEED_STATUS_100       1
0079 #define  SPEED_STATUS_1000      2
0080 #define  SPEED_STATUS_2500      3
0081 #define  SPEED_STATUS_MASK      SPEED_STATUS_2500
0082 #define  PAUSE_RESOLUTION_TX_SIDE   BIT(5)
0083 #define  PAUSE_RESOLUTION_RX_SIDE   BIT(6)
0084 #define  LINK_STATUS_CHANGE     BIT(7)
0085 #define  EARLY_END_EXT_DET      BIT(8)
0086 #define  CARRIER_EXT_ERR_DET        BIT(9)
0087 #define  RX_ERR_DET         BIT(10)
0088 #define  TX_ERR_DET         BIT(11)
0089 #define  CRC_ERR_DET            BIT(12)
0090 #define  FALSE_CARRIER_ERR_DET      BIT(13)
0091 #define  RXFIFO_ERR_DET         BIT(14)
0092 #define  TXFIFO_ERR_DET         BIT(15)
0093
0094 /* Block offsets */
0095 #define SERDES_DIGITAL_BLK      0x8300
0096 #define SERDES_ID0          0x8310
0097 #define SERDES_MII_BLK          0xffe0
0098 #define SERDES_XGXSBLK0_BLOCKADDRESS    0xffd0
0099
0100 struct phylink_link_state;
0101
0102 static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
0103 {
0104     if (!dev->ops->serdes_map_lane)
0105         return B53_INVALID_LANE;
0106
0107     return dev->ops->serdes_map_lane(dev, port);
0108 }
0109
0110 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
0111              phy_interface_t interface, bool link_up);
0112 struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
0113                               int port,
0114                               phy_interface_t interface);
0115 void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
0116                  struct phylink_config *config);
0117 #if IS_ENABLED(CONFIG_B53_SERDES)
0118 int b53_serdes_init(struct b53_device *dev, int port);
0119 #else
0120 static inline int b53_serdes_init(struct b53_device *dev, int port)
0121 {
0122     return -ENODEV;
0123 }
0124 #endif