dsa/b53/b53_serdes.c

0001 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
0002 /*
0003  * Northstar Plus switch SerDes/SGMII PHY main logic
0004  *
0005  * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
0006  */
0007
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009
0010 #include <linux/delay.h>
0011 #include <linux/kernel.h>
0012 #include <linux/phy.h>
0013 #include <linux/phylink.h>
0014 #include <net/dsa.h>
0015
0016 #include "b53_priv.h"
0017 #include "b53_serdes.h"
0018 #include "b53_regs.h"
0019
0020 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs)
0021 {
0022     return container_of(pcs, struct b53_pcs, pcs);
0023 }
0024
0025 static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block,
0026                  u16 value)
0027 {
0028     b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
0029     b53_write16(dev, B53_SERDES_PAGE, offset, value);
0030 }
0031
0032 static u16 b53_serdes_read_blk(struct b53_device *dev, u8 offset, u16 block)
0033 {
0034     u16 value;
0035
0036     b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);
0037     b53_read16(dev, B53_SERDES_PAGE, offset, &value);
0038
0039     return value;
0040 }
0041
0042 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane)
0043 {
0044     if (dev->serdes_lane == lane)
0045         return;
0046
0047     WARN_ON(lane > 1);
0048
0049     b53_serdes_write_blk(dev, B53_SERDES_LANE,
0050                  SERDES_XGXSBLK0_BLOCKADDRESS, lane);
0051     dev->serdes_lane = lane;
0052 }
0053
0054 static void b53_serdes_write(struct b53_device *dev, u8 lane,
0055                  u8 offset, u16 block, u16 value)
0056 {
0057     b53_serdes_set_lane(dev, lane);
0058     b53_serdes_write_blk(dev, offset, block, value);
0059 }
0060
0061 static u16 b53_serdes_read(struct b53_device *dev, u8 lane,
0062                u8 offset, u16 block)
0063 {
0064     b53_serdes_set_lane(dev, lane);
0065     return b53_serdes_read_blk(dev, offset, block);
0066 }
0067
0068 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int mode,
0069                  phy_interface_t interface,
0070                  const unsigned long *advertising,
0071                  bool permit_pause_to_mac)
0072 {
0073     struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
0074     u8 lane = pcs_to_b53_pcs(pcs)->lane;
0075     u16 reg;
0076
0077     reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
0078                   SERDES_DIGITAL_BLK);
0079     if (interface == PHY_INTERFACE_MODE_1000BASEX)
0080         reg |= FIBER_MODE_1000X;
0081     else
0082         reg &= ~FIBER_MODE_1000X;
0083     b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),
0084              SERDES_DIGITAL_BLK, reg);
0085
0086     return 0;
0087 }
0088
0089 static void b53_serdes_an_restart(struct phylink_pcs *pcs)
0090 {
0091     struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
0092     u8 lane = pcs_to_b53_pcs(pcs)->lane;
0093     u16 reg;
0094
0095     reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
0096                   SERDES_MII_BLK);
0097     reg |= BMCR_ANRESTART;
0098     b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
0099              SERDES_MII_BLK, reg);
0100 }
0101
0102 static void b53_serdes_get_state(struct phylink_pcs *pcs,
0103                   struct phylink_link_state *state)
0104 {
0105     struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev;
0106     u8 lane = pcs_to_b53_pcs(pcs)->lane;
0107     u16 dig, bmsr;
0108
0109     dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS,
0110                   SERDES_DIGITAL_BLK);
0111     bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR),
0112                    SERDES_MII_BLK);
0113
0114     switch ((dig >> SPEED_STATUS_SHIFT) & SPEED_STATUS_MASK) {
0115     case SPEED_STATUS_10:
0116         state->speed = SPEED_10;
0117         break;
0118     case SPEED_STATUS_100:
0119         state->speed = SPEED_100;
0120         break;
0121     case SPEED_STATUS_1000:
0122         state->speed = SPEED_1000;
0123         break;
0124     default:
0125     case SPEED_STATUS_2500:
0126         state->speed = SPEED_2500;
0127         break;
0128     }
0129
0130     state->duplex = dig & DUPLEX_STATUS ? DUPLEX_FULL : DUPLEX_HALF;
0131     state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
0132     state->link = !!(dig & LINK_STATUS);
0133     if (dig & PAUSE_RESOLUTION_RX_SIDE)
0134         state->pause |= MLO_PAUSE_RX;
0135     if (dig & PAUSE_RESOLUTION_TX_SIDE)
0136         state->pause |= MLO_PAUSE_TX;
0137 }
0138
0139 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
0140              phy_interface_t interface, bool link_up)
0141 {
0142     u8 lane = b53_serdes_map_lane(dev, port);
0143     u16 reg;
0144
0145     if (lane == B53_INVALID_LANE)
0146         return;
0147
0148     reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
0149                   SERDES_MII_BLK);
0150     if (link_up)
0151         reg &= ~BMCR_PDOWN;
0152     else
0153         reg |= BMCR_PDOWN;
0154     b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),
0155              SERDES_MII_BLK, reg);
0156 }
0157 EXPORT_SYMBOL(b53_serdes_link_set);
0158
0159 static const struct phylink_pcs_ops b53_pcs_ops = {
0160     .pcs_get_state = b53_serdes_get_state,
0161     .pcs_config = b53_serdes_config,
0162     .pcs_an_restart = b53_serdes_an_restart,
0163 };
0164
0165 void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
0166                  struct phylink_config *config)
0167 {
0168     u8 lane = b53_serdes_map_lane(dev, port);
0169
0170     if (lane == B53_INVALID_LANE)
0171         return;
0172
0173     switch (lane) {
0174     case 0:
0175         /* It appears lane 0 supports 2500base-X and 1000base-X */
0176         __set_bit(PHY_INTERFACE_MODE_2500BASEX,
0177               config->supported_interfaces);
0178         config->mac_capabilities |= MAC_2500FD;
0179         fallthrough;
0180     case 1:
0181         /* It appears lane 1 only supports 1000base-X and SGMII */
0182         __set_bit(PHY_INTERFACE_MODE_1000BASEX,
0183               config->supported_interfaces);
0184         __set_bit(PHY_INTERFACE_MODE_SGMII,
0185               config->supported_interfaces);
0186         config->mac_capabilities |= MAC_1000FD;
0187         break;
0188     default:
0189         break;
0190     }
0191 }
0192 EXPORT_SYMBOL(b53_serdes_phylink_get_caps);
0193
0194 struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
0195                               int port,
0196                               phy_interface_t interface)
0197 {
0198     u8 lane = b53_serdes_map_lane(dev, port);
0199
0200     if (lane == B53_INVALID_LANE || lane >= B53_N_PCS ||
0201         !dev->pcs[lane].dev)
0202         return NULL;
0203
0204     if (!phy_interface_mode_is_8023z(interface) &&
0205         interface != PHY_INTERFACE_MODE_SGMII)
0206         return NULL;
0207
0208     return &dev->pcs[lane].pcs;
0209 }
0210 EXPORT_SYMBOL(b53_serdes_phylink_mac_select_pcs);
0211
0212 int b53_serdes_init(struct b53_device *dev, int port)
0213 {
0214     u8 lane = b53_serdes_map_lane(dev, port);
0215     struct b53_pcs *pcs;
0216     u16 id0, msb, lsb;
0217
0218     if (lane == B53_INVALID_LANE)
0219         return -EINVAL;
0220
0221     id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0);
0222     msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1),
0223                   SERDES_MII_BLK);
0224     lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2),
0225                   SERDES_MII_BLK);
0226     if (id0 == 0 || id0 == 0xffff) {
0227         dev_err(dev->dev, "SerDes not initialized, check settings\n");
0228         return -ENODEV;
0229     }
0230
0231     dev_info(dev->dev,
0232          "SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n",
0233          lane, id0 & SERDES_ID0_MODEL_MASK,
0234          (id0 >> SERDES_ID0_REV_LETTER_SHIFT) + 0x41,
0235          (id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK,
0236          (u32)msb << 16 | lsb);
0237
0238     pcs = &dev->pcs[lane];
0239     pcs->dev = dev;
0240     pcs->lane = lane;
0241     pcs->pcs.ops = &b53_pcs_ops;
0242
0243     return 0;
0244 }
0245 EXPORT_SYMBOL(b53_serdes_init);
0246
0247 MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
0248 MODULE_DESCRIPTION("B53 Switch SerDes driver");
0249 MODULE_LICENSE("Dual BSD/GPL");