dsa/b53/b53_common.c

0001 /*
0002  * B53 switch driver main logic
0003  *
0004  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
0005  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
0006  *
0007  * Permission to use, copy, modify, and/or distribute this software for any
0008  * purpose with or without fee is hereby granted, provided that the above
0009  * copyright notice and this permission notice appear in all copies.
0010  *
0011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0018  */
0019
0020 #include <linux/delay.h>
0021 #include <linux/export.h>
0022 #include <linux/gpio.h>
0023 #include <linux/kernel.h>
0024 #include <linux/module.h>
0025 #include <linux/platform_data/b53.h>
0026 #include <linux/phy.h>
0027 #include <linux/phylink.h>
0028 #include <linux/etherdevice.h>
0029 #include <linux/if_bridge.h>
0030 #include <net/dsa.h>
0031
0032 #include "b53_regs.h"
0033 #include "b53_priv.h"
0034
0035 struct b53_mib_desc {
0036     u8 size;
0037     u8 offset;
0038     const char *name;
0039 };
0040
0041 /* BCM5365 MIB counters */
0042 static const struct b53_mib_desc b53_mibs_65[] = {
0043     { 8, 0x00, "TxOctets" },
0044     { 4, 0x08, "TxDropPkts" },
0045     { 4, 0x10, "TxBroadcastPkts" },
0046     { 4, 0x14, "TxMulticastPkts" },
0047     { 4, 0x18, "TxUnicastPkts" },
0048     { 4, 0x1c, "TxCollisions" },
0049     { 4, 0x20, "TxSingleCollision" },
0050     { 4, 0x24, "TxMultipleCollision" },
0051     { 4, 0x28, "TxDeferredTransmit" },
0052     { 4, 0x2c, "TxLateCollision" },
0053     { 4, 0x30, "TxExcessiveCollision" },
0054     { 4, 0x38, "TxPausePkts" },
0055     { 8, 0x44, "RxOctets" },
0056     { 4, 0x4c, "RxUndersizePkts" },
0057     { 4, 0x50, "RxPausePkts" },
0058     { 4, 0x54, "Pkts64Octets" },
0059     { 4, 0x58, "Pkts65to127Octets" },
0060     { 4, 0x5c, "Pkts128to255Octets" },
0061     { 4, 0x60, "Pkts256to511Octets" },
0062     { 4, 0x64, "Pkts512to1023Octets" },
0063     { 4, 0x68, "Pkts1024to1522Octets" },
0064     { 4, 0x6c, "RxOversizePkts" },
0065     { 4, 0x70, "RxJabbers" },
0066     { 4, 0x74, "RxAlignmentErrors" },
0067     { 4, 0x78, "RxFCSErrors" },
0068     { 8, 0x7c, "RxGoodOctets" },
0069     { 4, 0x84, "RxDropPkts" },
0070     { 4, 0x88, "RxUnicastPkts" },
0071     { 4, 0x8c, "RxMulticastPkts" },
0072     { 4, 0x90, "RxBroadcastPkts" },
0073     { 4, 0x94, "RxSAChanges" },
0074     { 4, 0x98, "RxFragments" },
0075 };
0076
0077 #define B53_MIBS_65_SIZE    ARRAY_SIZE(b53_mibs_65)
0078
0079 /* BCM63xx MIB counters */
0080 static const struct b53_mib_desc b53_mibs_63xx[] = {
0081     { 8, 0x00, "TxOctets" },
0082     { 4, 0x08, "TxDropPkts" },
0083     { 4, 0x0c, "TxQoSPkts" },
0084     { 4, 0x10, "TxBroadcastPkts" },
0085     { 4, 0x14, "TxMulticastPkts" },
0086     { 4, 0x18, "TxUnicastPkts" },
0087     { 4, 0x1c, "TxCollisions" },
0088     { 4, 0x20, "TxSingleCollision" },
0089     { 4, 0x24, "TxMultipleCollision" },
0090     { 4, 0x28, "TxDeferredTransmit" },
0091     { 4, 0x2c, "TxLateCollision" },
0092     { 4, 0x30, "TxExcessiveCollision" },
0093     { 4, 0x38, "TxPausePkts" },
0094     { 8, 0x3c, "TxQoSOctets" },
0095     { 8, 0x44, "RxOctets" },
0096     { 4, 0x4c, "RxUndersizePkts" },
0097     { 4, 0x50, "RxPausePkts" },
0098     { 4, 0x54, "Pkts64Octets" },
0099     { 4, 0x58, "Pkts65to127Octets" },
0100     { 4, 0x5c, "Pkts128to255Octets" },
0101     { 4, 0x60, "Pkts256to511Octets" },
0102     { 4, 0x64, "Pkts512to1023Octets" },
0103     { 4, 0x68, "Pkts1024to1522Octets" },
0104     { 4, 0x6c, "RxOversizePkts" },
0105     { 4, 0x70, "RxJabbers" },
0106     { 4, 0x74, "RxAlignmentErrors" },
0107     { 4, 0x78, "RxFCSErrors" },
0108     { 8, 0x7c, "RxGoodOctets" },
0109     { 4, 0x84, "RxDropPkts" },
0110     { 4, 0x88, "RxUnicastPkts" },
0111     { 4, 0x8c, "RxMulticastPkts" },
0112     { 4, 0x90, "RxBroadcastPkts" },
0113     { 4, 0x94, "RxSAChanges" },
0114     { 4, 0x98, "RxFragments" },
0115     { 4, 0xa0, "RxSymbolErrors" },
0116     { 4, 0xa4, "RxQoSPkts" },
0117     { 8, 0xa8, "RxQoSOctets" },
0118     { 4, 0xb0, "Pkts1523to2047Octets" },
0119     { 4, 0xb4, "Pkts2048to4095Octets" },
0120     { 4, 0xb8, "Pkts4096to8191Octets" },
0121     { 4, 0xbc, "Pkts8192to9728Octets" },
0122     { 4, 0xc0, "RxDiscarded" },
0123 };
0124
0125 #define B53_MIBS_63XX_SIZE  ARRAY_SIZE(b53_mibs_63xx)
0126
0127 /* MIB counters */
0128 static const struct b53_mib_desc b53_mibs[] = {
0129     { 8, 0x00, "TxOctets" },
0130     { 4, 0x08, "TxDropPkts" },
0131     { 4, 0x10, "TxBroadcastPkts" },
0132     { 4, 0x14, "TxMulticastPkts" },
0133     { 4, 0x18, "TxUnicastPkts" },
0134     { 4, 0x1c, "TxCollisions" },
0135     { 4, 0x20, "TxSingleCollision" },
0136     { 4, 0x24, "TxMultipleCollision" },
0137     { 4, 0x28, "TxDeferredTransmit" },
0138     { 4, 0x2c, "TxLateCollision" },
0139     { 4, 0x30, "TxExcessiveCollision" },
0140     { 4, 0x38, "TxPausePkts" },
0141     { 8, 0x50, "RxOctets" },
0142     { 4, 0x58, "RxUndersizePkts" },
0143     { 4, 0x5c, "RxPausePkts" },
0144     { 4, 0x60, "Pkts64Octets" },
0145     { 4, 0x64, "Pkts65to127Octets" },
0146     { 4, 0x68, "Pkts128to255Octets" },
0147     { 4, 0x6c, "Pkts256to511Octets" },
0148     { 4, 0x70, "Pkts512to1023Octets" },
0149     { 4, 0x74, "Pkts1024to1522Octets" },
0150     { 4, 0x78, "RxOversizePkts" },
0151     { 4, 0x7c, "RxJabbers" },
0152     { 4, 0x80, "RxAlignmentErrors" },
0153     { 4, 0x84, "RxFCSErrors" },
0154     { 8, 0x88, "RxGoodOctets" },
0155     { 4, 0x90, "RxDropPkts" },
0156     { 4, 0x94, "RxUnicastPkts" },
0157     { 4, 0x98, "RxMulticastPkts" },
0158     { 4, 0x9c, "RxBroadcastPkts" },
0159     { 4, 0xa0, "RxSAChanges" },
0160     { 4, 0xa4, "RxFragments" },
0161     { 4, 0xa8, "RxJumboPkts" },
0162     { 4, 0xac, "RxSymbolErrors" },
0163     { 4, 0xc0, "RxDiscarded" },
0164 };
0165
0166 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
0167
0168 static const struct b53_mib_desc b53_mibs_58xx[] = {
0169     { 8, 0x00, "TxOctets" },
0170     { 4, 0x08, "TxDropPkts" },
0171     { 4, 0x0c, "TxQPKTQ0" },
0172     { 4, 0x10, "TxBroadcastPkts" },
0173     { 4, 0x14, "TxMulticastPkts" },
0174     { 4, 0x18, "TxUnicastPKts" },
0175     { 4, 0x1c, "TxCollisions" },
0176     { 4, 0x20, "TxSingleCollision" },
0177     { 4, 0x24, "TxMultipleCollision" },
0178     { 4, 0x28, "TxDeferredCollision" },
0179     { 4, 0x2c, "TxLateCollision" },
0180     { 4, 0x30, "TxExcessiveCollision" },
0181     { 4, 0x34, "TxFrameInDisc" },
0182     { 4, 0x38, "TxPausePkts" },
0183     { 4, 0x3c, "TxQPKTQ1" },
0184     { 4, 0x40, "TxQPKTQ2" },
0185     { 4, 0x44, "TxQPKTQ3" },
0186     { 4, 0x48, "TxQPKTQ4" },
0187     { 4, 0x4c, "TxQPKTQ5" },
0188     { 8, 0x50, "RxOctets" },
0189     { 4, 0x58, "RxUndersizePkts" },
0190     { 4, 0x5c, "RxPausePkts" },
0191     { 4, 0x60, "RxPkts64Octets" },
0192     { 4, 0x64, "RxPkts65to127Octets" },
0193     { 4, 0x68, "RxPkts128to255Octets" },
0194     { 4, 0x6c, "RxPkts256to511Octets" },
0195     { 4, 0x70, "RxPkts512to1023Octets" },
0196     { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
0197     { 4, 0x78, "RxOversizePkts" },
0198     { 4, 0x7c, "RxJabbers" },
0199     { 4, 0x80, "RxAlignmentErrors" },
0200     { 4, 0x84, "RxFCSErrors" },
0201     { 8, 0x88, "RxGoodOctets" },
0202     { 4, 0x90, "RxDropPkts" },
0203     { 4, 0x94, "RxUnicastPkts" },
0204     { 4, 0x98, "RxMulticastPkts" },
0205     { 4, 0x9c, "RxBroadcastPkts" },
0206     { 4, 0xa0, "RxSAChanges" },
0207     { 4, 0xa4, "RxFragments" },
0208     { 4, 0xa8, "RxJumboPkt" },
0209     { 4, 0xac, "RxSymblErr" },
0210     { 4, 0xb0, "InRangeErrCount" },
0211     { 4, 0xb4, "OutRangeErrCount" },
0212     { 4, 0xb8, "EEELpiEvent" },
0213     { 4, 0xbc, "EEELpiDuration" },
0214     { 4, 0xc0, "RxDiscard" },
0215     { 4, 0xc8, "TxQPKTQ6" },
0216     { 4, 0xcc, "TxQPKTQ7" },
0217     { 4, 0xd0, "TxPkts64Octets" },
0218     { 4, 0xd4, "TxPkts65to127Octets" },
0219     { 4, 0xd8, "TxPkts128to255Octets" },
0220     { 4, 0xdc, "TxPkts256to511Ocets" },
0221     { 4, 0xe0, "TxPkts512to1023Ocets" },
0222     { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
0223 };
0224
0225 #define B53_MIBS_58XX_SIZE  ARRAY_SIZE(b53_mibs_58xx)
0226
0227 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
0228 {
0229     unsigned int i;
0230
0231     b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
0232
0233     for (i = 0; i < 10; i++) {
0234         u8 vta;
0235
0236         b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
0237         if (!(vta & VTA_START_CMD))
0238             return 0;
0239
0240         usleep_range(100, 200);
0241     }
0242
0243     return -EIO;
0244 }
0245
0246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
0247                    struct b53_vlan *vlan)
0248 {
0249     if (is5325(dev)) {
0250         u32 entry = 0;
0251
0252         if (vlan->members) {
0253             entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
0254                  VA_UNTAG_S_25) | vlan->members;
0255             if (dev->core_rev >= 3)
0256                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
0257             else
0258                 entry |= VA_VALID_25;
0259         }
0260
0261         b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
0262         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
0263                 VTA_RW_STATE_WR | VTA_RW_OP_EN);
0264     } else if (is5365(dev)) {
0265         u16 entry = 0;
0266
0267         if (vlan->members)
0268             entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
0269                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
0270
0271         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
0272         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
0273                 VTA_RW_STATE_WR | VTA_RW_OP_EN);
0274     } else {
0275         b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
0276         b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
0277                 (vlan->untag << VTE_UNTAG_S) | vlan->members);
0278
0279         b53_do_vlan_op(dev, VTA_CMD_WRITE);
0280     }
0281
0282     dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
0283         vid, vlan->members, vlan->untag);
0284 }
0285
0286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
0287                    struct b53_vlan *vlan)
0288 {
0289     if (is5325(dev)) {
0290         u32 entry = 0;
0291
0292         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
0293                 VTA_RW_STATE_RD | VTA_RW_OP_EN);
0294         b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
0295
0296         if (dev->core_rev >= 3)
0297             vlan->valid = !!(entry & VA_VALID_25_R4);
0298         else
0299             vlan->valid = !!(entry & VA_VALID_25);
0300         vlan->members = entry & VA_MEMBER_MASK;
0301         vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
0302
0303     } else if (is5365(dev)) {
0304         u16 entry = 0;
0305
0306         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
0307                 VTA_RW_STATE_WR | VTA_RW_OP_EN);
0308         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
0309
0310         vlan->valid = !!(entry & VA_VALID_65);
0311         vlan->members = entry & VA_MEMBER_MASK;
0312         vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
0313     } else {
0314         u32 entry = 0;
0315
0316         b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
0317         b53_do_vlan_op(dev, VTA_CMD_READ);
0318         b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
0319         vlan->members = entry & VTE_MEMBERS;
0320         vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
0321         vlan->valid = true;
0322     }
0323 }
0324
0325 static void b53_set_forwarding(struct b53_device *dev, int enable)
0326 {
0327     u8 mgmt;
0328
0329     b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
0330
0331     if (enable)
0332         mgmt |= SM_SW_FWD_EN;
0333     else
0334         mgmt &= ~SM_SW_FWD_EN;
0335
0336     b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
0337
0338     /* Include IMP port in dumb forwarding mode
0339      */
0340     b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
0341     mgmt |= B53_MII_DUMB_FWDG_EN;
0342     b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
0343
0344     /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
0345      * frames should be flooded or not.
0346      */
0347     b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
0348     mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
0349     b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
0350 }
0351
0352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
0353                 bool enable_filtering)
0354 {
0355     u8 mgmt, vc0, vc1, vc4 = 0, vc5;
0356
0357     b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
0358     b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
0359     b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
0360
0361     if (is5325(dev) || is5365(dev)) {
0362         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
0363         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
0364     } else if (is63xx(dev)) {
0365         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
0366         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
0367     } else {
0368         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
0369         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
0370     }
0371
0372     if (enable) {
0373         vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
0374         vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
0375         vc4 &= ~VC4_ING_VID_CHECK_MASK;
0376         if (enable_filtering) {
0377             vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
0378             vc5 |= VC5_DROP_VTABLE_MISS;
0379         } else {
0380             vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
0381             vc5 &= ~VC5_DROP_VTABLE_MISS;
0382         }
0383
0384         if (is5325(dev))
0385             vc0 &= ~VC0_RESERVED_1;
0386
0387         if (is5325(dev) || is5365(dev))
0388             vc1 |= VC1_RX_MCST_TAG_EN;
0389
0390     } else {
0391         vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
0392         vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
0393         vc4 &= ~VC4_ING_VID_CHECK_MASK;
0394         vc5 &= ~VC5_DROP_VTABLE_MISS;
0395
0396         if (is5325(dev) || is5365(dev))
0397             vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
0398         else
0399             vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
0400
0401         if (is5325(dev) || is5365(dev))
0402             vc1 &= ~VC1_RX_MCST_TAG_EN;
0403     }
0404
0405     if (!is5325(dev) && !is5365(dev))
0406         vc5 &= ~VC5_VID_FFF_EN;
0407
0408     b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
0409     b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
0410
0411     if (is5325(dev) || is5365(dev)) {
0412         /* enable the high 8 bit vid check on 5325 */
0413         if (is5325(dev) && enable)
0414             b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
0415                    VC3_HIGH_8BIT_EN);
0416         else
0417             b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
0418
0419         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
0420         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
0421     } else if (is63xx(dev)) {
0422         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
0423         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
0424         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
0425     } else {
0426         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
0427         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
0428         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
0429     }
0430
0431     b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
0432
0433     dev->vlan_enabled = enable;
0434
0435     dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
0436         port, enable, enable_filtering);
0437 }
0438
0439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
0440 {
0441     u32 port_mask = 0;
0442     u16 max_size = JMS_MIN_SIZE;
0443
0444     if (is5325(dev) || is5365(dev))
0445         return -EINVAL;
0446
0447     if (enable) {
0448         port_mask = dev->enabled_ports;
0449         max_size = JMS_MAX_SIZE;
0450         if (allow_10_100)
0451             port_mask |= JPM_10_100_JUMBO_EN;
0452     }
0453
0454     b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
0455     return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
0456 }
0457
0458 static int b53_flush_arl(struct b53_device *dev, u8 mask)
0459 {
0460     unsigned int i;
0461
0462     b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
0463            FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
0464
0465     for (i = 0; i < 10; i++) {
0466         u8 fast_age_ctrl;
0467
0468         b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
0469               &fast_age_ctrl);
0470
0471         if (!(fast_age_ctrl & FAST_AGE_DONE))
0472             goto out;
0473
0474         msleep(1);
0475     }
0476
0477     return -ETIMEDOUT;
0478 out:
0479     /* Only age dynamic entries (default behavior) */
0480     b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
0481     return 0;
0482 }
0483
0484 static int b53_fast_age_port(struct b53_device *dev, int port)
0485 {
0486     b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
0487
0488     return b53_flush_arl(dev, FAST_AGE_PORT);
0489 }
0490
0491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
0492 {
0493     b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
0494
0495     return b53_flush_arl(dev, FAST_AGE_VLAN);
0496 }
0497
0498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
0499 {
0500     struct b53_device *dev = ds->priv;
0501     unsigned int i;
0502     u16 pvlan;
0503
0504     /* Enable the IMP port to be in the same VLAN as the other ports
0505      * on a per-port basis such that we only have Port i and IMP in
0506      * the same VLAN.
0507      */
0508     b53_for_each_port(dev, i) {
0509         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
0510         pvlan |= BIT(cpu_port);
0511         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
0512     }
0513 }
0514 EXPORT_SYMBOL(b53_imp_vlan_setup);
0515
0516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
0517                      bool unicast)
0518 {
0519     u16 uc;
0520
0521     b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
0522     if (unicast)
0523         uc |= BIT(port);
0524     else
0525         uc &= ~BIT(port);
0526     b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
0527 }
0528
0529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
0530                      bool multicast)
0531 {
0532     u16 mc;
0533
0534     b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
0535     if (multicast)
0536         mc |= BIT(port);
0537     else
0538         mc &= ~BIT(port);
0539     b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
0540
0541     b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
0542     if (multicast)
0543         mc |= BIT(port);
0544     else
0545         mc &= ~BIT(port);
0546     b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
0547 }
0548
0549 static void b53_port_set_learning(struct b53_device *dev, int port,
0550                   bool learning)
0551 {
0552     u16 reg;
0553
0554     b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
0555     if (learning)
0556         reg &= ~BIT(port);
0557     else
0558         reg |= BIT(port);
0559     b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
0560 }
0561
0562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
0563 {
0564     struct b53_device *dev = ds->priv;
0565     unsigned int cpu_port;
0566     int ret = 0;
0567     u16 pvlan;
0568
0569     if (!dsa_is_user_port(ds, port))
0570         return 0;
0571
0572     cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
0573
0574     b53_port_set_ucast_flood(dev, port, true);
0575     b53_port_set_mcast_flood(dev, port, true);
0576     b53_port_set_learning(dev, port, false);
0577
0578     if (dev->ops->irq_enable)
0579         ret = dev->ops->irq_enable(dev, port);
0580     if (ret)
0581         return ret;
0582
0583     /* Clear the Rx and Tx disable bits and set to no spanning tree */
0584     b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
0585
0586     /* Set this port, and only this one to be in the default VLAN,
0587      * if member of a bridge, restore its membership prior to
0588      * bringing down this port.
0589      */
0590     b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
0591     pvlan &= ~0x1ff;
0592     pvlan |= BIT(port);
0593     pvlan |= dev->ports[port].vlan_ctl_mask;
0594     b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
0595
0596     b53_imp_vlan_setup(ds, cpu_port);
0597
0598     /* If EEE was enabled, restore it */
0599     if (dev->ports[port].eee.eee_enabled)
0600         b53_eee_enable_set(ds, port, true);
0601
0602     return 0;
0603 }
0604 EXPORT_SYMBOL(b53_enable_port);
0605
0606 void b53_disable_port(struct dsa_switch *ds, int port)
0607 {
0608     struct b53_device *dev = ds->priv;
0609     u8 reg;
0610
0611     /* Disable Tx/Rx for the port */
0612     b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
0613     reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
0614     b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
0615
0616     if (dev->ops->irq_disable)
0617         dev->ops->irq_disable(dev, port);
0618 }
0619 EXPORT_SYMBOL(b53_disable_port);
0620
0621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
0622 {
0623     struct b53_device *dev = ds->priv;
0624     bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
0625     u8 hdr_ctl, val;
0626     u16 reg;
0627
0628     /* Resolve which bit controls the Broadcom tag */
0629     switch (port) {
0630     case 8:
0631         val = BRCM_HDR_P8_EN;
0632         break;
0633     case 7:
0634         val = BRCM_HDR_P7_EN;
0635         break;
0636     case 5:
0637         val = BRCM_HDR_P5_EN;
0638         break;
0639     default:
0640         val = 0;
0641         break;
0642     }
0643
0644     /* Enable management mode if tagging is requested */
0645     b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
0646     if (tag_en)
0647         hdr_ctl |= SM_SW_FWD_MODE;
0648     else
0649         hdr_ctl &= ~SM_SW_FWD_MODE;
0650     b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
0651
0652     /* Configure the appropriate IMP port */
0653     b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
0654     if (port == 8)
0655         hdr_ctl |= GC_FRM_MGMT_PORT_MII;
0656     else if (port == 5)
0657         hdr_ctl |= GC_FRM_MGMT_PORT_M;
0658     b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
0659
0660     /* Enable Broadcom tags for IMP port */
0661     b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
0662     if (tag_en)
0663         hdr_ctl |= val;
0664     else
0665         hdr_ctl &= ~val;
0666     b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
0667
0668     /* Registers below are only accessible on newer devices */
0669     if (!is58xx(dev))
0670         return;
0671
0672     /* Enable reception Broadcom tag for CPU TX (switch RX) to
0673      * allow us to tag outgoing frames
0674      */
0675     b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
0676     if (tag_en)
0677         reg &= ~BIT(port);
0678     else
0679         reg |= BIT(port);
0680     b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
0681
0682     /* Enable transmission of Broadcom tags from the switch (CPU RX) to
0683      * allow delivering frames to the per-port net_devices
0684      */
0685     b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
0686     if (tag_en)
0687         reg &= ~BIT(port);
0688     else
0689         reg |= BIT(port);
0690     b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
0691 }
0692 EXPORT_SYMBOL(b53_brcm_hdr_setup);
0693
0694 static void b53_enable_cpu_port(struct b53_device *dev, int port)
0695 {
0696     u8 port_ctrl;
0697
0698     /* BCM5325 CPU port is at 8 */
0699     if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
0700         port = B53_CPU_PORT;
0701
0702     port_ctrl = PORT_CTRL_RX_BCST_EN |
0703             PORT_CTRL_RX_MCST_EN |
0704             PORT_CTRL_RX_UCST_EN;
0705     b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
0706
0707     b53_brcm_hdr_setup(dev->ds, port);
0708
0709     b53_port_set_ucast_flood(dev, port, true);
0710     b53_port_set_mcast_flood(dev, port, true);
0711     b53_port_set_learning(dev, port, false);
0712 }
0713
0714 static void b53_enable_mib(struct b53_device *dev)
0715 {
0716     u8 gc;
0717
0718     b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
0719     gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
0720     b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
0721 }
0722
0723 static u16 b53_default_pvid(struct b53_device *dev)
0724 {
0725     if (is5325(dev) || is5365(dev))
0726         return 1;
0727     else
0728         return 0;
0729 }
0730
0731 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
0732 {
0733     struct b53_device *dev = ds->priv;
0734
0735     return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
0736 }
0737
0738 int b53_configure_vlan(struct dsa_switch *ds)
0739 {
0740     struct b53_device *dev = ds->priv;
0741     struct b53_vlan vl = { 0 };
0742     struct b53_vlan *v;
0743     int i, def_vid;
0744     u16 vid;
0745
0746     def_vid = b53_default_pvid(dev);
0747
0748     /* clear all vlan entries */
0749     if (is5325(dev) || is5365(dev)) {
0750         for (i = def_vid; i < dev->num_vlans; i++)
0751             b53_set_vlan_entry(dev, i, &vl);
0752     } else {
0753         b53_do_vlan_op(dev, VTA_CMD_CLEAR);
0754     }
0755
0756     b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
0757
0758     /* Create an untagged VLAN entry for the default PVID in case
0759      * CONFIG_VLAN_8021Q is disabled and there are no calls to
0760      * dsa_slave_vlan_rx_add_vid() to create the default VLAN
0761      * entry. Do this only when the tagging protocol is not
0762      * DSA_TAG_PROTO_NONE
0763      */
0764     b53_for_each_port(dev, i) {
0765         v = &dev->vlans[def_vid];
0766         v->members |= BIT(i);
0767         if (!b53_vlan_port_needs_forced_tagged(ds, i))
0768             v->untag = v->members;
0769         b53_write16(dev, B53_VLAN_PAGE,
0770                 B53_VLAN_PORT_DEF_TAG(i), def_vid);
0771     }
0772
0773     /* Upon initial call we have not set-up any VLANs, but upon
0774      * system resume, we need to restore all VLAN entries.
0775      */
0776     for (vid = def_vid; vid < dev->num_vlans; vid++) {
0777         v = &dev->vlans[vid];
0778
0779         if (!v->members)
0780             continue;
0781
0782         b53_set_vlan_entry(dev, vid, v);
0783         b53_fast_age_vlan(dev, vid);
0784     }
0785
0786     return 0;
0787 }
0788 EXPORT_SYMBOL(b53_configure_vlan);
0789
0790 static void b53_switch_reset_gpio(struct b53_device *dev)
0791 {
0792     int gpio = dev->reset_gpio;
0793
0794     if (gpio < 0)
0795         return;
0796
0797     /* Reset sequence: RESET low(50ms)->high(20ms)
0798      */
0799     gpio_set_value(gpio, 0);
0800     mdelay(50);
0801
0802     gpio_set_value(gpio, 1);
0803     mdelay(20);
0804
0805     dev->current_page = 0xff;
0806 }
0807
0808 static int b53_switch_reset(struct b53_device *dev)
0809 {
0810     unsigned int timeout = 1000;
0811     u8 mgmt, reg;
0812
0813     b53_switch_reset_gpio(dev);
0814
0815     if (is539x(dev)) {
0816         b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
0817         b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
0818     }
0819
0820     /* This is specific to 58xx devices here, do not use is58xx() which
0821      * covers the larger Starfigther 2 family, including 7445/7278 which
0822      * still use this driver as a library and need to perform the reset
0823      * earlier.
0824      */
0825     if (dev->chip_id == BCM58XX_DEVICE_ID ||
0826         dev->chip_id == BCM583XX_DEVICE_ID) {
0827         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
0828         reg |= SW_RST | EN_SW_RST | EN_CH_RST;
0829         b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
0830
0831         do {
0832             b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
0833             if (!(reg & SW_RST))
0834                 break;
0835
0836             usleep_range(1000, 2000);
0837         } while (timeout-- > 0);
0838
0839         if (timeout == 0) {
0840             dev_err(dev->dev,
0841                 "Timeout waiting for SW_RST to clear!\n");
0842             return -ETIMEDOUT;
0843         }
0844     }
0845
0846     b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
0847
0848     if (!(mgmt & SM_SW_FWD_EN)) {
0849         mgmt &= ~SM_SW_FWD_MODE;
0850         mgmt |= SM_SW_FWD_EN;
0851
0852         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
0853         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
0854
0855         if (!(mgmt & SM_SW_FWD_EN)) {
0856             dev_err(dev->dev, "Failed to enable switch!\n");
0857             return -EINVAL;
0858         }
0859     }
0860
0861     b53_enable_mib(dev);
0862
0863     return b53_flush_arl(dev, FAST_AGE_STATIC);
0864 }
0865
0866 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
0867 {
0868     struct b53_device *priv = ds->priv;
0869     u16 value = 0;
0870     int ret;
0871
0872     if (priv->ops->phy_read16)
0873         ret = priv->ops->phy_read16(priv, addr, reg, &value);
0874     else
0875         ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
0876                  reg * 2, &value);
0877
0878     return ret ? ret : value;
0879 }
0880
0881 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
0882 {
0883     struct b53_device *priv = ds->priv;
0884
0885     if (priv->ops->phy_write16)
0886         return priv->ops->phy_write16(priv, addr, reg, val);
0887
0888     return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
0889 }
0890
0891 static int b53_reset_switch(struct b53_device *priv)
0892 {
0893     /* reset vlans */
0894     memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
0895     memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
0896
0897     priv->serdes_lane = B53_INVALID_LANE;
0898
0899     return b53_switch_reset(priv);
0900 }
0901
0902 static int b53_apply_config(struct b53_device *priv)
0903 {
0904     /* disable switching */
0905     b53_set_forwarding(priv, 0);
0906
0907     b53_configure_vlan(priv->ds);
0908
0909     /* enable switching */
0910     b53_set_forwarding(priv, 1);
0911
0912     return 0;
0913 }
0914
0915 static void b53_reset_mib(struct b53_device *priv)
0916 {
0917     u8 gc;
0918
0919     b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
0920
0921     b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
0922     msleep(1);
0923     b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
0924     msleep(1);
0925 }
0926
0927 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
0928 {
0929     if (is5365(dev))
0930         return b53_mibs_65;
0931     else if (is63xx(dev))
0932         return b53_mibs_63xx;
0933     else if (is58xx(dev))
0934         return b53_mibs_58xx;
0935     else
0936         return b53_mibs;
0937 }
0938
0939 static unsigned int b53_get_mib_size(struct b53_device *dev)
0940 {
0941     if (is5365(dev))
0942         return B53_MIBS_65_SIZE;
0943     else if (is63xx(dev))
0944         return B53_MIBS_63XX_SIZE;
0945     else if (is58xx(dev))
0946         return B53_MIBS_58XX_SIZE;
0947     else
0948         return B53_MIBS_SIZE;
0949 }
0950
0951 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
0952 {
0953     /* These ports typically do not have built-in PHYs */
0954     switch (port) {
0955     case B53_CPU_PORT_25:
0956     case 7:
0957     case B53_CPU_PORT:
0958         return NULL;
0959     }
0960
0961     return mdiobus_get_phy(ds->slave_mii_bus, port);
0962 }
0963
0964 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
0965              uint8_t *data)
0966 {
0967     struct b53_device *dev = ds->priv;
0968     const struct b53_mib_desc *mibs = b53_get_mib(dev);
0969     unsigned int mib_size = b53_get_mib_size(dev);
0970     struct phy_device *phydev;
0971     unsigned int i;
0972
0973     if (stringset == ETH_SS_STATS) {
0974         for (i = 0; i < mib_size; i++)
0975             strlcpy(data + i * ETH_GSTRING_LEN,
0976                 mibs[i].name, ETH_GSTRING_LEN);
0977     } else if (stringset == ETH_SS_PHY_STATS) {
0978         phydev = b53_get_phy_device(ds, port);
0979         if (!phydev)
0980             return;
0981
0982         phy_ethtool_get_strings(phydev, data);
0983     }
0984 }
0985 EXPORT_SYMBOL(b53_get_strings);
0986
0987 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
0988 {
0989     struct b53_device *dev = ds->priv;
0990     const struct b53_mib_desc *mibs = b53_get_mib(dev);
0991     unsigned int mib_size = b53_get_mib_size(dev);
0992     const struct b53_mib_desc *s;
0993     unsigned int i;
0994     u64 val = 0;
0995
0996     if (is5365(dev) && port == 5)
0997         port = 8;
0998
0999     mutex_lock(&dev->stats_mutex);
1000
1001     for (i = 0; i < mib_size; i++) {
1002         s = &mibs[i];
1003
1004         if (s->size == 8) {
1005             b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1006         } else {
1007             u32 val32;
1008
1009             b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1010                    &val32);
1011             val = val32;
1012         }
1013         data[i] = (u64)val;
1014     }
1015
1016     mutex_unlock(&dev->stats_mutex);
1017 }
1018 EXPORT_SYMBOL(b53_get_ethtool_stats);
1019
1020 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1021 {
1022     struct phy_device *phydev;
1023
1024     phydev = b53_get_phy_device(ds, port);
1025     if (!phydev)
1026         return;
1027
1028     phy_ethtool_get_stats(phydev, NULL, data);
1029 }
1030 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1031
1032 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1033 {
1034     struct b53_device *dev = ds->priv;
1035     struct phy_device *phydev;
1036
1037     if (sset == ETH_SS_STATS) {
1038         return b53_get_mib_size(dev);
1039     } else if (sset == ETH_SS_PHY_STATS) {
1040         phydev = b53_get_phy_device(ds, port);
1041         if (!phydev)
1042             return 0;
1043
1044         return phy_ethtool_get_sset_count(phydev);
1045     }
1046
1047     return 0;
1048 }
1049 EXPORT_SYMBOL(b53_get_sset_count);
1050
1051 enum b53_devlink_resource_id {
1052     B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1053 };
1054
1055 static u64 b53_devlink_vlan_table_get(void *priv)
1056 {
1057     struct b53_device *dev = priv;
1058     struct b53_vlan *vl;
1059     unsigned int i;
1060     u64 count = 0;
1061
1062     for (i = 0; i < dev->num_vlans; i++) {
1063         vl = &dev->vlans[i];
1064         if (vl->members)
1065             count++;
1066     }
1067
1068     return count;
1069 }
1070
1071 int b53_setup_devlink_resources(struct dsa_switch *ds)
1072 {
1073     struct devlink_resource_size_params size_params;
1074     struct b53_device *dev = ds->priv;
1075     int err;
1076
1077     devlink_resource_size_params_init(&size_params, dev->num_vlans,
1078                       dev->num_vlans,
1079                       1, DEVLINK_RESOURCE_UNIT_ENTRY);
1080
1081     err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1082                         B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1083                         DEVLINK_RESOURCE_ID_PARENT_TOP,
1084                         &size_params);
1085     if (err)
1086         goto out;
1087
1088     dsa_devlink_resource_occ_get_register(ds,
1089                           B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1090                           b53_devlink_vlan_table_get, dev);
1091
1092     return 0;
1093 out:
1094     dsa_devlink_resources_unregister(ds);
1095     return err;
1096 }
1097 EXPORT_SYMBOL(b53_setup_devlink_resources);
1098
1099 static int b53_setup(struct dsa_switch *ds)
1100 {
1101     struct b53_device *dev = ds->priv;
1102     unsigned int port;
1103     int ret;
1104
1105     /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1106      * which forces the CPU port to be tagged in all VLANs.
1107      */
1108     ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1109
1110     ret = b53_reset_switch(dev);
1111     if (ret) {
1112         dev_err(ds->dev, "failed to reset switch\n");
1113         return ret;
1114     }
1115
1116     b53_reset_mib(dev);
1117
1118     ret = b53_apply_config(dev);
1119     if (ret) {
1120         dev_err(ds->dev, "failed to apply configuration\n");
1121         return ret;
1122     }
1123
1124     /* Configure IMP/CPU port, disable all other ports. Enabled
1125      * ports will be configured with .port_enable
1126      */
1127     for (port = 0; port < dev->num_ports; port++) {
1128         if (dsa_is_cpu_port(ds, port))
1129             b53_enable_cpu_port(dev, port);
1130         else
1131             b53_disable_port(ds, port);
1132     }
1133
1134     return b53_setup_devlink_resources(ds);
1135 }
1136
1137 static void b53_teardown(struct dsa_switch *ds)
1138 {
1139     dsa_devlink_resources_unregister(ds);
1140 }
1141
1142 static void b53_force_link(struct b53_device *dev, int port, int link)
1143 {
1144     u8 reg, val, off;
1145
1146     /* Override the port settings */
1147     if (port == dev->imp_port) {
1148         off = B53_PORT_OVERRIDE_CTRL;
1149         val = PORT_OVERRIDE_EN;
1150     } else {
1151         off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1152         val = GMII_PO_EN;
1153     }
1154
1155     b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1156     reg |= val;
1157     if (link)
1158         reg |= PORT_OVERRIDE_LINK;
1159     else
1160         reg &= ~PORT_OVERRIDE_LINK;
1161     b53_write8(dev, B53_CTRL_PAGE, off, reg);
1162 }
1163
1164 static void b53_force_port_config(struct b53_device *dev, int port,
1165                   int speed, int duplex,
1166                   bool tx_pause, bool rx_pause)
1167 {
1168     u8 reg, val, off;
1169
1170     /* Override the port settings */
1171     if (port == dev->imp_port) {
1172         off = B53_PORT_OVERRIDE_CTRL;
1173         val = PORT_OVERRIDE_EN;
1174     } else {
1175         off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1176         val = GMII_PO_EN;
1177     }
1178
1179     b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1180     reg |= val;
1181     if (duplex == DUPLEX_FULL)
1182         reg |= PORT_OVERRIDE_FULL_DUPLEX;
1183     else
1184         reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1185
1186     switch (speed) {
1187     case 2000:
1188         reg |= PORT_OVERRIDE_SPEED_2000M;
1189         fallthrough;
1190     case SPEED_1000:
1191         reg |= PORT_OVERRIDE_SPEED_1000M;
1192         break;
1193     case SPEED_100:
1194         reg |= PORT_OVERRIDE_SPEED_100M;
1195         break;
1196     case SPEED_10:
1197         reg |= PORT_OVERRIDE_SPEED_10M;
1198         break;
1199     default:
1200         dev_err(dev->dev, "unknown speed: %d\n", speed);
1201         return;
1202     }
1203
1204     if (rx_pause)
1205         reg |= PORT_OVERRIDE_RX_FLOW;
1206     if (tx_pause)
1207         reg |= PORT_OVERRIDE_TX_FLOW;
1208
1209     b53_write8(dev, B53_CTRL_PAGE, off, reg);
1210 }
1211
1212 static void b53_adjust_link(struct dsa_switch *ds, int port,
1213                 struct phy_device *phydev)
1214 {
1215     struct b53_device *dev = ds->priv;
1216     struct ethtool_eee *p = &dev->ports[port].eee;
1217     u8 rgmii_ctrl = 0, reg = 0, off;
1218     bool tx_pause = false;
1219     bool rx_pause = false;
1220
1221     if (!phy_is_pseudo_fixed_link(phydev))
1222         return;
1223
1224     /* Enable flow control on BCM5301x's CPU port */
1225     if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1226         tx_pause = rx_pause = true;
1227
1228     if (phydev->pause) {
1229         if (phydev->asym_pause)
1230             tx_pause = true;
1231         rx_pause = true;
1232     }
1233
1234     b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1235                   tx_pause, rx_pause);
1236     b53_force_link(dev, port, phydev->link);
1237
1238     if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1239         if (port == dev->imp_port)
1240             off = B53_RGMII_CTRL_IMP;
1241         else
1242             off = B53_RGMII_CTRL_P(port);
1243
1244         /* Configure the port RGMII clock delay by DLL disabled and
1245          * tx_clk aligned timing (restoring to reset defaults)
1246          */
1247         b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1248         rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1249                 RGMII_CTRL_TIMING_SEL);
1250
1251         /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1252          * sure that we enable the port TX clock internal delay to
1253          * account for this internal delay that is inserted, otherwise
1254          * the switch won't be able to receive correctly.
1255          *
1256          * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1257          * any delay neither on transmission nor reception, so the
1258          * BCM53125 must also be configured accordingly to account for
1259          * the lack of delay and introduce
1260          *
1261          * The BCM53125 switch has its RX clock and TX clock control
1262          * swapped, hence the reason why we modify the TX clock path in
1263          * the "RGMII" case
1264          */
1265         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1266             rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1267         if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1268             rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1269         rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1270         b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1271
1272         dev_info(ds->dev, "Configured port %d for %s\n", port,
1273              phy_modes(phydev->interface));
1274     }
1275
1276     /* configure MII port if necessary */
1277     if (is5325(dev)) {
1278         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1279               &reg);
1280
1281         /* reverse mii needs to be enabled */
1282         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1283             b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1284                    reg | PORT_OVERRIDE_RV_MII_25);
1285             b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1286                   &reg);
1287
1288             if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1289                 dev_err(ds->dev,
1290                     "Failed to enable reverse MII mode\n");
1291                 return;
1292             }
1293         }
1294     }
1295
1296     /* Re-negotiate EEE if it was enabled already */
1297     p->eee_enabled = b53_eee_init(ds, port, phydev);
1298 }
1299
1300 void b53_port_event(struct dsa_switch *ds, int port)
1301 {
1302     struct b53_device *dev = ds->priv;
1303     bool link;
1304     u16 sts;
1305
1306     b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1307     link = !!(sts & BIT(port));
1308     dsa_port_phylink_mac_change(ds, port, link);
1309 }
1310 EXPORT_SYMBOL(b53_port_event);
1311
1312 static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1313                  struct phylink_config *config)
1314 {
1315     struct b53_device *dev = ds->priv;
1316
1317     /* Internal ports need GMII for PHYLIB */
1318     __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1319
1320     /* These switches appear to support MII and RevMII too, but beyond
1321      * this, the code gives very few clues. FIXME: We probably need more
1322      * interface modes here.
1323      *
1324      * According to b53_srab_mux_init(), ports 3..5 can support:
1325      *  SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1326      * However, the interface mode read from the MUX configuration is
1327      * not passed back to DSA, so phylink uses NA.
1328      * DT can specify RGMII for ports 0, 1.
1329      * For MDIO, port 8 can be RGMII_TXID.
1330      */
1331     __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1332     __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1333
1334     config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1335         MAC_10 | MAC_100;
1336
1337     /* 5325/5365 are not capable of gigabit speeds, everything else is.
1338      * Note: the original code also exclulded Gigagbit for MII, RevMII
1339      * and 802.3z modes. MII and RevMII are not able to work above 100M,
1340      * so will be excluded by the generic validator implementation.
1341      * However, the exclusion of Gigabit for 802.3z just seems wrong.
1342      */
1343     if (!(is5325(dev) || is5365(dev)))
1344         config->mac_capabilities |= MAC_1000;
1345
1346     /* Get the implementation specific capabilities */
1347     if (dev->ops->phylink_get_caps)
1348         dev->ops->phylink_get_caps(dev, port, config);
1349
1350     /* This driver does not make use of the speed, duplex, pause or the
1351      * advertisement in its mac_config, so it is safe to mark this driver
1352      * as non-legacy.
1353      */
1354     config->legacy_pre_march2020 = false;
1355 }
1356
1357 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1358                               int port,
1359                               phy_interface_t interface)
1360 {
1361     struct b53_device *dev = ds->priv;
1362
1363     if (!dev->ops->phylink_mac_select_pcs)
1364         return NULL;
1365
1366     return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1367 }
1368
1369 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1370                 unsigned int mode,
1371                 const struct phylink_link_state *state)
1372 {
1373 }
1374 EXPORT_SYMBOL(b53_phylink_mac_config);
1375
1376 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1377                    unsigned int mode,
1378                    phy_interface_t interface)
1379 {
1380     struct b53_device *dev = ds->priv;
1381
1382     if (mode == MLO_AN_PHY)
1383         return;
1384
1385     if (mode == MLO_AN_FIXED) {
1386         b53_force_link(dev, port, false);
1387         return;
1388     }
1389
1390     if (phy_interface_mode_is_8023z(interface) &&
1391         dev->ops->serdes_link_set)
1392         dev->ops->serdes_link_set(dev, port, mode, interface, false);
1393 }
1394 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1395
1396 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1397                  unsigned int mode,
1398                  phy_interface_t interface,
1399                  struct phy_device *phydev,
1400                  int speed, int duplex,
1401                  bool tx_pause, bool rx_pause)
1402 {
1403     struct b53_device *dev = ds->priv;
1404
1405     if (mode == MLO_AN_PHY)
1406         return;
1407
1408     if (mode == MLO_AN_FIXED) {
1409         b53_force_port_config(dev, port, speed, duplex,
1410                       tx_pause, rx_pause);
1411         b53_force_link(dev, port, true);
1412         return;
1413     }
1414
1415     if (phy_interface_mode_is_8023z(interface) &&
1416         dev->ops->serdes_link_set)
1417         dev->ops->serdes_link_set(dev, port, mode, interface, true);
1418 }
1419 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1420
1421 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1422                struct netlink_ext_ack *extack)
1423 {
1424     struct b53_device *dev = ds->priv;
1425
1426     b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1427
1428     return 0;
1429 }
1430 EXPORT_SYMBOL(b53_vlan_filtering);
1431
1432 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1433                 const struct switchdev_obj_port_vlan *vlan)
1434 {
1435     struct b53_device *dev = ds->priv;
1436
1437     if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1438         return -EOPNOTSUPP;
1439
1440     /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1441      * receiving VLAN tagged frames at all, we can still allow the port to
1442      * be configured for egress untagged.
1443      */
1444     if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1445         !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1446         return -EINVAL;
1447
1448     if (vlan->vid >= dev->num_vlans)
1449         return -ERANGE;
1450
1451     b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1452
1453     return 0;
1454 }
1455
1456 int b53_vlan_add(struct dsa_switch *ds, int port,
1457          const struct switchdev_obj_port_vlan *vlan,
1458          struct netlink_ext_ack *extack)
1459 {
1460     struct b53_device *dev = ds->priv;
1461     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1462     bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1463     struct b53_vlan *vl;
1464     int err;
1465
1466     err = b53_vlan_prepare(ds, port, vlan);
1467     if (err)
1468         return err;
1469
1470     vl = &dev->vlans[vlan->vid];
1471
1472     b53_get_vlan_entry(dev, vlan->vid, vl);
1473
1474     if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1475         untagged = true;
1476
1477     vl->members |= BIT(port);
1478     if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1479         vl->untag |= BIT(port);
1480     else
1481         vl->untag &= ~BIT(port);
1482
1483     b53_set_vlan_entry(dev, vlan->vid, vl);
1484     b53_fast_age_vlan(dev, vlan->vid);
1485
1486     if (pvid && !dsa_is_cpu_port(ds, port)) {
1487         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1488                 vlan->vid);
1489         b53_fast_age_vlan(dev, vlan->vid);
1490     }
1491
1492     return 0;
1493 }
1494 EXPORT_SYMBOL(b53_vlan_add);
1495
1496 int b53_vlan_del(struct dsa_switch *ds, int port,
1497          const struct switchdev_obj_port_vlan *vlan)
1498 {
1499     struct b53_device *dev = ds->priv;
1500     bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1501     struct b53_vlan *vl;
1502     u16 pvid;
1503
1504     b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1505
1506     vl = &dev->vlans[vlan->vid];
1507
1508     b53_get_vlan_entry(dev, vlan->vid, vl);
1509
1510     vl->members &= ~BIT(port);
1511
1512     if (pvid == vlan->vid)
1513         pvid = b53_default_pvid(dev);
1514
1515     if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1516         vl->untag &= ~(BIT(port));
1517
1518     b53_set_vlan_entry(dev, vlan->vid, vl);
1519     b53_fast_age_vlan(dev, vlan->vid);
1520
1521     b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1522     b53_fast_age_vlan(dev, pvid);
1523
1524     return 0;
1525 }
1526 EXPORT_SYMBOL(b53_vlan_del);
1527
1528 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
1529 static int b53_arl_op_wait(struct b53_device *dev)
1530 {
1531     unsigned int timeout = 10;
1532     u8 reg;
1533
1534     do {
1535         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1536         if (!(reg & ARLTBL_START_DONE))
1537             return 0;
1538
1539         usleep_range(1000, 2000);
1540     } while (timeout--);
1541
1542     dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1543
1544     return -ETIMEDOUT;
1545 }
1546
1547 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1548 {
1549     u8 reg;
1550
1551     if (op > ARLTBL_RW)
1552         return -EINVAL;
1553
1554     b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1555     reg |= ARLTBL_START_DONE;
1556     if (op)
1557         reg |= ARLTBL_RW;
1558     else
1559         reg &= ~ARLTBL_RW;
1560     if (dev->vlan_enabled)
1561         reg &= ~ARLTBL_IVL_SVL_SELECT;
1562     else
1563         reg |= ARLTBL_IVL_SVL_SELECT;
1564     b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1565
1566     return b53_arl_op_wait(dev);
1567 }
1568
1569 static int b53_arl_read(struct b53_device *dev, u64 mac,
1570             u16 vid, struct b53_arl_entry *ent, u8 *idx)
1571 {
1572     DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1573     unsigned int i;
1574     int ret;
1575
1576     ret = b53_arl_op_wait(dev);
1577     if (ret)
1578         return ret;
1579
1580     bitmap_zero(free_bins, dev->num_arl_bins);
1581
1582     /* Read the bins */
1583     for (i = 0; i < dev->num_arl_bins; i++) {
1584         u64 mac_vid;
1585         u32 fwd_entry;
1586
1587         b53_read64(dev, B53_ARLIO_PAGE,
1588                B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1589         b53_read32(dev, B53_ARLIO_PAGE,
1590                B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1591         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1592
1593         if (!(fwd_entry & ARLTBL_VALID)) {
1594             set_bit(i, free_bins);
1595             continue;
1596         }
1597         if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1598             continue;
1599         if (dev->vlan_enabled &&
1600             ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1601             continue;
1602         *idx = i;
1603         return 0;
1604     }
1605
1606     *idx = find_first_bit(free_bins, dev->num_arl_bins);
1607     return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1608 }
1609
1610 static int b53_arl_op(struct b53_device *dev, int op, int port,
1611               const unsigned char *addr, u16 vid, bool is_valid)
1612 {
1613     struct b53_arl_entry ent;
1614     u32 fwd_entry;
1615     u64 mac, mac_vid = 0;
1616     u8 idx = 0;
1617     int ret;
1618
1619     /* Convert the array into a 64-bit MAC */
1620     mac = ether_addr_to_u64(addr);
1621
1622     /* Perform a read for the given MAC and VID */
1623     b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1624     b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1625
1626     /* Issue a read operation for this MAC */
1627     ret = b53_arl_rw_op(dev, 1);
1628     if (ret)
1629         return ret;
1630
1631     ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1632
1633     /* If this is a read, just finish now */
1634     if (op)
1635         return ret;
1636
1637     switch (ret) {
1638     case -ETIMEDOUT:
1639         return ret;
1640     case -ENOSPC:
1641         dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1642             addr, vid);
1643         return is_valid ? ret : 0;
1644     case -ENOENT:
1645         /* We could not find a matching MAC, so reset to a new entry */
1646         dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1647             addr, vid, idx);
1648         fwd_entry = 0;
1649         break;
1650     default:
1651         dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1652             addr, vid, idx);
1653         break;
1654     }
1655
1656     /* For multicast address, the port is a bitmask and the validity
1657      * is determined by having at least one port being still active
1658      */
1659     if (!is_multicast_ether_addr(addr)) {
1660         ent.port = port;
1661         ent.is_valid = is_valid;
1662     } else {
1663         if (is_valid)
1664             ent.port |= BIT(port);
1665         else
1666             ent.port &= ~BIT(port);
1667
1668         ent.is_valid = !!(ent.port);
1669     }
1670
1671     ent.vid = vid;
1672     ent.is_static = true;
1673     ent.is_age = false;
1674     memcpy(ent.mac, addr, ETH_ALEN);
1675     b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1676
1677     b53_write64(dev, B53_ARLIO_PAGE,
1678             B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1679     b53_write32(dev, B53_ARLIO_PAGE,
1680             B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1681
1682     return b53_arl_rw_op(dev, 0);
1683 }
1684
1685 int b53_fdb_add(struct dsa_switch *ds, int port,
1686         const unsigned char *addr, u16 vid,
1687         struct dsa_db db)
1688 {
1689     struct b53_device *priv = ds->priv;
1690     int ret;
1691
1692     /* 5325 and 5365 require some more massaging, but could
1693      * be supported eventually
1694      */
1695     if (is5325(priv) || is5365(priv))
1696         return -EOPNOTSUPP;
1697
1698     mutex_lock(&priv->arl_mutex);
1699     ret = b53_arl_op(priv, 0, port, addr, vid, true);
1700     mutex_unlock(&priv->arl_mutex);
1701
1702     return ret;
1703 }
1704 EXPORT_SYMBOL(b53_fdb_add);
1705
1706 int b53_fdb_del(struct dsa_switch *ds, int port,
1707         const unsigned char *addr, u16 vid,
1708         struct dsa_db db)
1709 {
1710     struct b53_device *priv = ds->priv;
1711     int ret;
1712
1713     mutex_lock(&priv->arl_mutex);
1714     ret = b53_arl_op(priv, 0, port, addr, vid, false);
1715     mutex_unlock(&priv->arl_mutex);
1716
1717     return ret;
1718 }
1719 EXPORT_SYMBOL(b53_fdb_del);
1720
1721 static int b53_arl_search_wait(struct b53_device *dev)
1722 {
1723     unsigned int timeout = 1000;
1724     u8 reg;
1725
1726     do {
1727         b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1728         if (!(reg & ARL_SRCH_STDN))
1729             return 0;
1730
1731         if (reg & ARL_SRCH_VLID)
1732             return 0;
1733
1734         usleep_range(1000, 2000);
1735     } while (timeout--);
1736
1737     return -ETIMEDOUT;
1738 }
1739
1740 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1741                   struct b53_arl_entry *ent)
1742 {
1743     u64 mac_vid;
1744     u32 fwd_entry;
1745
1746     b53_read64(dev, B53_ARLIO_PAGE,
1747            B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1748     b53_read32(dev, B53_ARLIO_PAGE,
1749            B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1750     b53_arl_to_entry(ent, mac_vid, fwd_entry);
1751 }
1752
1753 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1754             dsa_fdb_dump_cb_t *cb, void *data)
1755 {
1756     if (!ent->is_valid)
1757         return 0;
1758
1759     if (port != ent->port)
1760         return 0;
1761
1762     return cb(ent->mac, ent->vid, ent->is_static, data);
1763 }
1764
1765 int b53_fdb_dump(struct dsa_switch *ds, int port,
1766          dsa_fdb_dump_cb_t *cb, void *data)
1767 {
1768     struct b53_device *priv = ds->priv;
1769     struct b53_arl_entry results[2];
1770     unsigned int count = 0;
1771     int ret;
1772     u8 reg;
1773
1774     mutex_lock(&priv->arl_mutex);
1775
1776     /* Start search operation */
1777     reg = ARL_SRCH_STDN;
1778     b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1779
1780     do {
1781         ret = b53_arl_search_wait(priv);
1782         if (ret)
1783             break;
1784
1785         b53_arl_search_rd(priv, 0, &results[0]);
1786         ret = b53_fdb_copy(port, &results[0], cb, data);
1787         if (ret)
1788             break;
1789
1790         if (priv->num_arl_bins > 2) {
1791             b53_arl_search_rd(priv, 1, &results[1]);
1792             ret = b53_fdb_copy(port, &results[1], cb, data);
1793             if (ret)
1794                 break;
1795
1796             if (!results[0].is_valid && !results[1].is_valid)
1797                 break;
1798         }
1799
1800     } while (count++ < b53_max_arl_entries(priv) / 2);
1801
1802     mutex_unlock(&priv->arl_mutex);
1803
1804     return 0;
1805 }
1806 EXPORT_SYMBOL(b53_fdb_dump);
1807
1808 int b53_mdb_add(struct dsa_switch *ds, int port,
1809         const struct switchdev_obj_port_mdb *mdb,
1810         struct dsa_db db)
1811 {
1812     struct b53_device *priv = ds->priv;
1813     int ret;
1814
1815     /* 5325 and 5365 require some more massaging, but could
1816      * be supported eventually
1817      */
1818     if (is5325(priv) || is5365(priv))
1819         return -EOPNOTSUPP;
1820
1821     mutex_lock(&priv->arl_mutex);
1822     ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1823     mutex_unlock(&priv->arl_mutex);
1824
1825     return ret;
1826 }
1827 EXPORT_SYMBOL(b53_mdb_add);
1828
1829 int b53_mdb_del(struct dsa_switch *ds, int port,
1830         const struct switchdev_obj_port_mdb *mdb,
1831         struct dsa_db db)
1832 {
1833     struct b53_device *priv = ds->priv;
1834     int ret;
1835
1836     mutex_lock(&priv->arl_mutex);
1837     ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1838     mutex_unlock(&priv->arl_mutex);
1839     if (ret)
1840         dev_err(ds->dev, "failed to delete MDB entry\n");
1841
1842     return ret;
1843 }
1844 EXPORT_SYMBOL(b53_mdb_del);
1845
1846 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1847         bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1848 {
1849     struct b53_device *dev = ds->priv;
1850     s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1851     u16 pvlan, reg;
1852     unsigned int i;
1853
1854     /* On 7278, port 7 which connects to the ASP should only receive
1855      * traffic from matching CFP rules.
1856      */
1857     if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1858         return -EINVAL;
1859
1860     /* Make this port leave the all VLANs join since we will have proper
1861      * VLAN entries from now on
1862      */
1863     if (is58xx(dev)) {
1864         b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1865         reg &= ~BIT(port);
1866         if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1867             reg &= ~BIT(cpu_port);
1868         b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1869     }
1870
1871     b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1872
1873     b53_for_each_port(dev, i) {
1874         if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1875             continue;
1876
1877         /* Add this local port to the remote port VLAN control
1878          * membership and update the remote port bitmask
1879          */
1880         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1881         reg |= BIT(port);
1882         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1883         dev->ports[i].vlan_ctl_mask = reg;
1884
1885         pvlan |= BIT(i);
1886     }
1887
1888     /* Configure the local port VLAN control membership to include
1889      * remote ports and update the local port bitmask
1890      */
1891     b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1892     dev->ports[port].vlan_ctl_mask = pvlan;
1893
1894     return 0;
1895 }
1896 EXPORT_SYMBOL(b53_br_join);
1897
1898 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1899 {
1900     struct b53_device *dev = ds->priv;
1901     struct b53_vlan *vl = &dev->vlans[0];
1902     s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1903     unsigned int i;
1904     u16 pvlan, reg, pvid;
1905
1906     b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1907
1908     b53_for_each_port(dev, i) {
1909         /* Don't touch the remaining ports */
1910         if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1911             continue;
1912
1913         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1914         reg &= ~BIT(port);
1915         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1916         dev->ports[port].vlan_ctl_mask = reg;
1917
1918         /* Prevent self removal to preserve isolation */
1919         if (port != i)
1920             pvlan &= ~BIT(i);
1921     }
1922
1923     b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1924     dev->ports[port].vlan_ctl_mask = pvlan;
1925
1926     pvid = b53_default_pvid(dev);
1927
1928     /* Make this port join all VLANs without VLAN entries */
1929     if (is58xx(dev)) {
1930         b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1931         reg |= BIT(port);
1932         if (!(reg & BIT(cpu_port)))
1933             reg |= BIT(cpu_port);
1934         b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1935     } else {
1936         b53_get_vlan_entry(dev, pvid, vl);
1937         vl->members |= BIT(port) | BIT(cpu_port);
1938         vl->untag |= BIT(port) | BIT(cpu_port);
1939         b53_set_vlan_entry(dev, pvid, vl);
1940     }
1941 }
1942 EXPORT_SYMBOL(b53_br_leave);
1943
1944 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1945 {
1946     struct b53_device *dev = ds->priv;
1947     u8 hw_state;
1948     u8 reg;
1949
1950     switch (state) {
1951     case BR_STATE_DISABLED:
1952         hw_state = PORT_CTRL_DIS_STATE;
1953         break;
1954     case BR_STATE_LISTENING:
1955         hw_state = PORT_CTRL_LISTEN_STATE;
1956         break;
1957     case BR_STATE_LEARNING:
1958         hw_state = PORT_CTRL_LEARN_STATE;
1959         break;
1960     case BR_STATE_FORWARDING:
1961         hw_state = PORT_CTRL_FWD_STATE;
1962         break;
1963     case BR_STATE_BLOCKING:
1964         hw_state = PORT_CTRL_BLOCK_STATE;
1965         break;
1966     default:
1967         dev_err(ds->dev, "invalid STP state: %d\n", state);
1968         return;
1969     }
1970
1971     b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1972     reg &= ~PORT_CTRL_STP_STATE_MASK;
1973     reg |= hw_state;
1974     b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1975 }
1976 EXPORT_SYMBOL(b53_br_set_stp_state);
1977
1978 void b53_br_fast_age(struct dsa_switch *ds, int port)
1979 {
1980     struct b53_device *dev = ds->priv;
1981
1982     if (b53_fast_age_port(dev, port))
1983         dev_err(ds->dev, "fast ageing failed\n");
1984 }
1985 EXPORT_SYMBOL(b53_br_fast_age);
1986
1987 int b53_br_flags_pre(struct dsa_switch *ds, int port,
1988              struct switchdev_brport_flags flags,
1989              struct netlink_ext_ack *extack)
1990 {
1991     if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
1992         return -EINVAL;
1993
1994     return 0;
1995 }
1996 EXPORT_SYMBOL(b53_br_flags_pre);
1997
1998 int b53_br_flags(struct dsa_switch *ds, int port,
1999          struct switchdev_brport_flags flags,
2000          struct netlink_ext_ack *extack)
2001 {
2002     if (flags.mask & BR_FLOOD)
2003         b53_port_set_ucast_flood(ds->priv, port,
2004                      !!(flags.val & BR_FLOOD));
2005     if (flags.mask & BR_MCAST_FLOOD)
2006         b53_port_set_mcast_flood(ds->priv, port,
2007                      !!(flags.val & BR_MCAST_FLOOD));
2008     if (flags.mask & BR_LEARNING)
2009         b53_port_set_learning(ds->priv, port,
2010                       !!(flags.val & BR_LEARNING));
2011
2012     return 0;
2013 }
2014 EXPORT_SYMBOL(b53_br_flags);
2015
2016 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2017 {
2018     /* Broadcom switches will accept enabling Broadcom tags on the
2019      * following ports: 5, 7 and 8, any other port is not supported
2020      */
2021     switch (port) {
2022     case B53_CPU_PORT_25:
2023     case 7:
2024     case B53_CPU_PORT:
2025         return true;
2026     }
2027
2028     return false;
2029 }
2030
2031 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2032                      enum dsa_tag_protocol tag_protocol)
2033 {
2034     bool ret = b53_possible_cpu_port(ds, port);
2035
2036     if (!ret) {
2037         dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2038              port);
2039         return ret;
2040     }
2041
2042     switch (tag_protocol) {
2043     case DSA_TAG_PROTO_BRCM:
2044     case DSA_TAG_PROTO_BRCM_PREPEND:
2045         dev_warn(ds->dev,
2046              "Port %d is stacked to Broadcom tag switch\n", port);
2047         ret = false;
2048         break;
2049     default:
2050         ret = true;
2051         break;
2052     }
2053
2054     return ret;
2055 }
2056
2057 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2058                        enum dsa_tag_protocol mprot)
2059 {
2060     struct b53_device *dev = ds->priv;
2061
2062     if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2063         dev->tag_protocol = DSA_TAG_PROTO_NONE;
2064         goto out;
2065     }
2066
2067     /* Older models require a different 6 byte tag */
2068     if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2069         dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2070         goto out;
2071     }
2072
2073     /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2074      * which requires us to use the prepended Broadcom tag type
2075      */
2076     if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2077         dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2078         goto out;
2079     }
2080
2081     dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2082 out:
2083     return dev->tag_protocol;
2084 }
2085 EXPORT_SYMBOL(b53_get_tag_protocol);
2086
2087 int b53_mirror_add(struct dsa_switch *ds, int port,
2088            struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2089            struct netlink_ext_ack *extack)
2090 {
2091     struct b53_device *dev = ds->priv;
2092     u16 reg, loc;
2093
2094     if (ingress)
2095         loc = B53_IG_MIR_CTL;
2096     else
2097         loc = B53_EG_MIR_CTL;
2098
2099     b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2100     reg |= BIT(port);
2101     b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2102
2103     b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2104     reg &= ~CAP_PORT_MASK;
2105     reg |= mirror->to_local_port;
2106     reg |= MIRROR_EN;
2107     b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2108
2109     return 0;
2110 }
2111 EXPORT_SYMBOL(b53_mirror_add);
2112
2113 void b53_mirror_del(struct dsa_switch *ds, int port,
2114             struct dsa_mall_mirror_tc_entry *mirror)
2115 {
2116     struct b53_device *dev = ds->priv;
2117     bool loc_disable = false, other_loc_disable = false;
2118     u16 reg, loc;
2119
2120     if (mirror->ingress)
2121         loc = B53_IG_MIR_CTL;
2122     else
2123         loc = B53_EG_MIR_CTL;
2124
2125     /* Update the desired ingress/egress register */
2126     b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2127     reg &= ~BIT(port);
2128     if (!(reg & MIRROR_MASK))
2129         loc_disable = true;
2130     b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2131
2132     /* Now look at the other one to know if we can disable mirroring
2133      * entirely
2134      */
2135     if (mirror->ingress)
2136         b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2137     else
2138         b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2139     if (!(reg & MIRROR_MASK))
2140         other_loc_disable = true;
2141
2142     b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2143     /* Both no longer have ports, let's disable mirroring */
2144     if (loc_disable && other_loc_disable) {
2145         reg &= ~MIRROR_EN;
2146         reg &= ~mirror->to_local_port;
2147     }
2148     b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2149 }
2150 EXPORT_SYMBOL(b53_mirror_del);
2151
2152 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2153 {
2154     struct b53_device *dev = ds->priv;
2155     u16 reg;
2156
2157     b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
2158     if (enable)
2159         reg |= BIT(port);
2160     else
2161         reg &= ~BIT(port);
2162     b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2163 }
2164 EXPORT_SYMBOL(b53_eee_enable_set);
2165
2166
2167 /* Returns 0 if EEE was not enabled, or 1 otherwise
2168  */
2169 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2170 {
2171     int ret;
2172
2173     ret = phy_init_eee(phy, false);
2174     if (ret)
2175         return 0;
2176
2177     b53_eee_enable_set(ds, port, true);
2178
2179     return 1;
2180 }
2181 EXPORT_SYMBOL(b53_eee_init);
2182
2183 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2184 {
2185     struct b53_device *dev = ds->priv;
2186     struct ethtool_eee *p = &dev->ports[port].eee;
2187     u16 reg;
2188
2189     if (is5325(dev) || is5365(dev))
2190         return -EOPNOTSUPP;
2191
2192     b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
2193     e->eee_enabled = p->eee_enabled;
2194     e->eee_active = !!(reg & BIT(port));
2195
2196     return 0;
2197 }
2198 EXPORT_SYMBOL(b53_get_mac_eee);
2199
2200 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2201 {
2202     struct b53_device *dev = ds->priv;
2203     struct ethtool_eee *p = &dev->ports[port].eee;
2204
2205     if (is5325(dev) || is5365(dev))
2206         return -EOPNOTSUPP;
2207
2208     p->eee_enabled = e->eee_enabled;
2209     b53_eee_enable_set(ds, port, e->eee_enabled);
2210
2211     return 0;
2212 }
2213 EXPORT_SYMBOL(b53_set_mac_eee);
2214
2215 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2216 {
2217     struct b53_device *dev = ds->priv;
2218     bool enable_jumbo;
2219     bool allow_10_100;
2220
2221     if (is5325(dev) || is5365(dev))
2222         return -EOPNOTSUPP;
2223
2224     enable_jumbo = (mtu >= JMS_MIN_SIZE);
2225     allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2226
2227     return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2228 }
2229
2230 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2231 {
2232     return JMS_MAX_SIZE;
2233 }
2234
2235 static const struct dsa_switch_ops b53_switch_ops = {
2236     .get_tag_protocol   = b53_get_tag_protocol,
2237     .setup          = b53_setup,
2238     .teardown       = b53_teardown,
2239     .get_strings        = b53_get_strings,
2240     .get_ethtool_stats  = b53_get_ethtool_stats,
2241     .get_sset_count     = b53_get_sset_count,
2242     .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
2243     .phy_read       = b53_phy_read16,
2244     .phy_write      = b53_phy_write16,
2245     .adjust_link        = b53_adjust_link,
2246     .phylink_get_caps   = b53_phylink_get_caps,
2247     .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2248     .phylink_mac_config = b53_phylink_mac_config,
2249     .phylink_mac_link_down  = b53_phylink_mac_link_down,
2250     .phylink_mac_link_up    = b53_phylink_mac_link_up,
2251     .port_enable        = b53_enable_port,
2252     .port_disable       = b53_disable_port,
2253     .get_mac_eee        = b53_get_mac_eee,
2254     .set_mac_eee        = b53_set_mac_eee,
2255     .port_bridge_join   = b53_br_join,
2256     .port_bridge_leave  = b53_br_leave,
2257     .port_pre_bridge_flags  = b53_br_flags_pre,
2258     .port_bridge_flags  = b53_br_flags,
2259     .port_stp_state_set = b53_br_set_stp_state,
2260     .port_fast_age      = b53_br_fast_age,
2261     .port_vlan_filtering    = b53_vlan_filtering,
2262     .port_vlan_add      = b53_vlan_add,
2263     .port_vlan_del      = b53_vlan_del,
2264     .port_fdb_dump      = b53_fdb_dump,
2265     .port_fdb_add       = b53_fdb_add,
2266     .port_fdb_del       = b53_fdb_del,
2267     .port_mirror_add    = b53_mirror_add,
2268     .port_mirror_del    = b53_mirror_del,
2269     .port_mdb_add       = b53_mdb_add,
2270     .port_mdb_del       = b53_mdb_del,
2271     .port_max_mtu       = b53_get_max_mtu,
2272     .port_change_mtu    = b53_change_mtu,
2273 };
2274
2275 struct b53_chip_data {
2276     u32 chip_id;
2277     const char *dev_name;
2278     u16 vlans;
2279     u16 enabled_ports;
2280     u8 imp_port;
2281     u8 cpu_port;
2282     u8 vta_regs[3];
2283     u8 arl_bins;
2284     u16 arl_buckets;
2285     u8 duplex_reg;
2286     u8 jumbo_pm_reg;
2287     u8 jumbo_size_reg;
2288 };
2289
2290 #define B53_VTA_REGS    \
2291     { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2292 #define B53_VTA_REGS_9798 \
2293     { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2294 #define B53_VTA_REGS_63XX \
2295     { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2296
2297 static const struct b53_chip_data b53_switch_chips[] = {
2298     {
2299         .chip_id = BCM5325_DEVICE_ID,
2300         .dev_name = "BCM5325",
2301         .vlans = 16,
2302         .enabled_ports = 0x3f,
2303         .arl_bins = 2,
2304         .arl_buckets = 1024,
2305         .imp_port = 5,
2306         .duplex_reg = B53_DUPLEX_STAT_FE,
2307     },
2308     {
2309         .chip_id = BCM5365_DEVICE_ID,
2310         .dev_name = "BCM5365",
2311         .vlans = 256,
2312         .enabled_ports = 0x3f,
2313         .arl_bins = 2,
2314         .arl_buckets = 1024,
2315         .imp_port = 5,
2316         .duplex_reg = B53_DUPLEX_STAT_FE,
2317     },
2318     {
2319         .chip_id = BCM5389_DEVICE_ID,
2320         .dev_name = "BCM5389",
2321         .vlans = 4096,
2322         .enabled_ports = 0x11f,
2323         .arl_bins = 4,
2324         .arl_buckets = 1024,
2325         .imp_port = 8,
2326         .vta_regs = B53_VTA_REGS,
2327         .duplex_reg = B53_DUPLEX_STAT_GE,
2328         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2329         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2330     },
2331     {
2332         .chip_id = BCM5395_DEVICE_ID,
2333         .dev_name = "BCM5395",
2334         .vlans = 4096,
2335         .enabled_ports = 0x11f,
2336         .arl_bins = 4,
2337         .arl_buckets = 1024,
2338         .imp_port = 8,
2339         .vta_regs = B53_VTA_REGS,
2340         .duplex_reg = B53_DUPLEX_STAT_GE,
2341         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2342         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2343     },
2344     {
2345         .chip_id = BCM5397_DEVICE_ID,
2346         .dev_name = "BCM5397",
2347         .vlans = 4096,
2348         .enabled_ports = 0x11f,
2349         .arl_bins = 4,
2350         .arl_buckets = 1024,
2351         .imp_port = 8,
2352         .vta_regs = B53_VTA_REGS_9798,
2353         .duplex_reg = B53_DUPLEX_STAT_GE,
2354         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2355         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2356     },
2357     {
2358         .chip_id = BCM5398_DEVICE_ID,
2359         .dev_name = "BCM5398",
2360         .vlans = 4096,
2361         .enabled_ports = 0x17f,
2362         .arl_bins = 4,
2363         .arl_buckets = 1024,
2364         .imp_port = 8,
2365         .vta_regs = B53_VTA_REGS_9798,
2366         .duplex_reg = B53_DUPLEX_STAT_GE,
2367         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2368         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2369     },
2370     {
2371         .chip_id = BCM53115_DEVICE_ID,
2372         .dev_name = "BCM53115",
2373         .vlans = 4096,
2374         .enabled_ports = 0x11f,
2375         .arl_bins = 4,
2376         .arl_buckets = 1024,
2377         .vta_regs = B53_VTA_REGS,
2378         .imp_port = 8,
2379         .duplex_reg = B53_DUPLEX_STAT_GE,
2380         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2381         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2382     },
2383     {
2384         .chip_id = BCM53125_DEVICE_ID,
2385         .dev_name = "BCM53125",
2386         .vlans = 4096,
2387         .enabled_ports = 0x1ff,
2388         .arl_bins = 4,
2389         .arl_buckets = 1024,
2390         .imp_port = 8,
2391         .vta_regs = B53_VTA_REGS,
2392         .duplex_reg = B53_DUPLEX_STAT_GE,
2393         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2394         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2395     },
2396     {
2397         .chip_id = BCM53128_DEVICE_ID,
2398         .dev_name = "BCM53128",
2399         .vlans = 4096,
2400         .enabled_ports = 0x1ff,
2401         .arl_bins = 4,
2402         .arl_buckets = 1024,
2403         .imp_port = 8,
2404         .vta_regs = B53_VTA_REGS,
2405         .duplex_reg = B53_DUPLEX_STAT_GE,
2406         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2407         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2408     },
2409     {
2410         .chip_id = BCM63XX_DEVICE_ID,
2411         .dev_name = "BCM63xx",
2412         .vlans = 4096,
2413         .enabled_ports = 0, /* pdata must provide them */
2414         .arl_bins = 4,
2415         .arl_buckets = 1024,
2416         .imp_port = 8,
2417         .vta_regs = B53_VTA_REGS_63XX,
2418         .duplex_reg = B53_DUPLEX_STAT_63XX,
2419         .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2420         .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2421     },
2422     {
2423         .chip_id = BCM53010_DEVICE_ID,
2424         .dev_name = "BCM53010",
2425         .vlans = 4096,
2426         .enabled_ports = 0x1bf,
2427         .arl_bins = 4,
2428         .arl_buckets = 1024,
2429         .imp_port = 8,
2430         .vta_regs = B53_VTA_REGS,
2431         .duplex_reg = B53_DUPLEX_STAT_GE,
2432         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2433         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2434     },
2435     {
2436         .chip_id = BCM53011_DEVICE_ID,
2437         .dev_name = "BCM53011",
2438         .vlans = 4096,
2439         .enabled_ports = 0x1bf,
2440         .arl_bins = 4,
2441         .arl_buckets = 1024,
2442         .imp_port = 8,
2443         .vta_regs = B53_VTA_REGS,
2444         .duplex_reg = B53_DUPLEX_STAT_GE,
2445         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2446         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2447     },
2448     {
2449         .chip_id = BCM53012_DEVICE_ID,
2450         .dev_name = "BCM53012",
2451         .vlans = 4096,
2452         .enabled_ports = 0x1bf,
2453         .arl_bins = 4,
2454         .arl_buckets = 1024,
2455         .imp_port = 8,
2456         .vta_regs = B53_VTA_REGS,
2457         .duplex_reg = B53_DUPLEX_STAT_GE,
2458         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2459         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2460     },
2461     {
2462         .chip_id = BCM53018_DEVICE_ID,
2463         .dev_name = "BCM53018",
2464         .vlans = 4096,
2465         .enabled_ports = 0x1bf,
2466         .arl_bins = 4,
2467         .arl_buckets = 1024,
2468         .imp_port = 8,
2469         .vta_regs = B53_VTA_REGS,
2470         .duplex_reg = B53_DUPLEX_STAT_GE,
2471         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2472         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2473     },
2474     {
2475         .chip_id = BCM53019_DEVICE_ID,
2476         .dev_name = "BCM53019",
2477         .vlans = 4096,
2478         .enabled_ports = 0x1bf,
2479         .arl_bins = 4,
2480         .arl_buckets = 1024,
2481         .imp_port = 8,
2482         .vta_regs = B53_VTA_REGS,
2483         .duplex_reg = B53_DUPLEX_STAT_GE,
2484         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2485         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2486     },
2487     {
2488         .chip_id = BCM58XX_DEVICE_ID,
2489         .dev_name = "BCM585xx/586xx/88312",
2490         .vlans  = 4096,
2491         .enabled_ports = 0x1ff,
2492         .arl_bins = 4,
2493         .arl_buckets = 1024,
2494         .imp_port = 8,
2495         .vta_regs = B53_VTA_REGS,
2496         .duplex_reg = B53_DUPLEX_STAT_GE,
2497         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2498         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2499     },
2500     {
2501         .chip_id = BCM583XX_DEVICE_ID,
2502         .dev_name = "BCM583xx/11360",
2503         .vlans = 4096,
2504         .enabled_ports = 0x103,
2505         .arl_bins = 4,
2506         .arl_buckets = 1024,
2507         .imp_port = 8,
2508         .vta_regs = B53_VTA_REGS,
2509         .duplex_reg = B53_DUPLEX_STAT_GE,
2510         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2511         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2512     },
2513     /* Starfighter 2 */
2514     {
2515         .chip_id = BCM4908_DEVICE_ID,
2516         .dev_name = "BCM4908",
2517         .vlans = 4096,
2518         .enabled_ports = 0x1bf,
2519         .arl_bins = 4,
2520         .arl_buckets = 256,
2521         .imp_port = 8,
2522         .vta_regs = B53_VTA_REGS,
2523         .duplex_reg = B53_DUPLEX_STAT_GE,
2524         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2525         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2526     },
2527     {
2528         .chip_id = BCM7445_DEVICE_ID,
2529         .dev_name = "BCM7445",
2530         .vlans  = 4096,
2531         .enabled_ports = 0x1ff,
2532         .arl_bins = 4,
2533         .arl_buckets = 1024,
2534         .imp_port = 8,
2535         .vta_regs = B53_VTA_REGS,
2536         .duplex_reg = B53_DUPLEX_STAT_GE,
2537         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2538         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2539     },
2540     {
2541         .chip_id = BCM7278_DEVICE_ID,
2542         .dev_name = "BCM7278",
2543         .vlans = 4096,
2544         .enabled_ports = 0x1ff,
2545         .arl_bins = 4,
2546         .arl_buckets = 256,
2547         .imp_port = 8,
2548         .vta_regs = B53_VTA_REGS,
2549         .duplex_reg = B53_DUPLEX_STAT_GE,
2550         .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2551         .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2552     },
2553 };
2554
2555 static int b53_switch_init(struct b53_device *dev)
2556 {
2557     unsigned int i;
2558     int ret;
2559
2560     for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2561         const struct b53_chip_data *chip = &b53_switch_chips[i];
2562
2563         if (chip->chip_id == dev->chip_id) {
2564             if (!dev->enabled_ports)
2565                 dev->enabled_ports = chip->enabled_ports;
2566             dev->name = chip->dev_name;
2567             dev->duplex_reg = chip->duplex_reg;
2568             dev->vta_regs[0] = chip->vta_regs[0];
2569             dev->vta_regs[1] = chip->vta_regs[1];
2570             dev->vta_regs[2] = chip->vta_regs[2];
2571             dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2572             dev->imp_port = chip->imp_port;
2573             dev->num_vlans = chip->vlans;
2574             dev->num_arl_bins = chip->arl_bins;
2575             dev->num_arl_buckets = chip->arl_buckets;
2576             break;
2577         }
2578     }
2579
2580     /* check which BCM5325x version we have */
2581     if (is5325(dev)) {
2582         u8 vc4;
2583
2584         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2585
2586         /* check reserved bits */
2587         switch (vc4 & 3) {
2588         case 1:
2589             /* BCM5325E */
2590             break;
2591         case 3:
2592             /* BCM5325F - do not use port 4 */
2593             dev->enabled_ports &= ~BIT(4);
2594             break;
2595         default:
2596 /* On the BCM47XX SoCs this is the supported internal switch.*/
2597 #ifndef CONFIG_BCM47XX
2598             /* BCM5325M */
2599             return -EINVAL;
2600 #else
2601             break;
2602 #endif
2603         }
2604     }
2605
2606     dev->num_ports = fls(dev->enabled_ports);
2607
2608     dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2609
2610     /* Include non standard CPU port built-in PHYs to be probed */
2611     if (is539x(dev) || is531x5(dev)) {
2612         for (i = 0; i < dev->num_ports; i++) {
2613             if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2614                 !b53_possible_cpu_port(dev->ds, i))
2615                 dev->ds->phys_mii_mask |= BIT(i);
2616         }
2617     }
2618
2619     dev->ports = devm_kcalloc(dev->dev,
2620                   dev->num_ports, sizeof(struct b53_port),
2621                   GFP_KERNEL);
2622     if (!dev->ports)
2623         return -ENOMEM;
2624
2625     dev->vlans = devm_kcalloc(dev->dev,
2626                   dev->num_vlans, sizeof(struct b53_vlan),
2627                   GFP_KERNEL);
2628     if (!dev->vlans)
2629         return -ENOMEM;
2630
2631     dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2632     if (dev->reset_gpio >= 0) {
2633         ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2634                         GPIOF_OUT_INIT_HIGH, "robo_reset");
2635         if (ret)
2636             return ret;
2637     }
2638
2639     return 0;
2640 }
2641
2642 struct b53_device *b53_switch_alloc(struct device *base,
2643                     const struct b53_io_ops *ops,
2644                     void *priv)
2645 {
2646     struct dsa_switch *ds;
2647     struct b53_device *dev;
2648
2649     ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2650     if (!ds)
2651         return NULL;
2652
2653     ds->dev = base;
2654
2655     dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2656     if (!dev)
2657         return NULL;
2658
2659     ds->priv = dev;
2660     dev->dev = base;
2661
2662     dev->ds = ds;
2663     dev->priv = priv;
2664     dev->ops = ops;
2665     ds->ops = &b53_switch_ops;
2666     dev->vlan_enabled = true;
2667     /* Let DSA handle the case were multiple bridges span the same switch
2668      * device and different VLAN awareness settings are requested, which
2669      * would be breaking filtering semantics for any of the other bridge
2670      * devices. (not hardware supported)
2671      */
2672     ds->vlan_filtering_is_global = true;
2673
2674     mutex_init(&dev->reg_mutex);
2675     mutex_init(&dev->stats_mutex);
2676     mutex_init(&dev->arl_mutex);
2677
2678     return dev;
2679 }
2680 EXPORT_SYMBOL(b53_switch_alloc);
2681
2682 int b53_switch_detect(struct b53_device *dev)
2683 {
2684     u32 id32;
2685     u16 tmp;
2686     u8 id8;
2687     int ret;
2688
2689     ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2690     if (ret)
2691         return ret;
2692
2693     switch (id8) {
2694     case 0:
2695         /* BCM5325 and BCM5365 do not have this register so reads
2696          * return 0. But the read operation did succeed, so assume this
2697          * is one of them.
2698          *
2699          * Next check if we can write to the 5325's VTA register; for
2700          * 5365 it is read only.
2701          */
2702         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2703         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2704
2705         if (tmp == 0xf)
2706             dev->chip_id = BCM5325_DEVICE_ID;
2707         else
2708             dev->chip_id = BCM5365_DEVICE_ID;
2709         break;
2710     case BCM5389_DEVICE_ID:
2711     case BCM5395_DEVICE_ID:
2712     case BCM5397_DEVICE_ID:
2713     case BCM5398_DEVICE_ID:
2714         dev->chip_id = id8;
2715         break;
2716     default:
2717         ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2718         if (ret)
2719             return ret;
2720
2721         switch (id32) {
2722         case BCM53115_DEVICE_ID:
2723         case BCM53125_DEVICE_ID:
2724         case BCM53128_DEVICE_ID:
2725         case BCM53010_DEVICE_ID:
2726         case BCM53011_DEVICE_ID:
2727         case BCM53012_DEVICE_ID:
2728         case BCM53018_DEVICE_ID:
2729         case BCM53019_DEVICE_ID:
2730             dev->chip_id = id32;
2731             break;
2732         default:
2733             dev_err(dev->dev,
2734                 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2735                 id8, id32);
2736             return -ENODEV;
2737         }
2738     }
2739
2740     if (dev->chip_id == BCM5325_DEVICE_ID)
2741         return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2742                  &dev->core_rev);
2743     else
2744         return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2745                  &dev->core_rev);
2746 }
2747 EXPORT_SYMBOL(b53_switch_detect);
2748
2749 int b53_switch_register(struct b53_device *dev)
2750 {
2751     int ret;
2752
2753     if (dev->pdata) {
2754         dev->chip_id = dev->pdata->chip_id;
2755         dev->enabled_ports = dev->pdata->enabled_ports;
2756     }
2757
2758     if (!dev->chip_id && b53_switch_detect(dev))
2759         return -EINVAL;
2760
2761     ret = b53_switch_init(dev);
2762     if (ret)
2763         return ret;
2764
2765     dev_info(dev->dev, "found switch: %s, rev %i\n",
2766          dev->name, dev->core_rev);
2767
2768     return dsa_register_switch(dev->ds);
2769 }
2770 EXPORT_SYMBOL(b53_switch_register);
2771
2772 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2773 MODULE_DESCRIPTION("B53 switch library");
2774 MODULE_LICENSE("Dual BSD/GPL");