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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI HECC (CAN) device driver
0004  *
0005  * This driver supports TI's HECC (High End CAN Controller module) and the
0006  * specs for the same is available at <http://www.ti.com>
0007  *
0008  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
0009  * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/types.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/errno.h>
0017 #include <linux/ethtool.h>
0018 #include <linux/netdevice.h>
0019 #include <linux/skbuff.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/clk.h>
0022 #include <linux/io.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/regulator/consumer.h>
0026 
0027 #include <linux/can/dev.h>
0028 #include <linux/can/error.h>
0029 #include <linux/can/rx-offload.h>
0030 
0031 #define DRV_NAME "ti_hecc"
0032 #define HECC_MODULE_VERSION     "0.7"
0033 MODULE_VERSION(HECC_MODULE_VERSION);
0034 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
0035 
0036 /* TX / RX Mailbox Configuration */
0037 #define HECC_MAX_MAILBOXES  32  /* hardware mailboxes - do not change */
0038 #define MAX_TX_PRIO     0x3F    /* hardware value - do not change */
0039 
0040 /* Important Note: TX mailbox configuration
0041  * TX mailboxes should be restricted to the number of SKB buffers to avoid
0042  * maintaining SKB buffers separately. TX mailboxes should be a power of 2
0043  * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
0044  * and lower mailboxes for TX.
0045  *
0046  * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
0047  * 4 (default)      2
0048  * 8            3
0049  * 16           4
0050  */
0051 #define HECC_MB_TX_SHIFT    2 /* as per table above */
0052 #define HECC_MAX_TX_MBOX    BIT(HECC_MB_TX_SHIFT)
0053 
0054 #define HECC_TX_PRIO_SHIFT  (HECC_MB_TX_SHIFT)
0055 #define HECC_TX_PRIO_MASK   (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
0056 #define HECC_TX_MB_MASK     (HECC_MAX_TX_MBOX - 1)
0057 #define HECC_TX_MASK        ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
0058 
0059 /* RX mailbox configuration
0060  *
0061  * The remaining mailboxes are used for reception and are delivered
0062  * based on their timestamp, to avoid a hardware race when CANME is
0063  * changed while CAN-bus traffic is being received.
0064  */
0065 #define HECC_MAX_RX_MBOX    (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
0066 #define HECC_RX_FIRST_MBOX  (HECC_MAX_MAILBOXES - 1)
0067 #define HECC_RX_LAST_MBOX   (HECC_MAX_TX_MBOX)
0068 
0069 /* TI HECC module registers */
0070 #define HECC_CANME      0x0 /* Mailbox enable */
0071 #define HECC_CANMD      0x4 /* Mailbox direction */
0072 #define HECC_CANTRS     0x8 /* Transmit request set */
0073 #define HECC_CANTRR     0xC /* Transmit request */
0074 #define HECC_CANTA      0x10    /* Transmission acknowledge */
0075 #define HECC_CANAA      0x14    /* Abort acknowledge */
0076 #define HECC_CANRMP     0x18    /* Receive message pending */
0077 #define HECC_CANRML     0x1C    /* Receive message lost */
0078 #define HECC_CANRFP     0x20    /* Remote frame pending */
0079 #define HECC_CANGAM     0x24    /* SECC only:Global acceptance mask */
0080 #define HECC_CANMC      0x28    /* Master control */
0081 #define HECC_CANBTC     0x2C    /* Bit timing configuration */
0082 #define HECC_CANES      0x30    /* Error and status */
0083 #define HECC_CANTEC     0x34    /* Transmit error counter */
0084 #define HECC_CANREC     0x38    /* Receive error counter */
0085 #define HECC_CANGIF0        0x3C    /* Global interrupt flag 0 */
0086 #define HECC_CANGIM     0x40    /* Global interrupt mask */
0087 #define HECC_CANGIF1        0x44    /* Global interrupt flag 1 */
0088 #define HECC_CANMIM     0x48    /* Mailbox interrupt mask */
0089 #define HECC_CANMIL     0x4C    /* Mailbox interrupt level */
0090 #define HECC_CANOPC     0x50    /* Overwrite protection control */
0091 #define HECC_CANTIOC        0x54    /* Transmit I/O control */
0092 #define HECC_CANRIOC        0x58    /* Receive I/O control */
0093 #define HECC_CANLNT     0x5C    /* HECC only: Local network time */
0094 #define HECC_CANTOC     0x60    /* HECC only: Time-out control */
0095 #define HECC_CANTOS     0x64    /* HECC only: Time-out status */
0096 #define HECC_CANTIOCE       0x68    /* SCC only:Enhanced TX I/O control */
0097 #define HECC_CANRIOCE       0x6C    /* SCC only:Enhanced RX I/O control */
0098 
0099 /* TI HECC RAM registers */
0100 #define HECC_CANMOTS        0x80    /* Message object time stamp */
0101 
0102 /* Mailbox registers */
0103 #define HECC_CANMID     0x0
0104 #define HECC_CANMCF     0x4
0105 #define HECC_CANMDL     0x8
0106 #define HECC_CANMDH     0xC
0107 
0108 #define HECC_SET_REG        0xFFFFFFFF
0109 #define HECC_CANID_MASK     0x3FF   /* 18 bits mask for extended id's */
0110 #define HECC_CCE_WAIT_COUNT     100 /* Wait for ~1 sec for CCE bit */
0111 
0112 #define HECC_CANMC_SCM      BIT(13) /* SCC compat mode */
0113 #define HECC_CANMC_CCR      BIT(12) /* Change config request */
0114 #define HECC_CANMC_PDR      BIT(11) /* Local Power down - for sleep mode */
0115 #define HECC_CANMC_ABO      BIT(7)  /* Auto Bus On */
0116 #define HECC_CANMC_STM      BIT(6)  /* Self test mode - loopback */
0117 #define HECC_CANMC_SRES     BIT(5)  /* Software reset */
0118 
0119 #define HECC_CANTIOC_EN     BIT(3)  /* Enable CAN TX I/O pin */
0120 #define HECC_CANRIOC_EN     BIT(3)  /* Enable CAN RX I/O pin */
0121 
0122 #define HECC_CANMID_IDE     BIT(31) /* Extended frame format */
0123 #define HECC_CANMID_AME     BIT(30) /* Acceptance mask enable */
0124 #define HECC_CANMID_AAM     BIT(29) /* Auto answer mode */
0125 
0126 #define HECC_CANES_FE       BIT(24) /* form error */
0127 #define HECC_CANES_BE       BIT(23) /* bit error */
0128 #define HECC_CANES_SA1      BIT(22) /* stuck at dominant error */
0129 #define HECC_CANES_CRCE     BIT(21) /* CRC error */
0130 #define HECC_CANES_SE       BIT(20) /* stuff bit error */
0131 #define HECC_CANES_ACKE     BIT(19) /* ack error */
0132 #define HECC_CANES_BO       BIT(18) /* Bus off status */
0133 #define HECC_CANES_EP       BIT(17) /* Error passive status */
0134 #define HECC_CANES_EW       BIT(16) /* Error warning status */
0135 #define HECC_CANES_SMA      BIT(5)  /* suspend mode ack */
0136 #define HECC_CANES_CCE      BIT(4)  /* Change config enabled */
0137 #define HECC_CANES_PDA      BIT(3)  /* Power down mode ack */
0138 
0139 #define HECC_CANBTC_SAM     BIT(7)  /* sample points */
0140 
0141 #define HECC_BUS_ERROR      (HECC_CANES_FE | HECC_CANES_BE |\
0142                 HECC_CANES_CRCE | HECC_CANES_SE |\
0143                 HECC_CANES_ACKE)
0144 #define HECC_CANES_FLAGS    (HECC_BUS_ERROR | HECC_CANES_BO |\
0145                 HECC_CANES_EP | HECC_CANES_EW)
0146 
0147 #define HECC_CANMCF_RTR     BIT(4)  /* Remote transmit request */
0148 
0149 #define HECC_CANGIF_MAIF    BIT(17) /* Message alarm interrupt */
0150 #define HECC_CANGIF_TCOIF   BIT(16) /* Timer counter overflow int */
0151 #define HECC_CANGIF_GMIF    BIT(15) /* Global mailbox interrupt */
0152 #define HECC_CANGIF_AAIF    BIT(14) /* Abort ack interrupt */
0153 #define HECC_CANGIF_WDIF    BIT(13) /* Write denied interrupt */
0154 #define HECC_CANGIF_WUIF    BIT(12) /* Wake up interrupt */
0155 #define HECC_CANGIF_RMLIF   BIT(11) /* Receive message lost interrupt */
0156 #define HECC_CANGIF_BOIF    BIT(10) /* Bus off interrupt */
0157 #define HECC_CANGIF_EPIF    BIT(9)  /* Error passive interrupt */
0158 #define HECC_CANGIF_WLIF    BIT(8)  /* Warning level interrupt */
0159 #define HECC_CANGIF_MBOX_MASK   0x1F    /* Mailbox number mask */
0160 #define HECC_CANGIM_I1EN    BIT(1)  /* Int line 1 enable */
0161 #define HECC_CANGIM_I0EN    BIT(0)  /* Int line 0 enable */
0162 #define HECC_CANGIM_DEF_MASK    0x700   /* only busoff/warning/passive */
0163 #define HECC_CANGIM_SIL     BIT(2)  /* system interrupts to int line 1 */
0164 
0165 /* CAN Bittiming constants as per HECC specs */
0166 static const struct can_bittiming_const ti_hecc_bittiming_const = {
0167     .name = DRV_NAME,
0168     .tseg1_min = 1,
0169     .tseg1_max = 16,
0170     .tseg2_min = 1,
0171     .tseg2_max = 8,
0172     .sjw_max = 4,
0173     .brp_min = 1,
0174     .brp_max = 256,
0175     .brp_inc = 1,
0176 };
0177 
0178 struct ti_hecc_priv {
0179     struct can_priv can;    /* MUST be first member/field */
0180     struct can_rx_offload offload;
0181     struct net_device *ndev;
0182     struct clk *clk;
0183     void __iomem *base;
0184     void __iomem *hecc_ram;
0185     void __iomem *mbx;
0186     bool use_hecc1int;
0187     spinlock_t mbx_lock; /* CANME register needs protection */
0188     u32 tx_head;
0189     u32 tx_tail;
0190     struct regulator *reg_xceiver;
0191 };
0192 
0193 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
0194 {
0195     return priv->tx_head & HECC_TX_MB_MASK;
0196 }
0197 
0198 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
0199 {
0200     return priv->tx_tail & HECC_TX_MB_MASK;
0201 }
0202 
0203 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
0204 {
0205     return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
0206 }
0207 
0208 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
0209 {
0210     __raw_writel(val, priv->hecc_ram + mbxno * 4);
0211 }
0212 
0213 static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
0214 {
0215     return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
0216 }
0217 
0218 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
0219                   u32 reg, u32 val)
0220 {
0221     __raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
0222 }
0223 
0224 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
0225 {
0226     return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
0227 }
0228 
0229 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
0230 {
0231     __raw_writel(val, priv->base + reg);
0232 }
0233 
0234 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
0235 {
0236     return __raw_readl(priv->base + reg);
0237 }
0238 
0239 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
0240                 u32 bit_mask)
0241 {
0242     hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
0243 }
0244 
0245 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
0246                   u32 bit_mask)
0247 {
0248     hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
0249 }
0250 
0251 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
0252 {
0253     return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
0254 }
0255 
0256 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
0257 {
0258     struct can_bittiming *bit_timing = &priv->can.bittiming;
0259     u32 can_btc;
0260 
0261     can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
0262     can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
0263             & 0xF) << 3;
0264     if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
0265         if (bit_timing->brp > 4)
0266             can_btc |= HECC_CANBTC_SAM;
0267         else
0268             netdev_warn(priv->ndev,
0269                     "WARN: Triple sampling not set due to h/w limitations");
0270     }
0271     can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
0272     can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
0273 
0274     /* ERM being set to 0 by default meaning resync at falling edge */
0275 
0276     hecc_write(priv, HECC_CANBTC, can_btc);
0277     netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
0278 
0279     return 0;
0280 }
0281 
0282 static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
0283                       int on)
0284 {
0285     if (!priv->reg_xceiver)
0286         return 0;
0287 
0288     if (on)
0289         return regulator_enable(priv->reg_xceiver);
0290     else
0291         return regulator_disable(priv->reg_xceiver);
0292 }
0293 
0294 static void ti_hecc_reset(struct net_device *ndev)
0295 {
0296     u32 cnt;
0297     struct ti_hecc_priv *priv = netdev_priv(ndev);
0298 
0299     netdev_dbg(ndev, "resetting hecc ...\n");
0300     hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
0301 
0302     /* Set change control request and wait till enabled */
0303     hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
0304 
0305     /* INFO: It has been observed that at times CCE bit may not be
0306      * set and hw seems to be ok even if this bit is not set so
0307      * timing out with a timing of 1ms to respect the specs
0308      */
0309     cnt = HECC_CCE_WAIT_COUNT;
0310     while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
0311         --cnt;
0312         udelay(10);
0313     }
0314 
0315     /* Note: On HECC, BTC can be programmed only in initialization mode, so
0316      * it is expected that the can bittiming parameters are set via ip
0317      * utility before the device is opened
0318      */
0319     ti_hecc_set_btc(priv);
0320 
0321     /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
0322     hecc_write(priv, HECC_CANMC, 0);
0323 
0324     /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
0325      * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
0326      */
0327 
0328     /* INFO: It has been observed that at times CCE bit may not be
0329      * set and hw seems to be ok even if this bit is not set so
0330      */
0331     cnt = HECC_CCE_WAIT_COUNT;
0332     while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
0333         --cnt;
0334         udelay(10);
0335     }
0336 
0337     /* Enable TX and RX I/O Control pins */
0338     hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
0339     hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
0340 
0341     /* Clear registers for clean operation */
0342     hecc_write(priv, HECC_CANTA, HECC_SET_REG);
0343     hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
0344     hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
0345     hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
0346     hecc_write(priv, HECC_CANME, 0);
0347     hecc_write(priv, HECC_CANMD, 0);
0348 
0349     /* SCC compat mode NOT supported (and not needed too) */
0350     hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
0351 }
0352 
0353 static void ti_hecc_start(struct net_device *ndev)
0354 {
0355     struct ti_hecc_priv *priv = netdev_priv(ndev);
0356     u32 cnt, mbxno, mbx_mask;
0357 
0358     /* put HECC in initialization mode and set btc */
0359     ti_hecc_reset(ndev);
0360 
0361     priv->tx_head = HECC_TX_MASK;
0362     priv->tx_tail = HECC_TX_MASK;
0363 
0364     /* Enable local and global acceptance mask registers */
0365     hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
0366 
0367     /* Prepare configured mailboxes to receive messages */
0368     for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
0369         mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
0370         mbx_mask = BIT(mbxno);
0371         hecc_clear_bit(priv, HECC_CANME, mbx_mask);
0372         hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
0373         hecc_write_lam(priv, mbxno, HECC_SET_REG);
0374         hecc_set_bit(priv, HECC_CANMD, mbx_mask);
0375         hecc_set_bit(priv, HECC_CANME, mbx_mask);
0376         hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
0377     }
0378 
0379     /* Enable tx interrupts */
0380     hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1);
0381 
0382     /* Prevent message over-write to create a rx fifo, but not for
0383      * the lowest priority mailbox, since that allows detecting
0384      * overflows instead of the hardware silently dropping the
0385      * messages.
0386      */
0387     mbx_mask = ~BIT(HECC_RX_LAST_MBOX);
0388     hecc_write(priv, HECC_CANOPC, mbx_mask);
0389 
0390     /* Enable interrupts */
0391     if (priv->use_hecc1int) {
0392         hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
0393         hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
0394             HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
0395     } else {
0396         hecc_write(priv, HECC_CANMIL, 0);
0397         hecc_write(priv, HECC_CANGIM,
0398                HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
0399     }
0400     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0401 }
0402 
0403 static void ti_hecc_stop(struct net_device *ndev)
0404 {
0405     struct ti_hecc_priv *priv = netdev_priv(ndev);
0406 
0407     /* Disable the CPK; stop sending, erroring and acking */
0408     hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
0409 
0410     /* Disable interrupts and disable mailboxes */
0411     hecc_write(priv, HECC_CANGIM, 0);
0412     hecc_write(priv, HECC_CANMIM, 0);
0413     hecc_write(priv, HECC_CANME, 0);
0414     priv->can.state = CAN_STATE_STOPPED;
0415 }
0416 
0417 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
0418 {
0419     int ret = 0;
0420 
0421     switch (mode) {
0422     case CAN_MODE_START:
0423         ti_hecc_start(ndev);
0424         netif_wake_queue(ndev);
0425         break;
0426     default:
0427         ret = -EOPNOTSUPP;
0428         break;
0429     }
0430 
0431     return ret;
0432 }
0433 
0434 static int ti_hecc_get_berr_counter(const struct net_device *ndev,
0435                     struct can_berr_counter *bec)
0436 {
0437     struct ti_hecc_priv *priv = netdev_priv(ndev);
0438 
0439     bec->txerr = hecc_read(priv, HECC_CANTEC);
0440     bec->rxerr = hecc_read(priv, HECC_CANREC);
0441 
0442     return 0;
0443 }
0444 
0445 /* ti_hecc_xmit: HECC Transmit
0446  *
0447  * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
0448  * priority of the mailbox for transmission is dependent upon priority setting
0449  * field in mailbox registers. The mailbox with highest value in priority field
0450  * is transmitted first. Only when two mailboxes have the same value in
0451  * priority field the highest numbered mailbox is transmitted first.
0452  *
0453  * To utilize the HECC priority feature as described above we start with the
0454  * highest numbered mailbox with highest priority level and move on to the next
0455  * mailbox with the same priority level and so on. Once we loop through all the
0456  * transmit mailboxes we choose the next priority level (lower) and so on
0457  * until we reach the lowest priority level on the lowest numbered mailbox
0458  * when we stop transmission until all mailboxes are transmitted and then
0459  * restart at highest numbered mailbox with highest priority.
0460  *
0461  * Two counters (head and tail) are used to track the next mailbox to transmit
0462  * and to track the echo buffer for already transmitted mailbox. The queue
0463  * is stopped when all the mailboxes are busy or when there is a priority
0464  * value roll-over happens.
0465  */
0466 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
0467 {
0468     struct ti_hecc_priv *priv = netdev_priv(ndev);
0469     struct can_frame *cf = (struct can_frame *)skb->data;
0470     u32 mbxno, mbx_mask, data;
0471     unsigned long flags;
0472 
0473     if (can_dropped_invalid_skb(ndev, skb))
0474         return NETDEV_TX_OK;
0475 
0476     mbxno = get_tx_head_mb(priv);
0477     mbx_mask = BIT(mbxno);
0478     spin_lock_irqsave(&priv->mbx_lock, flags);
0479     if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
0480         spin_unlock_irqrestore(&priv->mbx_lock, flags);
0481         netif_stop_queue(ndev);
0482         netdev_err(priv->ndev,
0483                "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
0484                priv->tx_head, priv->tx_tail);
0485         return NETDEV_TX_BUSY;
0486     }
0487     spin_unlock_irqrestore(&priv->mbx_lock, flags);
0488 
0489     /* Prepare mailbox for transmission */
0490     data = cf->len | (get_tx_head_prio(priv) << 8);
0491     if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
0492         data |= HECC_CANMCF_RTR;
0493     hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
0494 
0495     if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
0496         data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
0497     else /* Standard frame format */
0498         data = (cf->can_id & CAN_SFF_MASK) << 18;
0499     hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
0500     hecc_write_mbx(priv, mbxno, HECC_CANMDL,
0501                be32_to_cpu(*(__be32 *)(cf->data)));
0502     if (cf->len > 4)
0503         hecc_write_mbx(priv, mbxno, HECC_CANMDH,
0504                    be32_to_cpu(*(__be32 *)(cf->data + 4)));
0505     else
0506         *(u32 *)(cf->data + 4) = 0;
0507     can_put_echo_skb(skb, ndev, mbxno, 0);
0508 
0509     spin_lock_irqsave(&priv->mbx_lock, flags);
0510     --priv->tx_head;
0511     if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
0512         (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
0513         netif_stop_queue(ndev);
0514     }
0515     hecc_set_bit(priv, HECC_CANME, mbx_mask);
0516     spin_unlock_irqrestore(&priv->mbx_lock, flags);
0517 
0518     hecc_write(priv, HECC_CANTRS, mbx_mask);
0519 
0520     return NETDEV_TX_OK;
0521 }
0522 
0523 static inline
0524 struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
0525 {
0526     return container_of(offload, struct ti_hecc_priv, offload);
0527 }
0528 
0529 static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload,
0530                         unsigned int mbxno, u32 *timestamp,
0531                         bool drop)
0532 {
0533     struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
0534     struct sk_buff *skb;
0535     struct can_frame *cf;
0536     u32 data, mbx_mask;
0537 
0538     mbx_mask = BIT(mbxno);
0539 
0540     if (unlikely(drop)) {
0541         skb = ERR_PTR(-ENOBUFS);
0542         goto mark_as_read;
0543     }
0544 
0545     skb = alloc_can_skb(offload->dev, &cf);
0546     if (unlikely(!skb)) {
0547         skb = ERR_PTR(-ENOMEM);
0548         goto mark_as_read;
0549     }
0550 
0551     data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
0552     if (data & HECC_CANMID_IDE)
0553         cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
0554     else
0555         cf->can_id = (data >> 18) & CAN_SFF_MASK;
0556 
0557     data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
0558     if (data & HECC_CANMCF_RTR)
0559         cf->can_id |= CAN_RTR_FLAG;
0560     cf->len = can_cc_dlc2len(data & 0xF);
0561 
0562     data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
0563     *(__be32 *)(cf->data) = cpu_to_be32(data);
0564     if (cf->len > 4) {
0565         data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
0566         *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
0567     }
0568 
0569     *timestamp = hecc_read_stamp(priv, mbxno);
0570 
0571     /* Check for FIFO overrun.
0572      *
0573      * All but the last RX mailbox have activated overwrite
0574      * protection. So skip check for overrun, if we're not
0575      * handling the last RX mailbox.
0576      *
0577      * As the overwrite protection for the last RX mailbox is
0578      * disabled, the CAN core might update while we're reading
0579      * it. This means the skb might be inconsistent.
0580      *
0581      * Return an error to let rx-offload discard this CAN frame.
0582      */
0583     if (unlikely(mbxno == HECC_RX_LAST_MBOX &&
0584              hecc_read(priv, HECC_CANRML) & mbx_mask))
0585         skb = ERR_PTR(-ENOBUFS);
0586 
0587  mark_as_read:
0588     hecc_write(priv, HECC_CANRMP, mbx_mask);
0589 
0590     return skb;
0591 }
0592 
0593 static int ti_hecc_error(struct net_device *ndev, int int_status,
0594              int err_status)
0595 {
0596     struct ti_hecc_priv *priv = netdev_priv(ndev);
0597     struct can_frame *cf;
0598     struct sk_buff *skb;
0599     u32 timestamp;
0600     int err;
0601 
0602     if (err_status & HECC_BUS_ERROR) {
0603         /* propagate the error condition to the can stack */
0604         skb = alloc_can_err_skb(ndev, &cf);
0605         if (!skb) {
0606             if (net_ratelimit())
0607                 netdev_err(priv->ndev,
0608                        "%s: alloc_can_err_skb() failed\n",
0609                        __func__);
0610             return -ENOMEM;
0611         }
0612 
0613         ++priv->can.can_stats.bus_error;
0614         cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
0615         if (err_status & HECC_CANES_FE)
0616             cf->data[2] |= CAN_ERR_PROT_FORM;
0617         if (err_status & HECC_CANES_BE)
0618             cf->data[2] |= CAN_ERR_PROT_BIT;
0619         if (err_status & HECC_CANES_SE)
0620             cf->data[2] |= CAN_ERR_PROT_STUFF;
0621         if (err_status & HECC_CANES_CRCE)
0622             cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
0623         if (err_status & HECC_CANES_ACKE)
0624             cf->data[3] = CAN_ERR_PROT_LOC_ACK;
0625 
0626         timestamp = hecc_read(priv, HECC_CANLNT);
0627         err = can_rx_offload_queue_timestamp(&priv->offload, skb,
0628                           timestamp);
0629         if (err)
0630             ndev->stats.rx_fifo_errors++;
0631     }
0632 
0633     hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS);
0634 
0635     return 0;
0636 }
0637 
0638 static void ti_hecc_change_state(struct net_device *ndev,
0639                  enum can_state rx_state,
0640                  enum can_state tx_state)
0641 {
0642     struct ti_hecc_priv *priv = netdev_priv(ndev);
0643     struct can_frame *cf;
0644     struct sk_buff *skb;
0645     u32 timestamp;
0646     int err;
0647 
0648     skb = alloc_can_err_skb(priv->ndev, &cf);
0649     if (unlikely(!skb)) {
0650         priv->can.state = max(tx_state, rx_state);
0651         return;
0652     }
0653 
0654     can_change_state(priv->ndev, cf, tx_state, rx_state);
0655 
0656     if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) {
0657         cf->can_id |= CAN_ERR_CNT;
0658         cf->data[6] = hecc_read(priv, HECC_CANTEC);
0659         cf->data[7] = hecc_read(priv, HECC_CANREC);
0660     }
0661 
0662     timestamp = hecc_read(priv, HECC_CANLNT);
0663     err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
0664     if (err)
0665         ndev->stats.rx_fifo_errors++;
0666 }
0667 
0668 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
0669 {
0670     struct net_device *ndev = (struct net_device *)dev_id;
0671     struct ti_hecc_priv *priv = netdev_priv(ndev);
0672     struct net_device_stats *stats = &ndev->stats;
0673     u32 mbxno, mbx_mask, int_status, err_status, stamp;
0674     unsigned long flags, rx_pending;
0675     u32 handled = 0;
0676 
0677     int_status = hecc_read(priv,
0678                    priv->use_hecc1int ?
0679                    HECC_CANGIF1 : HECC_CANGIF0);
0680 
0681     if (!int_status)
0682         return IRQ_NONE;
0683 
0684     err_status = hecc_read(priv, HECC_CANES);
0685     if (unlikely(err_status & HECC_CANES_FLAGS))
0686         ti_hecc_error(ndev, int_status, err_status);
0687 
0688     if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) {
0689         enum can_state rx_state, tx_state;
0690         u32 rec = hecc_read(priv, HECC_CANREC);
0691         u32 tec = hecc_read(priv, HECC_CANTEC);
0692 
0693         if (int_status & HECC_CANGIF_WLIF) {
0694             handled |= HECC_CANGIF_WLIF;
0695             rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0;
0696             tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0;
0697             netdev_dbg(priv->ndev, "Error Warning interrupt\n");
0698             ti_hecc_change_state(ndev, rx_state, tx_state);
0699         }
0700 
0701         if (int_status & HECC_CANGIF_EPIF) {
0702             handled |= HECC_CANGIF_EPIF;
0703             rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0;
0704             tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0;
0705             netdev_dbg(priv->ndev, "Error passive interrupt\n");
0706             ti_hecc_change_state(ndev, rx_state, tx_state);
0707         }
0708 
0709         if (int_status & HECC_CANGIF_BOIF) {
0710             handled |= HECC_CANGIF_BOIF;
0711             rx_state = CAN_STATE_BUS_OFF;
0712             tx_state = CAN_STATE_BUS_OFF;
0713             netdev_dbg(priv->ndev, "Bus off interrupt\n");
0714 
0715             /* Disable all interrupts */
0716             hecc_write(priv, HECC_CANGIM, 0);
0717             can_bus_off(ndev);
0718             ti_hecc_change_state(ndev, rx_state, tx_state);
0719         }
0720     } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) {
0721         enum can_state new_state, tx_state, rx_state;
0722         u32 rec = hecc_read(priv, HECC_CANREC);
0723         u32 tec = hecc_read(priv, HECC_CANTEC);
0724 
0725         if (rec >= 128 || tec >= 128)
0726             new_state = CAN_STATE_ERROR_PASSIVE;
0727         else if (rec >= 96 || tec >= 96)
0728             new_state = CAN_STATE_ERROR_WARNING;
0729         else
0730             new_state = CAN_STATE_ERROR_ACTIVE;
0731 
0732         if (new_state < priv->can.state) {
0733             rx_state = rec >= tec ? new_state : 0;
0734             tx_state = rec <= tec ? new_state : 0;
0735             ti_hecc_change_state(ndev, rx_state, tx_state);
0736         }
0737     }
0738 
0739     if (int_status & HECC_CANGIF_GMIF) {
0740         while (priv->tx_tail - priv->tx_head > 0) {
0741             mbxno = get_tx_tail_mb(priv);
0742             mbx_mask = BIT(mbxno);
0743             if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
0744                 break;
0745             hecc_write(priv, HECC_CANTA, mbx_mask);
0746             spin_lock_irqsave(&priv->mbx_lock, flags);
0747             hecc_clear_bit(priv, HECC_CANME, mbx_mask);
0748             spin_unlock_irqrestore(&priv->mbx_lock, flags);
0749             stamp = hecc_read_stamp(priv, mbxno);
0750             stats->tx_bytes +=
0751                 can_rx_offload_get_echo_skb(&priv->offload,
0752                                 mbxno, stamp, NULL);
0753             stats->tx_packets++;
0754             --priv->tx_tail;
0755         }
0756 
0757         /* restart queue if wrap-up or if queue stalled on last pkt */
0758         if ((priv->tx_head == priv->tx_tail &&
0759              ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
0760             (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
0761              ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
0762             netif_wake_queue(ndev);
0763 
0764         /* offload RX mailboxes and let NAPI deliver them */
0765         while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
0766             can_rx_offload_irq_offload_timestamp(&priv->offload,
0767                                  rx_pending);
0768         }
0769     }
0770 
0771     /* clear all interrupt conditions - read back to avoid spurious ints */
0772     if (priv->use_hecc1int) {
0773         hecc_write(priv, HECC_CANGIF1, handled);
0774         int_status = hecc_read(priv, HECC_CANGIF1);
0775     } else {
0776         hecc_write(priv, HECC_CANGIF0, handled);
0777         int_status = hecc_read(priv, HECC_CANGIF0);
0778     }
0779 
0780     can_rx_offload_irq_finish(&priv->offload);
0781 
0782     return IRQ_HANDLED;
0783 }
0784 
0785 static int ti_hecc_open(struct net_device *ndev)
0786 {
0787     struct ti_hecc_priv *priv = netdev_priv(ndev);
0788     int err;
0789 
0790     err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
0791               ndev->name, ndev);
0792     if (err) {
0793         netdev_err(ndev, "error requesting interrupt\n");
0794         return err;
0795     }
0796 
0797     ti_hecc_transceiver_switch(priv, 1);
0798 
0799     /* Open common can device */
0800     err = open_candev(ndev);
0801     if (err) {
0802         netdev_err(ndev, "open_candev() failed %d\n", err);
0803         ti_hecc_transceiver_switch(priv, 0);
0804         free_irq(ndev->irq, ndev);
0805         return err;
0806     }
0807 
0808     ti_hecc_start(ndev);
0809     can_rx_offload_enable(&priv->offload);
0810     netif_start_queue(ndev);
0811 
0812     return 0;
0813 }
0814 
0815 static int ti_hecc_close(struct net_device *ndev)
0816 {
0817     struct ti_hecc_priv *priv = netdev_priv(ndev);
0818 
0819     netif_stop_queue(ndev);
0820     can_rx_offload_disable(&priv->offload);
0821     ti_hecc_stop(ndev);
0822     free_irq(ndev->irq, ndev);
0823     close_candev(ndev);
0824     ti_hecc_transceiver_switch(priv, 0);
0825 
0826     return 0;
0827 }
0828 
0829 static const struct net_device_ops ti_hecc_netdev_ops = {
0830     .ndo_open       = ti_hecc_open,
0831     .ndo_stop       = ti_hecc_close,
0832     .ndo_start_xmit     = ti_hecc_xmit,
0833     .ndo_change_mtu     = can_change_mtu,
0834 };
0835 
0836 static const struct ethtool_ops ti_hecc_ethtool_ops = {
0837     .get_ts_info = ethtool_op_get_ts_info,
0838 };
0839 
0840 static const struct of_device_id ti_hecc_dt_ids[] = {
0841     {
0842         .compatible = "ti,am3517-hecc",
0843     },
0844     { }
0845 };
0846 MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
0847 
0848 static int ti_hecc_probe(struct platform_device *pdev)
0849 {
0850     struct net_device *ndev = (struct net_device *)0;
0851     struct ti_hecc_priv *priv;
0852     struct device_node *np = pdev->dev.of_node;
0853     struct regulator *reg_xceiver;
0854     int err = -ENODEV;
0855 
0856     if (!IS_ENABLED(CONFIG_OF) || !np)
0857         return -EINVAL;
0858 
0859     reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
0860     if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
0861         return -EPROBE_DEFER;
0862     else if (IS_ERR(reg_xceiver))
0863         reg_xceiver = NULL;
0864 
0865     ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
0866     if (!ndev) {
0867         dev_err(&pdev->dev, "alloc_candev failed\n");
0868         return -ENOMEM;
0869     }
0870     priv = netdev_priv(ndev);
0871 
0872     /* handle hecc memory */
0873     priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc");
0874     if (IS_ERR(priv->base)) {
0875         dev_err(&pdev->dev, "hecc ioremap failed\n");
0876         err = PTR_ERR(priv->base);
0877         goto probe_exit_candev;
0878     }
0879 
0880     /* handle hecc-ram memory */
0881     priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev,
0882                                    "hecc-ram");
0883     if (IS_ERR(priv->hecc_ram)) {
0884         dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
0885         err = PTR_ERR(priv->hecc_ram);
0886         goto probe_exit_candev;
0887     }
0888 
0889     /* handle mbx memory */
0890     priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx");
0891     if (IS_ERR(priv->mbx)) {
0892         dev_err(&pdev->dev, "mbx ioremap failed\n");
0893         err = PTR_ERR(priv->mbx);
0894         goto probe_exit_candev;
0895     }
0896 
0897     ndev->irq = platform_get_irq(pdev, 0);
0898     if (ndev->irq < 0) {
0899         err = ndev->irq;
0900         goto probe_exit_candev;
0901     }
0902 
0903     priv->ndev = ndev;
0904     priv->reg_xceiver = reg_xceiver;
0905     priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
0906 
0907     priv->can.bittiming_const = &ti_hecc_bittiming_const;
0908     priv->can.do_set_mode = ti_hecc_do_set_mode;
0909     priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
0910     priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
0911 
0912     spin_lock_init(&priv->mbx_lock);
0913     ndev->flags |= IFF_ECHO;
0914     platform_set_drvdata(pdev, ndev);
0915     SET_NETDEV_DEV(ndev, &pdev->dev);
0916     ndev->netdev_ops = &ti_hecc_netdev_ops;
0917     ndev->ethtool_ops = &ti_hecc_ethtool_ops;
0918 
0919     priv->clk = clk_get(&pdev->dev, "hecc_ck");
0920     if (IS_ERR(priv->clk)) {
0921         dev_err(&pdev->dev, "No clock available\n");
0922         err = PTR_ERR(priv->clk);
0923         priv->clk = NULL;
0924         goto probe_exit_candev;
0925     }
0926     priv->can.clock.freq = clk_get_rate(priv->clk);
0927 
0928     err = clk_prepare_enable(priv->clk);
0929     if (err) {
0930         dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
0931         goto probe_exit_release_clk;
0932     }
0933 
0934     priv->offload.mailbox_read = ti_hecc_mailbox_read;
0935     priv->offload.mb_first = HECC_RX_FIRST_MBOX;
0936     priv->offload.mb_last = HECC_RX_LAST_MBOX;
0937     err = can_rx_offload_add_timestamp(ndev, &priv->offload);
0938     if (err) {
0939         dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
0940         goto probe_exit_disable_clk;
0941     }
0942 
0943     err = register_candev(ndev);
0944     if (err) {
0945         dev_err(&pdev->dev, "register_candev() failed\n");
0946         goto probe_exit_offload;
0947     }
0948 
0949     dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
0950          priv->base, (u32)ndev->irq);
0951 
0952     return 0;
0953 
0954 probe_exit_offload:
0955     can_rx_offload_del(&priv->offload);
0956 probe_exit_disable_clk:
0957     clk_disable_unprepare(priv->clk);
0958 probe_exit_release_clk:
0959     clk_put(priv->clk);
0960 probe_exit_candev:
0961     free_candev(ndev);
0962 
0963     return err;
0964 }
0965 
0966 static int ti_hecc_remove(struct platform_device *pdev)
0967 {
0968     struct net_device *ndev = platform_get_drvdata(pdev);
0969     struct ti_hecc_priv *priv = netdev_priv(ndev);
0970 
0971     unregister_candev(ndev);
0972     clk_disable_unprepare(priv->clk);
0973     clk_put(priv->clk);
0974     can_rx_offload_del(&priv->offload);
0975     free_candev(ndev);
0976 
0977     return 0;
0978 }
0979 
0980 #ifdef CONFIG_PM
0981 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
0982 {
0983     struct net_device *dev = platform_get_drvdata(pdev);
0984     struct ti_hecc_priv *priv = netdev_priv(dev);
0985 
0986     if (netif_running(dev)) {
0987         netif_stop_queue(dev);
0988         netif_device_detach(dev);
0989     }
0990 
0991     hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
0992     priv->can.state = CAN_STATE_SLEEPING;
0993 
0994     clk_disable_unprepare(priv->clk);
0995 
0996     return 0;
0997 }
0998 
0999 static int ti_hecc_resume(struct platform_device *pdev)
1000 {
1001     struct net_device *dev = platform_get_drvdata(pdev);
1002     struct ti_hecc_priv *priv = netdev_priv(dev);
1003     int err;
1004 
1005     err = clk_prepare_enable(priv->clk);
1006     if (err)
1007         return err;
1008 
1009     hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1010     priv->can.state = CAN_STATE_ERROR_ACTIVE;
1011 
1012     if (netif_running(dev)) {
1013         netif_device_attach(dev);
1014         netif_start_queue(dev);
1015     }
1016 
1017     return 0;
1018 }
1019 #else
1020 #define ti_hecc_suspend NULL
1021 #define ti_hecc_resume NULL
1022 #endif
1023 
1024 /* TI HECC netdevice driver: platform driver structure */
1025 static struct platform_driver ti_hecc_driver = {
1026     .driver = {
1027         .name    = DRV_NAME,
1028         .of_match_table = ti_hecc_dt_ids,
1029     },
1030     .probe = ti_hecc_probe,
1031     .remove = ti_hecc_remove,
1032     .suspend = ti_hecc_suspend,
1033     .resume = ti_hecc_resume,
1034 };
1035 
1036 module_platform_driver(ti_hecc_driver);
1037 
1038 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1039 MODULE_LICENSE("GPL v2");
1040 MODULE_DESCRIPTION(DRV_DESC);
1041 MODULE_ALIAS("platform:" DRV_NAME);
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