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0001 /*
0002  * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs
0003  *
0004  * Copyright (C) 2013 Peter Chen
0005  * Copyright (C) 2015 Gerhard Bertelsmann
0006  * All rights reserved.
0007  *
0008  * Parts of this software are based on (derived from) the SJA1000 code by:
0009  *   Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
0010  *   Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
0011  *   Copyright (C) 2002-2007 Volkswagen Group Electronic Research
0012  *   Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
0013  *   38106 Braunschweig, GERMANY
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  * 3. Neither the name of Volkswagen nor the names of its contributors
0024  *    may be used to endorse or promote products derived from this software
0025  *    without specific prior written permission.
0026  *
0027  * Alternatively, provided that this notice is retained in full, this
0028  * software may be distributed under the terms of the GNU General
0029  * Public License ("GPL") version 2, in which case the provisions of the
0030  * GPL apply INSTEAD OF those given above.
0031  *
0032  * The provided data structures and external interfaces from this code
0033  * are not restricted to be used by modules with a GPL compatible license.
0034  *
0035  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0036  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0037  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0038  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0039  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0040  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0041  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0042  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0043  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0044  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0045  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
0046  * DAMAGE.
0047  *
0048  */
0049 
0050 #include <linux/netdevice.h>
0051 #include <linux/can.h>
0052 #include <linux/can/dev.h>
0053 #include <linux/can/error.h>
0054 #include <linux/clk.h>
0055 #include <linux/delay.h>
0056 #include <linux/ethtool.h>
0057 #include <linux/interrupt.h>
0058 #include <linux/init.h>
0059 #include <linux/io.h>
0060 #include <linux/module.h>
0061 #include <linux/of.h>
0062 #include <linux/of_device.h>
0063 #include <linux/platform_device.h>
0064 #include <linux/reset.h>
0065 
0066 #define DRV_NAME "sun4i_can"
0067 
0068 /* Registers address (physical base address 0x01C2BC00) */
0069 #define SUN4I_REG_MSEL_ADDR 0x0000  /* CAN Mode Select */
0070 #define SUN4I_REG_CMD_ADDR  0x0004  /* CAN Command */
0071 #define SUN4I_REG_STA_ADDR  0x0008  /* CAN Status */
0072 #define SUN4I_REG_INT_ADDR  0x000c  /* CAN Interrupt Flag */
0073 #define SUN4I_REG_INTEN_ADDR    0x0010  /* CAN Interrupt Enable */
0074 #define SUN4I_REG_BTIME_ADDR    0x0014  /* CAN Bus Timing 0 */
0075 #define SUN4I_REG_TEWL_ADDR 0x0018  /* CAN Tx Error Warning Limit */
0076 #define SUN4I_REG_ERRC_ADDR 0x001c  /* CAN Error Counter */
0077 #define SUN4I_REG_RMCNT_ADDR    0x0020  /* CAN Receive Message Counter */
0078 #define SUN4I_REG_RBUFSA_ADDR   0x0024  /* CAN Receive Buffer Start Address */
0079 #define SUN4I_REG_BUF0_ADDR 0x0040  /* CAN Tx/Rx Buffer 0 */
0080 #define SUN4I_REG_BUF1_ADDR 0x0044  /* CAN Tx/Rx Buffer 1 */
0081 #define SUN4I_REG_BUF2_ADDR 0x0048  /* CAN Tx/Rx Buffer 2 */
0082 #define SUN4I_REG_BUF3_ADDR 0x004c  /* CAN Tx/Rx Buffer 3 */
0083 #define SUN4I_REG_BUF4_ADDR 0x0050  /* CAN Tx/Rx Buffer 4 */
0084 #define SUN4I_REG_BUF5_ADDR 0x0054  /* CAN Tx/Rx Buffer 5 */
0085 #define SUN4I_REG_BUF6_ADDR 0x0058  /* CAN Tx/Rx Buffer 6 */
0086 #define SUN4I_REG_BUF7_ADDR 0x005c  /* CAN Tx/Rx Buffer 7 */
0087 #define SUN4I_REG_BUF8_ADDR 0x0060  /* CAN Tx/Rx Buffer 8 */
0088 #define SUN4I_REG_BUF9_ADDR 0x0064  /* CAN Tx/Rx Buffer 9 */
0089 #define SUN4I_REG_BUF10_ADDR    0x0068  /* CAN Tx/Rx Buffer 10 */
0090 #define SUN4I_REG_BUF11_ADDR    0x006c  /* CAN Tx/Rx Buffer 11 */
0091 #define SUN4I_REG_BUF12_ADDR    0x0070  /* CAN Tx/Rx Buffer 12 */
0092 #define SUN4I_REG_ACPC_ADDR 0x0040  /* CAN Acceptance Code 0 */
0093 #define SUN4I_REG_ACPM_ADDR 0x0044  /* CAN Acceptance Mask 0 */
0094 #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180  /* CAN transmit buffer start */
0095 #define SUN4I_REG_RBUF_RBACK_END_ADDR   0x01b0  /* CAN transmit buffer end */
0096 
0097 /* Controller Register Description */
0098 
0099 /* mode select register (r/w)
0100  * offset:0x0000 default:0x0000_0001
0101  */
0102 #define SUN4I_MSEL_SLEEP_MODE       (0x01 << 4) /* write in reset mode */
0103 #define SUN4I_MSEL_WAKE_UP      (0x00 << 4)
0104 #define SUN4I_MSEL_SINGLE_FILTER    (0x01 << 3) /* write in reset mode */
0105 #define SUN4I_MSEL_DUAL_FILTERS     (0x00 << 3)
0106 #define SUN4I_MSEL_LOOPBACK_MODE    BIT(2)
0107 #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1)
0108 #define SUN4I_MSEL_RESET_MODE       BIT(0)
0109 
0110 /* command register (w)
0111  * offset:0x0004 default:0x0000_0000
0112  */
0113 #define SUN4I_CMD_BUS_OFF_REQ   BIT(5)
0114 #define SUN4I_CMD_SELF_RCV_REQ  BIT(4)
0115 #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3)
0116 #define SUN4I_CMD_RELEASE_RBUF  BIT(2)
0117 #define SUN4I_CMD_ABORT_REQ BIT(1)
0118 #define SUN4I_CMD_TRANS_REQ BIT(0)
0119 
0120 /* status register (r)
0121  * offset:0x0008 default:0x0000_003c
0122  */
0123 #define SUN4I_STA_BIT_ERR   (0x00 << 22)
0124 #define SUN4I_STA_FORM_ERR  (0x01 << 22)
0125 #define SUN4I_STA_STUFF_ERR (0x02 << 22)
0126 #define SUN4I_STA_OTHER_ERR (0x03 << 22)
0127 #define SUN4I_STA_MASK_ERR  (0x03 << 22)
0128 #define SUN4I_STA_ERR_DIR   BIT(21)
0129 #define SUN4I_STA_ERR_SEG_CODE  (0x1f << 16)
0130 #define SUN4I_STA_START     (0x03 << 16)
0131 #define SUN4I_STA_ID28_21   (0x02 << 16)
0132 #define SUN4I_STA_ID20_18   (0x06 << 16)
0133 #define SUN4I_STA_SRTR      (0x04 << 16)
0134 #define SUN4I_STA_IDE       (0x05 << 16)
0135 #define SUN4I_STA_ID17_13   (0x07 << 16)
0136 #define SUN4I_STA_ID12_5    (0x0f << 16)
0137 #define SUN4I_STA_ID4_0     (0x0e << 16)
0138 #define SUN4I_STA_RTR       (0x0c << 16)
0139 #define SUN4I_STA_RB1       (0x0d << 16)
0140 #define SUN4I_STA_RB0       (0x09 << 16)
0141 #define SUN4I_STA_DLEN      (0x0b << 16)
0142 #define SUN4I_STA_DATA_FIELD    (0x0a << 16)
0143 #define SUN4I_STA_CRC_SEQUENCE  (0x08 << 16)
0144 #define SUN4I_STA_CRC_DELIMITER (0x18 << 16)
0145 #define SUN4I_STA_ACK       (0x19 << 16)
0146 #define SUN4I_STA_ACK_DELIMITER (0x1b << 16)
0147 #define SUN4I_STA_END       (0x1a << 16)
0148 #define SUN4I_STA_INTERMISSION  (0x12 << 16)
0149 #define SUN4I_STA_ACTIVE_ERROR  (0x11 << 16)
0150 #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16)
0151 #define SUN4I_STA_TOLERATE_DOMINANT_BITS    (0x13 << 16)
0152 #define SUN4I_STA_ERROR_DELIMITER   (0x17 << 16)
0153 #define SUN4I_STA_OVERLOAD  (0x1c << 16)
0154 #define SUN4I_STA_BUS_OFF   BIT(7)
0155 #define SUN4I_STA_ERR_STA   BIT(6)
0156 #define SUN4I_STA_TRANS_BUSY    BIT(5)
0157 #define SUN4I_STA_RCV_BUSY  BIT(4)
0158 #define SUN4I_STA_TRANS_OVER    BIT(3)
0159 #define SUN4I_STA_TBUF_RDY  BIT(2)
0160 #define SUN4I_STA_DATA_ORUN BIT(1)
0161 #define SUN4I_STA_RBUF_RDY  BIT(0)
0162 
0163 /* interrupt register (r)
0164  * offset:0x000c default:0x0000_0000
0165  */
0166 #define SUN4I_INT_BUS_ERR   BIT(7)
0167 #define SUN4I_INT_ARB_LOST  BIT(6)
0168 #define SUN4I_INT_ERR_PASSIVE   BIT(5)
0169 #define SUN4I_INT_WAKEUP    BIT(4)
0170 #define SUN4I_INT_DATA_OR   BIT(3)
0171 #define SUN4I_INT_ERR_WRN   BIT(2)
0172 #define SUN4I_INT_TBUF_VLD  BIT(1)
0173 #define SUN4I_INT_RBUF_VLD  BIT(0)
0174 
0175 /* interrupt enable register (r/w)
0176  * offset:0x0010 default:0x0000_0000
0177  */
0178 #define SUN4I_INTEN_BERR    BIT(7)
0179 #define SUN4I_INTEN_ARB_LOST    BIT(6)
0180 #define SUN4I_INTEN_ERR_PASSIVE BIT(5)
0181 #define SUN4I_INTEN_WAKEUP  BIT(4)
0182 #define SUN4I_INTEN_OR      BIT(3)
0183 #define SUN4I_INTEN_ERR_WRN BIT(2)
0184 #define SUN4I_INTEN_TX      BIT(1)
0185 #define SUN4I_INTEN_RX      BIT(0)
0186 
0187 /* error code */
0188 #define SUN4I_ERR_INRCV     (0x1 << 5)
0189 #define SUN4I_ERR_INTRANS   (0x0 << 5)
0190 
0191 /* filter mode */
0192 #define SUN4I_FILTER_CLOSE  0
0193 #define SUN4I_SINGLE_FLTER_MODE 1
0194 #define SUN4I_DUAL_FILTER_MODE  2
0195 
0196 /* message buffer flags */
0197 #define SUN4I_MSG_EFF_FLAG  BIT(7)
0198 #define SUN4I_MSG_RTR_FLAG  BIT(6)
0199 
0200 /* max. number of interrupts handled in ISR */
0201 #define SUN4I_CAN_MAX_IRQ   20
0202 #define SUN4I_MODE_MAX_RETRIES  100
0203 
0204 /**
0205  * struct sun4ican_quirks - Differences between SoC variants.
0206  *
0207  * @has_reset: SoC needs reset deasserted.
0208  */
0209 struct sun4ican_quirks {
0210     bool has_reset;
0211 };
0212 
0213 struct sun4ican_priv {
0214     struct can_priv can;
0215     void __iomem *base;
0216     struct clk *clk;
0217     struct reset_control *reset;
0218     spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
0219 };
0220 
0221 static const struct can_bittiming_const sun4ican_bittiming_const = {
0222     .name = DRV_NAME,
0223     .tseg1_min = 1,
0224     .tseg1_max = 16,
0225     .tseg2_min = 1,
0226     .tseg2_max = 8,
0227     .sjw_max = 4,
0228     .brp_min = 1,
0229     .brp_max = 64,
0230     .brp_inc = 1,
0231 };
0232 
0233 static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val)
0234 {
0235     unsigned long flags;
0236 
0237     spin_lock_irqsave(&priv->cmdreg_lock, flags);
0238     writel(val, priv->base + SUN4I_REG_CMD_ADDR);
0239     spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
0240 }
0241 
0242 static int set_normal_mode(struct net_device *dev)
0243 {
0244     struct sun4ican_priv *priv = netdev_priv(dev);
0245     int retry = SUN4I_MODE_MAX_RETRIES;
0246     u32 mod_reg_val = 0;
0247 
0248     do {
0249         mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
0250         mod_reg_val &= ~SUN4I_MSEL_RESET_MODE;
0251         writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
0252     } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE));
0253 
0254     if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) {
0255         netdev_err(dev,
0256                "setting controller into normal mode failed!\n");
0257         return -ETIMEDOUT;
0258     }
0259 
0260     return 0;
0261 }
0262 
0263 static int set_reset_mode(struct net_device *dev)
0264 {
0265     struct sun4ican_priv *priv = netdev_priv(dev);
0266     int retry = SUN4I_MODE_MAX_RETRIES;
0267     u32 mod_reg_val = 0;
0268 
0269     do {
0270         mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
0271         mod_reg_val |= SUN4I_MSEL_RESET_MODE;
0272         writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
0273     } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE));
0274 
0275     if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) &
0276           SUN4I_MSEL_RESET_MODE)) {
0277         netdev_err(dev, "setting controller into reset mode failed!\n");
0278         return -ETIMEDOUT;
0279     }
0280 
0281     return 0;
0282 }
0283 
0284 /* bittiming is called in reset_mode only */
0285 static int sun4ican_set_bittiming(struct net_device *dev)
0286 {
0287     struct sun4ican_priv *priv = netdev_priv(dev);
0288     struct can_bittiming *bt = &priv->can.bittiming;
0289     u32 cfg;
0290 
0291     cfg = ((bt->brp - 1) & 0x3FF) |
0292          (((bt->sjw - 1) & 0x3) << 14) |
0293          (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) |
0294          (((bt->phase_seg2 - 1) & 0x7) << 20);
0295     if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
0296         cfg |= 0x800000;
0297 
0298     netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg);
0299     writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
0300 
0301     return 0;
0302 }
0303 
0304 static int sun4ican_get_berr_counter(const struct net_device *dev,
0305                      struct can_berr_counter *bec)
0306 {
0307     struct sun4ican_priv *priv = netdev_priv(dev);
0308     u32 errors;
0309     int err;
0310 
0311     err = clk_prepare_enable(priv->clk);
0312     if (err) {
0313         netdev_err(dev, "could not enable clock\n");
0314         return err;
0315     }
0316 
0317     errors = readl(priv->base + SUN4I_REG_ERRC_ADDR);
0318 
0319     bec->txerr = errors & 0xFF;
0320     bec->rxerr = (errors >> 16) & 0xFF;
0321 
0322     clk_disable_unprepare(priv->clk);
0323 
0324     return 0;
0325 }
0326 
0327 static int sun4i_can_start(struct net_device *dev)
0328 {
0329     struct sun4ican_priv *priv = netdev_priv(dev);
0330     int err;
0331     u32 mod_reg_val;
0332 
0333     /* we need to enter the reset mode */
0334     err = set_reset_mode(dev);
0335     if (err) {
0336         netdev_err(dev, "could not enter reset mode\n");
0337         return err;
0338     }
0339 
0340     /* set filters - we accept all */
0341     writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
0342     writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
0343 
0344     /* clear error counters and error code capture */
0345     writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
0346 
0347     /* enable interrupts */
0348     if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
0349         writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
0350     else
0351         writel(0xFF & ~SUN4I_INTEN_BERR,
0352                priv->base + SUN4I_REG_INTEN_ADDR);
0353 
0354     /* enter the selected mode */
0355     mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
0356     if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
0357         mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE;
0358     else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
0359         mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE;
0360     writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
0361 
0362     err = sun4ican_set_bittiming(dev);
0363     if (err)
0364         return err;
0365 
0366     /* we are ready to enter the normal mode */
0367     err = set_normal_mode(dev);
0368     if (err) {
0369         netdev_err(dev, "could not enter normal mode\n");
0370         return err;
0371     }
0372 
0373     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0374 
0375     return 0;
0376 }
0377 
0378 static int sun4i_can_stop(struct net_device *dev)
0379 {
0380     struct sun4ican_priv *priv = netdev_priv(dev);
0381     int err;
0382 
0383     priv->can.state = CAN_STATE_STOPPED;
0384     /* we need to enter reset mode */
0385     err = set_reset_mode(dev);
0386     if (err) {
0387         netdev_err(dev, "could not enter reset mode\n");
0388         return err;
0389     }
0390 
0391     /* disable all interrupts */
0392     writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
0393 
0394     return 0;
0395 }
0396 
0397 static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode)
0398 {
0399     int err;
0400 
0401     switch (mode) {
0402     case CAN_MODE_START:
0403         err = sun4i_can_start(dev);
0404         if (err) {
0405             netdev_err(dev, "starting CAN controller failed!\n");
0406             return err;
0407         }
0408         if (netif_queue_stopped(dev))
0409             netif_wake_queue(dev);
0410         break;
0411 
0412     default:
0413         return -EOPNOTSUPP;
0414     }
0415     return 0;
0416 }
0417 
0418 /* transmit a CAN message
0419  * message layout in the sk_buff should be like this:
0420  * xx xx xx xx         ff         ll 00 11 22 33 44 55 66 77
0421  * [ can_id ] [flags] [len] [can data (up to 8 bytes]
0422  */
0423 static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev)
0424 {
0425     struct sun4ican_priv *priv = netdev_priv(dev);
0426     struct can_frame *cf = (struct can_frame *)skb->data;
0427     u8 dlc;
0428     u32 dreg, msg_flag_n;
0429     canid_t id;
0430     int i;
0431 
0432     if (can_dropped_invalid_skb(dev, skb))
0433         return NETDEV_TX_OK;
0434 
0435     netif_stop_queue(dev);
0436 
0437     id = cf->can_id;
0438     dlc = cf->len;
0439     msg_flag_n = dlc;
0440 
0441     if (id & CAN_RTR_FLAG)
0442         msg_flag_n |= SUN4I_MSG_RTR_FLAG;
0443 
0444     if (id & CAN_EFF_FLAG) {
0445         msg_flag_n |= SUN4I_MSG_EFF_FLAG;
0446         dreg = SUN4I_REG_BUF5_ADDR;
0447         writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
0448         writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
0449         writel((id >> 5)  & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
0450         writel((id << 3)  & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
0451     } else {
0452         dreg = SUN4I_REG_BUF3_ADDR;
0453         writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
0454         writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
0455     }
0456 
0457     for (i = 0; i < dlc; i++)
0458         writel(cf->data[i], priv->base + (dreg + i * 4));
0459 
0460     writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
0461 
0462     can_put_echo_skb(skb, dev, 0, 0);
0463 
0464     if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
0465         sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ);
0466     else
0467         sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ);
0468 
0469     return NETDEV_TX_OK;
0470 }
0471 
0472 static void sun4i_can_rx(struct net_device *dev)
0473 {
0474     struct sun4ican_priv *priv = netdev_priv(dev);
0475     struct net_device_stats *stats = &dev->stats;
0476     struct can_frame *cf;
0477     struct sk_buff *skb;
0478     u8 fi;
0479     u32 dreg;
0480     canid_t id;
0481     int i;
0482 
0483     /* create zero'ed CAN frame buffer */
0484     skb = alloc_can_skb(dev, &cf);
0485     if (!skb)
0486         return;
0487 
0488     fi = readl(priv->base + SUN4I_REG_BUF0_ADDR);
0489     cf->len = can_cc_dlc2len(fi & 0x0F);
0490     if (fi & SUN4I_MSG_EFF_FLAG) {
0491         dreg = SUN4I_REG_BUF5_ADDR;
0492         id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) |
0493              (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) |
0494              (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5)  |
0495             ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3)  & 0x1f);
0496         id |= CAN_EFF_FLAG;
0497     } else {
0498         dreg = SUN4I_REG_BUF3_ADDR;
0499         id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) |
0500             ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7);
0501     }
0502 
0503     /* remote frame ? */
0504     if (fi & SUN4I_MSG_RTR_FLAG) {
0505         id |= CAN_RTR_FLAG;
0506     } else {
0507         for (i = 0; i < cf->len; i++)
0508             cf->data[i] = readl(priv->base + dreg + i * 4);
0509 
0510         stats->rx_bytes += cf->len;
0511     }
0512     stats->rx_packets++;
0513 
0514     cf->can_id = id;
0515 
0516     sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF);
0517 
0518     netif_rx(skb);
0519 }
0520 
0521 static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status)
0522 {
0523     struct sun4ican_priv *priv = netdev_priv(dev);
0524     struct net_device_stats *stats = &dev->stats;
0525     struct can_frame *cf;
0526     struct sk_buff *skb;
0527     enum can_state state = priv->can.state;
0528     enum can_state rx_state, tx_state;
0529     unsigned int rxerr, txerr, errc;
0530     u32 ecc, alc;
0531 
0532     /* we don't skip if alloc fails because we want the stats anyhow */
0533     skb = alloc_can_err_skb(dev, &cf);
0534 
0535     errc = readl(priv->base + SUN4I_REG_ERRC_ADDR);
0536     rxerr = (errc >> 16) & 0xFF;
0537     txerr = errc & 0xFF;
0538 
0539     if (isrc & SUN4I_INT_DATA_OR) {
0540         /* data overrun interrupt */
0541         netdev_dbg(dev, "data overrun interrupt\n");
0542         if (likely(skb)) {
0543             cf->can_id |= CAN_ERR_CRTL;
0544             cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
0545         }
0546         stats->rx_over_errors++;
0547         stats->rx_errors++;
0548 
0549         /* reset the CAN IP by entering reset mode
0550          * ignoring timeout error
0551          */
0552         set_reset_mode(dev);
0553         set_normal_mode(dev);
0554 
0555         /* clear bit */
0556         sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG);
0557     }
0558     if (isrc & SUN4I_INT_ERR_WRN) {
0559         /* error warning interrupt */
0560         netdev_dbg(dev, "error warning interrupt\n");
0561 
0562         if (status & SUN4I_STA_BUS_OFF)
0563             state = CAN_STATE_BUS_OFF;
0564         else if (status & SUN4I_STA_ERR_STA)
0565             state = CAN_STATE_ERROR_WARNING;
0566         else
0567             state = CAN_STATE_ERROR_ACTIVE;
0568     }
0569     if (skb && state != CAN_STATE_BUS_OFF) {
0570         cf->can_id |= CAN_ERR_CNT;
0571         cf->data[6] = txerr;
0572         cf->data[7] = rxerr;
0573     }
0574     if (isrc & SUN4I_INT_BUS_ERR) {
0575         /* bus error interrupt */
0576         netdev_dbg(dev, "bus error interrupt\n");
0577         priv->can.can_stats.bus_error++;
0578         stats->rx_errors++;
0579 
0580         if (likely(skb)) {
0581             ecc = readl(priv->base + SUN4I_REG_STA_ADDR);
0582 
0583             cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
0584 
0585             switch (ecc & SUN4I_STA_MASK_ERR) {
0586             case SUN4I_STA_BIT_ERR:
0587                 cf->data[2] |= CAN_ERR_PROT_BIT;
0588                 break;
0589             case SUN4I_STA_FORM_ERR:
0590                 cf->data[2] |= CAN_ERR_PROT_FORM;
0591                 break;
0592             case SUN4I_STA_STUFF_ERR:
0593                 cf->data[2] |= CAN_ERR_PROT_STUFF;
0594                 break;
0595             default:
0596                 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE)
0597                            >> 16;
0598                 break;
0599             }
0600             /* error occurred during transmission? */
0601             if ((ecc & SUN4I_STA_ERR_DIR) == 0)
0602                 cf->data[2] |= CAN_ERR_PROT_TX;
0603         }
0604     }
0605     if (isrc & SUN4I_INT_ERR_PASSIVE) {
0606         /* error passive interrupt */
0607         netdev_dbg(dev, "error passive interrupt\n");
0608         if (state == CAN_STATE_ERROR_PASSIVE)
0609             state = CAN_STATE_ERROR_WARNING;
0610         else
0611             state = CAN_STATE_ERROR_PASSIVE;
0612     }
0613     if (isrc & SUN4I_INT_ARB_LOST) {
0614         /* arbitration lost interrupt */
0615         netdev_dbg(dev, "arbitration lost interrupt\n");
0616         alc = readl(priv->base + SUN4I_REG_STA_ADDR);
0617         priv->can.can_stats.arbitration_lost++;
0618         if (likely(skb)) {
0619             cf->can_id |= CAN_ERR_LOSTARB;
0620             cf->data[0] = (alc >> 8) & 0x1f;
0621         }
0622     }
0623 
0624     if (state != priv->can.state) {
0625         tx_state = txerr >= rxerr ? state : 0;
0626         rx_state = txerr <= rxerr ? state : 0;
0627 
0628         if (likely(skb))
0629             can_change_state(dev, cf, tx_state, rx_state);
0630         else
0631             priv->can.state = state;
0632         if (state == CAN_STATE_BUS_OFF)
0633             can_bus_off(dev);
0634     }
0635 
0636     if (likely(skb))
0637         netif_rx(skb);
0638     else
0639         return -ENOMEM;
0640 
0641     return 0;
0642 }
0643 
0644 static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
0645 {
0646     struct net_device *dev = (struct net_device *)dev_id;
0647     struct sun4ican_priv *priv = netdev_priv(dev);
0648     struct net_device_stats *stats = &dev->stats;
0649     u8 isrc, status;
0650     int n = 0;
0651 
0652     while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
0653            (n < SUN4I_CAN_MAX_IRQ)) {
0654         n++;
0655         status = readl(priv->base + SUN4I_REG_STA_ADDR);
0656 
0657         if (isrc & SUN4I_INT_WAKEUP)
0658             netdev_warn(dev, "wakeup interrupt\n");
0659 
0660         if (isrc & SUN4I_INT_TBUF_VLD) {
0661             /* transmission complete interrupt */
0662             stats->tx_bytes += can_get_echo_skb(dev, 0, NULL);
0663             stats->tx_packets++;
0664             netif_wake_queue(dev);
0665         }
0666         if ((isrc & SUN4I_INT_RBUF_VLD) &&
0667             !(isrc & SUN4I_INT_DATA_OR)) {
0668             /* receive interrupt - don't read if overrun occurred */
0669             while (status & SUN4I_STA_RBUF_RDY) {
0670                 /* RX buffer is not empty */
0671                 sun4i_can_rx(dev);
0672                 status = readl(priv->base + SUN4I_REG_STA_ADDR);
0673             }
0674         }
0675         if (isrc &
0676             (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR |
0677              SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) {
0678             /* error interrupt */
0679             if (sun4i_can_err(dev, isrc, status))
0680                 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n");
0681         }
0682         /* clear interrupts */
0683         writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
0684         readl(priv->base + SUN4I_REG_INT_ADDR);
0685     }
0686     if (n >= SUN4I_CAN_MAX_IRQ)
0687         netdev_dbg(dev, "%d messages handled in ISR", n);
0688 
0689     return (n) ? IRQ_HANDLED : IRQ_NONE;
0690 }
0691 
0692 static int sun4ican_open(struct net_device *dev)
0693 {
0694     struct sun4ican_priv *priv = netdev_priv(dev);
0695     int err;
0696 
0697     /* common open */
0698     err = open_candev(dev);
0699     if (err)
0700         return err;
0701 
0702     /* register interrupt handler */
0703     err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev);
0704     if (err) {
0705         netdev_err(dev, "request_irq err: %d\n", err);
0706         goto exit_irq;
0707     }
0708 
0709     /* software reset deassert */
0710     err = reset_control_deassert(priv->reset);
0711     if (err) {
0712         netdev_err(dev, "could not deassert CAN reset\n");
0713         goto exit_soft_reset;
0714     }
0715 
0716     /* turn on clocking for CAN peripheral block */
0717     err = clk_prepare_enable(priv->clk);
0718     if (err) {
0719         netdev_err(dev, "could not enable CAN peripheral clock\n");
0720         goto exit_clock;
0721     }
0722 
0723     err = sun4i_can_start(dev);
0724     if (err) {
0725         netdev_err(dev, "could not start CAN peripheral\n");
0726         goto exit_can_start;
0727     }
0728 
0729     netif_start_queue(dev);
0730 
0731     return 0;
0732 
0733 exit_can_start:
0734     clk_disable_unprepare(priv->clk);
0735 exit_clock:
0736     reset_control_assert(priv->reset);
0737 exit_soft_reset:
0738     free_irq(dev->irq, dev);
0739 exit_irq:
0740     close_candev(dev);
0741     return err;
0742 }
0743 
0744 static int sun4ican_close(struct net_device *dev)
0745 {
0746     struct sun4ican_priv *priv = netdev_priv(dev);
0747 
0748     netif_stop_queue(dev);
0749     sun4i_can_stop(dev);
0750     clk_disable_unprepare(priv->clk);
0751     reset_control_assert(priv->reset);
0752 
0753     free_irq(dev->irq, dev);
0754     close_candev(dev);
0755 
0756     return 0;
0757 }
0758 
0759 static const struct net_device_ops sun4ican_netdev_ops = {
0760     .ndo_open = sun4ican_open,
0761     .ndo_stop = sun4ican_close,
0762     .ndo_start_xmit = sun4ican_start_xmit,
0763 };
0764 
0765 static const struct ethtool_ops sun4ican_ethtool_ops = {
0766     .get_ts_info = ethtool_op_get_ts_info,
0767 };
0768 
0769 static const struct sun4ican_quirks sun4ican_quirks_a10 = {
0770     .has_reset = false,
0771 };
0772 
0773 static const struct sun4ican_quirks sun4ican_quirks_r40 = {
0774     .has_reset = true,
0775 };
0776 
0777 static const struct of_device_id sun4ican_of_match[] = {
0778     {
0779         .compatible = "allwinner,sun4i-a10-can",
0780         .data = &sun4ican_quirks_a10
0781     }, {
0782         .compatible = "allwinner,sun7i-a20-can",
0783         .data = &sun4ican_quirks_a10
0784     }, {
0785         .compatible = "allwinner,sun8i-r40-can",
0786         .data = &sun4ican_quirks_r40
0787     }, {
0788         /* sentinel */
0789     },
0790 };
0791 
0792 MODULE_DEVICE_TABLE(of, sun4ican_of_match);
0793 
0794 static int sun4ican_remove(struct platform_device *pdev)
0795 {
0796     struct net_device *dev = platform_get_drvdata(pdev);
0797 
0798     unregister_netdev(dev);
0799     free_candev(dev);
0800 
0801     return 0;
0802 }
0803 
0804 static int sun4ican_probe(struct platform_device *pdev)
0805 {
0806     struct device_node *np = pdev->dev.of_node;
0807     struct clk *clk;
0808     struct reset_control *reset = NULL;
0809     void __iomem *addr;
0810     int err, irq;
0811     struct net_device *dev;
0812     struct sun4ican_priv *priv;
0813     const struct sun4ican_quirks *quirks;
0814 
0815     quirks = of_device_get_match_data(&pdev->dev);
0816     if (!quirks) {
0817         dev_err(&pdev->dev, "failed to determine the quirks to use\n");
0818         err = -ENODEV;
0819         goto exit;
0820     }
0821 
0822     if (quirks->has_reset) {
0823         reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0824         if (IS_ERR(reset)) {
0825             dev_err(&pdev->dev, "unable to request reset\n");
0826             err = PTR_ERR(reset);
0827             goto exit;
0828         }
0829     }
0830 
0831     clk = of_clk_get(np, 0);
0832     if (IS_ERR(clk)) {
0833         dev_err(&pdev->dev, "unable to request clock\n");
0834         err = -ENODEV;
0835         goto exit;
0836     }
0837 
0838     irq = platform_get_irq(pdev, 0);
0839     if (irq < 0) {
0840         err = -ENODEV;
0841         goto exit;
0842     }
0843 
0844     addr = devm_platform_ioremap_resource(pdev, 0);
0845     if (IS_ERR(addr)) {
0846         err = PTR_ERR(addr);
0847         goto exit;
0848     }
0849 
0850     dev = alloc_candev(sizeof(struct sun4ican_priv), 1);
0851     if (!dev) {
0852         dev_err(&pdev->dev,
0853             "could not allocate memory for CAN device\n");
0854         err = -ENOMEM;
0855         goto exit;
0856     }
0857 
0858     dev->netdev_ops = &sun4ican_netdev_ops;
0859     dev->ethtool_ops = &sun4ican_ethtool_ops;
0860     dev->irq = irq;
0861     dev->flags |= IFF_ECHO;
0862 
0863     priv = netdev_priv(dev);
0864     priv->can.clock.freq = clk_get_rate(clk);
0865     priv->can.bittiming_const = &sun4ican_bittiming_const;
0866     priv->can.do_set_mode = sun4ican_set_mode;
0867     priv->can.do_get_berr_counter = sun4ican_get_berr_counter;
0868     priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
0869                        CAN_CTRLMODE_LISTENONLY |
0870                        CAN_CTRLMODE_LOOPBACK |
0871                        CAN_CTRLMODE_3_SAMPLES;
0872     priv->base = addr;
0873     priv->clk = clk;
0874     priv->reset = reset;
0875     spin_lock_init(&priv->cmdreg_lock);
0876 
0877     platform_set_drvdata(pdev, dev);
0878     SET_NETDEV_DEV(dev, &pdev->dev);
0879 
0880     err = register_candev(dev);
0881     if (err) {
0882         dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
0883             DRV_NAME, err);
0884         goto exit_free;
0885     }
0886 
0887     dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n",
0888          priv->base, dev->irq);
0889 
0890     return 0;
0891 
0892 exit_free:
0893     free_candev(dev);
0894 exit:
0895     return err;
0896 }
0897 
0898 static struct platform_driver sun4i_can_driver = {
0899     .driver = {
0900         .name = DRV_NAME,
0901         .of_match_table = sun4ican_of_match,
0902     },
0903     .probe = sun4ican_probe,
0904     .remove = sun4ican_remove,
0905 };
0906 
0907 module_platform_driver(sun4i_can_driver);
0908 
0909 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
0910 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
0911 MODULE_LICENSE("Dual BSD/GPL");
0912 MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
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