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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
0004 //
0005 // Copyright (c) 2019, 2020, 2021 Pengutronix,
0006 //               Marc Kleine-Budde <kernel@pengutronix.de>
0007 //
0008 // Based on:
0009 //
0010 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
0011 //
0012 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
0013 //
0014 
0015 #include <asm/unaligned.h>
0016 #include <linux/bitfield.h>
0017 #include <linux/clk.h>
0018 #include <linux/device.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/module.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/property.h>
0023 
0024 #include "mcp251xfd.h"
0025 
0026 #define DEVICE_NAME "mcp251xfd"
0027 
0028 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
0029     .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
0030         MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
0031         MCP251XFD_QUIRK_ECC,
0032     .model = MCP251XFD_MODEL_MCP2517FD,
0033 };
0034 
0035 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
0036     .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
0037         MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
0038     .model = MCP251XFD_MODEL_MCP2518FD,
0039 };
0040 
0041 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
0042     .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
0043         MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
0044     .model = MCP251XFD_MODEL_MCP251863,
0045 };
0046 
0047 /* Autodetect model, start with CRC enabled. */
0048 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
0049     .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
0050         MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
0051     .model = MCP251XFD_MODEL_MCP251XFD,
0052 };
0053 
0054 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
0055     .name = DEVICE_NAME,
0056     .tseg1_min = 2,
0057     .tseg1_max = 256,
0058     .tseg2_min = 1,
0059     .tseg2_max = 128,
0060     .sjw_max = 128,
0061     .brp_min = 1,
0062     .brp_max = 256,
0063     .brp_inc = 1,
0064 };
0065 
0066 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
0067     .name = DEVICE_NAME,
0068     .tseg1_min = 1,
0069     .tseg1_max = 32,
0070     .tseg2_min = 1,
0071     .tseg2_max = 16,
0072     .sjw_max = 16,
0073     .brp_min = 1,
0074     .brp_max = 256,
0075     .brp_inc = 1,
0076 };
0077 
0078 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
0079 {
0080     switch (model) {
0081     case MCP251XFD_MODEL_MCP2517FD:
0082         return "MCP2517FD";
0083     case MCP251XFD_MODEL_MCP2518FD:
0084         return "MCP2518FD";
0085     case MCP251XFD_MODEL_MCP251863:
0086         return "MCP251863";
0087     case MCP251XFD_MODEL_MCP251XFD:
0088         return "MCP251xFD";
0089     }
0090 
0091     return "<unknown>";
0092 }
0093 
0094 static inline const char *
0095 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
0096 {
0097     return __mcp251xfd_get_model_str(priv->devtype_data.model);
0098 }
0099 
0100 static const char *mcp251xfd_get_mode_str(const u8 mode)
0101 {
0102     switch (mode) {
0103     case MCP251XFD_REG_CON_MODE_MIXED:
0104         return "Mixed (CAN FD/CAN 2.0)";
0105     case MCP251XFD_REG_CON_MODE_SLEEP:
0106         return "Sleep";
0107     case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
0108         return "Internal Loopback";
0109     case MCP251XFD_REG_CON_MODE_LISTENONLY:
0110         return "Listen Only";
0111     case MCP251XFD_REG_CON_MODE_CONFIG:
0112         return "Configuration";
0113     case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
0114         return "External Loopback";
0115     case MCP251XFD_REG_CON_MODE_CAN2_0:
0116         return "CAN 2.0";
0117     case MCP251XFD_REG_CON_MODE_RESTRICTED:
0118         return "Restricted Operation";
0119     }
0120 
0121     return "<unknown>";
0122 }
0123 
0124 static const char *
0125 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
0126 {
0127     switch (~osc & osc_reference &
0128         (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
0129     case MCP251XFD_REG_OSC_PLLRDY:
0130         return "PLL";
0131     case MCP251XFD_REG_OSC_OSCRDY:
0132         return "Oscillator";
0133     case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
0134         return "Oscillator/PLL";
0135     }
0136 
0137     return "<unknown>";
0138 }
0139 
0140 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
0141 {
0142     if (!priv->reg_vdd)
0143         return 0;
0144 
0145     return regulator_enable(priv->reg_vdd);
0146 }
0147 
0148 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
0149 {
0150     if (!priv->reg_vdd)
0151         return 0;
0152 
0153     return regulator_disable(priv->reg_vdd);
0154 }
0155 
0156 static inline int
0157 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
0158 {
0159     if (!priv->reg_xceiver)
0160         return 0;
0161 
0162     return regulator_enable(priv->reg_xceiver);
0163 }
0164 
0165 static inline int
0166 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
0167 {
0168     if (!priv->reg_xceiver)
0169         return 0;
0170 
0171     return regulator_disable(priv->reg_xceiver);
0172 }
0173 
0174 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
0175 {
0176     int err;
0177 
0178     err = clk_prepare_enable(priv->clk);
0179     if (err)
0180         return err;
0181 
0182     err = mcp251xfd_vdd_enable(priv);
0183     if (err)
0184         clk_disable_unprepare(priv->clk);
0185 
0186     /* Wait for oscillator stabilisation time after power up */
0187     usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
0188              2 * MCP251XFD_OSC_STAB_SLEEP_US);
0189 
0190     return err;
0191 }
0192 
0193 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
0194 {
0195     int err;
0196 
0197     err = mcp251xfd_vdd_disable(priv);
0198     if (err)
0199         return err;
0200 
0201     clk_disable_unprepare(priv->clk);
0202 
0203     return 0;
0204 }
0205 
0206 static inline bool mcp251xfd_reg_invalid(u32 reg)
0207 {
0208     return reg == 0x0 || reg == 0xffffffff;
0209 }
0210 
0211 static inline int
0212 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
0213 {
0214     u32 val;
0215     int err;
0216 
0217     err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
0218     if (err)
0219         return err;
0220 
0221     *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
0222 
0223     return 0;
0224 }
0225 
0226 static int
0227 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
0228               const u8 mode_req, bool nowait)
0229 {
0230     u32 con = 0, con_reqop, osc = 0;
0231     u8 mode;
0232     int err;
0233 
0234     con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
0235     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
0236                  MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
0237     if (err == -EBADMSG) {
0238         netdev_err(priv->ndev,
0239                "Failed to set Requested Operation Mode.\n");
0240 
0241         return -ENODEV;
0242     } else if (err) {
0243         return err;
0244     }
0245 
0246     if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
0247         return 0;
0248 
0249     err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
0250                        !mcp251xfd_reg_invalid(con) &&
0251                        FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
0252                          con) == mode_req,
0253                        MCP251XFD_POLL_SLEEP_US,
0254                        MCP251XFD_POLL_TIMEOUT_US);
0255     if (err != -ETIMEDOUT && err != -EBADMSG)
0256         return err;
0257 
0258     /* Ignore return value.
0259      * Print below error messages, even if this fails.
0260      */
0261     regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
0262 
0263     if (mcp251xfd_reg_invalid(con)) {
0264         netdev_err(priv->ndev,
0265                "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
0266                con, osc);
0267 
0268         return -ENODEV;
0269     }
0270 
0271     mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
0272     netdev_err(priv->ndev,
0273            "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
0274            mcp251xfd_get_mode_str(mode_req), mode_req,
0275            mcp251xfd_get_mode_str(mode), mode,
0276            con, osc);
0277 
0278     return -ETIMEDOUT;
0279 }
0280 
0281 static inline int
0282 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
0283             const u8 mode_req)
0284 {
0285     return __mcp251xfd_chip_set_mode(priv, mode_req, false);
0286 }
0287 
0288 static inline int __maybe_unused
0289 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
0290                    const u8 mode_req)
0291 {
0292     return __mcp251xfd_chip_set_mode(priv, mode_req, true);
0293 }
0294 
0295 static int
0296 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
0297                   u32 osc_reference, u32 osc_mask)
0298 {
0299     u32 osc;
0300     int err;
0301 
0302     err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
0303                        !mcp251xfd_reg_invalid(osc) &&
0304                        (osc & osc_mask) == osc_reference,
0305                        MCP251XFD_OSC_STAB_SLEEP_US,
0306                        MCP251XFD_OSC_STAB_TIMEOUT_US);
0307     if (err != -ETIMEDOUT)
0308         return err;
0309 
0310     if (mcp251xfd_reg_invalid(osc)) {
0311         netdev_err(priv->ndev,
0312                "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
0313                osc);
0314         return -ENODEV;
0315     }
0316 
0317     netdev_err(priv->ndev,
0318            "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
0319            mcp251xfd_get_osc_str(osc, osc_reference),
0320            osc, osc_reference, osc_mask);
0321 
0322     return -ETIMEDOUT;
0323 }
0324 
0325 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
0326 {
0327     u32 osc, osc_reference, osc_mask;
0328     int err;
0329 
0330     /* For normal sleep on MCP2517FD and MCP2518FD, clearing
0331      * "Oscillator Disable" will wake the chip. For low power mode
0332      * on MCP2518FD, asserting the chip select will wake the
0333      * chip. Writing to the Oscillator register will wake it in
0334      * both cases.
0335      */
0336     osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
0337              MCP251XFD_REG_OSC_CLKODIV_10);
0338 
0339     /* We cannot check for the PLL ready bit (either set or
0340      * unset), as the PLL might be enabled. This can happen if the
0341      * system reboots, while the mcp251xfd stays powered.
0342      */
0343     osc_reference = MCP251XFD_REG_OSC_OSCRDY;
0344     osc_mask = MCP251XFD_REG_OSC_OSCRDY;
0345 
0346     /* If the controller is in Sleep Mode the following write only
0347      * removes the "Oscillator Disable" bit and powers it up. All
0348      * other bits are unaffected.
0349      */
0350     err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
0351     if (err)
0352         return err;
0353 
0354     /* Sometimes the PLL is stuck enabled, the controller never
0355      * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
0356      * caller takes care of retry.
0357      */
0358     return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
0359 }
0360 
0361 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
0362 {
0363     if (priv->pll_enable) {
0364         u32 osc;
0365         int err;
0366 
0367         /* Turn off PLL */
0368         osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
0369                  MCP251XFD_REG_OSC_CLKODIV_10);
0370         err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
0371         if (err)
0372             netdev_err(priv->ndev,
0373                    "Failed to disable PLL.\n");
0374 
0375         priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
0376     }
0377 
0378     return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
0379 }
0380 
0381 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
0382 {
0383     const __be16 cmd = mcp251xfd_cmd_reset();
0384     int err;
0385 
0386     /* The Set Mode and SPI Reset command only works if the
0387      * controller is not in Sleep Mode.
0388      */
0389     err = mcp251xfd_chip_wake(priv);
0390     if (err)
0391         return err;
0392 
0393     err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
0394     if (err)
0395         return err;
0396 
0397     /* spi_write_then_read() works with non DMA-safe buffers */
0398     return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
0399 }
0400 
0401 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
0402 {
0403     u32 osc_reference, osc_mask;
0404     u8 mode;
0405     int err;
0406 
0407     /* Check for reset defaults of OSC reg.
0408      * This will take care of stabilization period.
0409      */
0410     osc_reference = MCP251XFD_REG_OSC_OSCRDY |
0411         FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
0412                MCP251XFD_REG_OSC_CLKODIV_10);
0413     osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
0414     err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
0415     if (err)
0416         return err;
0417 
0418     err = mcp251xfd_chip_get_mode(priv, &mode);
0419     if (err)
0420         return err;
0421 
0422     if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
0423         netdev_info(priv->ndev,
0424                 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
0425                 mcp251xfd_get_mode_str(mode), mode);
0426         return -ETIMEDOUT;
0427     }
0428 
0429     return 0;
0430 }
0431 
0432 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
0433 {
0434     int err, i;
0435 
0436     for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
0437         if (i)
0438             netdev_info(priv->ndev,
0439                     "Retrying to reset controller.\n");
0440 
0441         err = mcp251xfd_chip_softreset_do(priv);
0442         if (err == -ETIMEDOUT)
0443             continue;
0444         if (err)
0445             return err;
0446 
0447         err = mcp251xfd_chip_softreset_check(priv);
0448         if (err == -ETIMEDOUT)
0449             continue;
0450         if (err)
0451             return err;
0452 
0453         return 0;
0454     }
0455 
0456     return err;
0457 }
0458 
0459 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
0460 {
0461     u32 osc, osc_reference, osc_mask;
0462     int err;
0463 
0464     /* Activate Low Power Mode on Oscillator Disable. This only
0465      * works on the MCP2518FD. The MCP2517FD will go into normal
0466      * Sleep Mode instead.
0467      */
0468     osc = MCP251XFD_REG_OSC_LPMEN |
0469         FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
0470                MCP251XFD_REG_OSC_CLKODIV_10);
0471     osc_reference = MCP251XFD_REG_OSC_OSCRDY;
0472     osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
0473 
0474     if (priv->pll_enable) {
0475         osc |= MCP251XFD_REG_OSC_PLLEN;
0476         osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
0477     }
0478 
0479     err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
0480     if (err)
0481         return err;
0482 
0483     err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
0484     if (err)
0485         return err;
0486 
0487     priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
0488 
0489     return 0;
0490 }
0491 
0492 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
0493 {
0494     /* Set Time Base Counter Prescaler to 1.
0495      *
0496      * This means an overflow of the 32 bit Time Base Counter
0497      * register at 40 MHz every 107 seconds.
0498      */
0499     return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
0500                 MCP251XFD_REG_TSCON_TBCEN);
0501 }
0502 
0503 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
0504 {
0505     const struct can_bittiming *bt = &priv->can.bittiming;
0506     const struct can_bittiming *dbt = &priv->can.data_bittiming;
0507     u32 val = 0;
0508     s8 tdco;
0509     int err;
0510 
0511     /* CAN Control Register
0512      *
0513      * - no transmit bandwidth sharing
0514      * - config mode
0515      * - disable transmit queue
0516      * - store in transmit FIFO event
0517      * - transition to restricted operation mode on system error
0518      * - ESI is transmitted recessive when ESI of message is high or
0519      *   CAN controller error passive
0520      * - restricted retransmission attempts,
0521      *   use TQXCON_TXAT and FIFOCON_TXAT
0522      * - wake-up filter bits T11FILTER
0523      * - use CAN bus line filter for wakeup
0524      * - protocol exception is treated as a form error
0525      * - Do not compare data bytes
0526      */
0527     val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
0528              MCP251XFD_REG_CON_MODE_CONFIG) |
0529         MCP251XFD_REG_CON_STEF |
0530         MCP251XFD_REG_CON_ESIGM |
0531         MCP251XFD_REG_CON_RTXAT |
0532         FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
0533                MCP251XFD_REG_CON_WFT_T11FILTER) |
0534         MCP251XFD_REG_CON_WAKFIL |
0535         MCP251XFD_REG_CON_PXEDIS;
0536 
0537     if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
0538         val |= MCP251XFD_REG_CON_ISOCRCEN;
0539 
0540     err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
0541     if (err)
0542         return err;
0543 
0544     /* Nominal Bit Time */
0545     val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
0546         FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
0547                bt->prop_seg + bt->phase_seg1 - 1) |
0548         FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
0549                bt->phase_seg2 - 1) |
0550         FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
0551 
0552     err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
0553     if (err)
0554         return err;
0555 
0556     if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
0557         return 0;
0558 
0559     /* Data Bit Time */
0560     val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
0561         FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
0562                dbt->prop_seg + dbt->phase_seg1 - 1) |
0563         FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
0564                dbt->phase_seg2 - 1) |
0565         FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
0566 
0567     err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
0568     if (err)
0569         return err;
0570 
0571     /* Transmitter Delay Compensation */
0572     tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
0573                -64, 63);
0574     val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
0575              MCP251XFD_REG_TDC_TDCMOD_AUTO) |
0576         FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
0577 
0578     return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
0579 }
0580 
0581 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
0582 {
0583     u32 val;
0584 
0585     if (!priv->rx_int)
0586         return 0;
0587 
0588     /* Configure GPIOs:
0589      * - PIN0: GPIO Input
0590      * - PIN1: GPIO Input/RX Interrupt
0591      *
0592      * PIN1 must be Input, otherwise there is a glitch on the
0593      * rx-INT line. It happens between setting the PIN as output
0594      * (in the first byte of the SPI transfer) and configuring the
0595      * PIN as interrupt (in the last byte of the SPI transfer).
0596      */
0597     val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
0598         MCP251XFD_REG_IOCON_TRIS0;
0599     return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
0600 }
0601 
0602 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
0603 {
0604     u32 val;
0605 
0606     if (!priv->rx_int)
0607         return 0;
0608 
0609     /* Configure GPIOs:
0610      * - PIN0: GPIO Input
0611      * - PIN1: GPIO Input
0612      */
0613     val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
0614         MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
0615     return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
0616 }
0617 
0618 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
0619 {
0620     struct mcp251xfd_ecc *ecc = &priv->ecc;
0621     void *ram;
0622     u32 val = 0;
0623     int err;
0624 
0625     ecc->ecc_stat = 0;
0626 
0627     if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
0628         val = MCP251XFD_REG_ECCCON_ECCEN;
0629 
0630     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
0631                  MCP251XFD_REG_ECCCON_ECCEN, val);
0632     if (err)
0633         return err;
0634 
0635     ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
0636     if (!ram)
0637         return -ENOMEM;
0638 
0639     err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
0640                    MCP251XFD_RAM_SIZE);
0641     kfree(ram);
0642 
0643     return err;
0644 }
0645 
0646 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
0647 {
0648     u8 mode;
0649 
0650     if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
0651         mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
0652     else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
0653         mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
0654     else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
0655         mode = MCP251XFD_REG_CON_MODE_MIXED;
0656     else
0657         mode = MCP251XFD_REG_CON_MODE_CAN2_0;
0658 
0659     return mode;
0660 }
0661 
0662 static int
0663 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
0664                  bool nowait)
0665 {
0666     u8 mode;
0667 
0668     mode = mcp251xfd_get_normal_mode(priv);
0669 
0670     return __mcp251xfd_chip_set_mode(priv, mode, nowait);
0671 }
0672 
0673 static inline int
0674 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
0675 {
0676     return __mcp251xfd_chip_set_normal_mode(priv, false);
0677 }
0678 
0679 static inline int
0680 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
0681 {
0682     return __mcp251xfd_chip_set_normal_mode(priv, true);
0683 }
0684 
0685 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
0686 {
0687     u32 val;
0688     int err;
0689 
0690     val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
0691     err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
0692     if (err)
0693         return err;
0694 
0695     val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
0696     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
0697     if (err)
0698         return err;
0699 
0700     val = MCP251XFD_REG_INT_CERRIE |
0701         MCP251XFD_REG_INT_SERRIE |
0702         MCP251XFD_REG_INT_RXOVIE |
0703         MCP251XFD_REG_INT_TXATIE |
0704         MCP251XFD_REG_INT_SPICRCIE |
0705         MCP251XFD_REG_INT_ECCIE |
0706         MCP251XFD_REG_INT_TEFIE |
0707         MCP251XFD_REG_INT_MODIE |
0708         MCP251XFD_REG_INT_RXIE;
0709 
0710     if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
0711         val |= MCP251XFD_REG_INT_IVMIE;
0712 
0713     return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
0714 }
0715 
0716 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
0717 {
0718     int err;
0719     u32 mask;
0720 
0721     err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
0722     if (err)
0723         return err;
0724 
0725     mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
0726     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
0727                  mask, 0x0);
0728     if (err)
0729         return err;
0730 
0731     return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
0732 }
0733 
0734 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
0735                 const enum can_state state)
0736 {
0737     priv->can.state = state;
0738 
0739     mcp251xfd_chip_interrupts_disable(priv);
0740     mcp251xfd_chip_rx_int_disable(priv);
0741     mcp251xfd_chip_sleep(priv);
0742 }
0743 
0744 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
0745 {
0746     int err;
0747 
0748     err = mcp251xfd_chip_softreset(priv);
0749     if (err)
0750         goto out_chip_stop;
0751 
0752     err = mcp251xfd_chip_clock_init(priv);
0753     if (err)
0754         goto out_chip_stop;
0755 
0756     err = mcp251xfd_chip_timestamp_init(priv);
0757     if (err)
0758         goto out_chip_stop;
0759 
0760     err = mcp251xfd_set_bittiming(priv);
0761     if (err)
0762         goto out_chip_stop;
0763 
0764     err = mcp251xfd_chip_rx_int_enable(priv);
0765     if (err)
0766         goto out_chip_stop;
0767 
0768     err = mcp251xfd_chip_ecc_init(priv);
0769     if (err)
0770         goto out_chip_stop;
0771 
0772     err = mcp251xfd_ring_init(priv);
0773     if (err)
0774         goto out_chip_stop;
0775 
0776     err = mcp251xfd_chip_fifo_init(priv);
0777     if (err)
0778         goto out_chip_stop;
0779 
0780     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0781 
0782     err = mcp251xfd_chip_set_normal_mode(priv);
0783     if (err)
0784         goto out_chip_stop;
0785 
0786     return 0;
0787 
0788  out_chip_stop:
0789     mcp251xfd_dump(priv);
0790     mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
0791 
0792     return err;
0793 }
0794 
0795 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
0796 {
0797     struct mcp251xfd_priv *priv = netdev_priv(ndev);
0798     int err;
0799 
0800     switch (mode) {
0801     case CAN_MODE_START:
0802         err = mcp251xfd_chip_start(priv);
0803         if (err)
0804             return err;
0805 
0806         err = mcp251xfd_chip_interrupts_enable(priv);
0807         if (err) {
0808             mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
0809             return err;
0810         }
0811 
0812         netif_wake_queue(ndev);
0813         break;
0814 
0815     default:
0816         return -EOPNOTSUPP;
0817     }
0818 
0819     return 0;
0820 }
0821 
0822 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
0823                     struct can_berr_counter *bec)
0824 {
0825     const struct mcp251xfd_priv *priv = netdev_priv(ndev);
0826     u32 trec;
0827     int err;
0828 
0829     err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
0830     if (err)
0831         return err;
0832 
0833     if (trec & MCP251XFD_REG_TREC_TXBO)
0834         bec->txerr = 256;
0835     else
0836         bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
0837     bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
0838 
0839     return 0;
0840 }
0841 
0842 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
0843                       struct can_berr_counter *bec)
0844 {
0845     const struct mcp251xfd_priv *priv = netdev_priv(ndev);
0846 
0847     /* Avoid waking up the controller if the interface is down */
0848     if (!(ndev->flags & IFF_UP))
0849         return 0;
0850 
0851     /* The controller is powered down during Bus Off, use saved
0852      * bec values.
0853      */
0854     if (priv->can.state == CAN_STATE_BUS_OFF) {
0855         *bec = priv->bec;
0856         return 0;
0857     }
0858 
0859     return __mcp251xfd_get_berr_counter(ndev, bec);
0860 }
0861 
0862 static struct sk_buff *
0863 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
0864                 struct can_frame **cf, u32 *timestamp)
0865 {
0866     struct sk_buff *skb;
0867     int err;
0868 
0869     err = mcp251xfd_get_timestamp(priv, timestamp);
0870     if (err)
0871         return NULL;
0872 
0873     skb = alloc_can_err_skb(priv->ndev, cf);
0874     if (skb)
0875         mcp251xfd_skb_set_timestamp(priv, skb, *timestamp);
0876 
0877     return skb;
0878 }
0879 
0880 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
0881 {
0882     struct net_device_stats *stats = &priv->ndev->stats;
0883     struct mcp251xfd_rx_ring *ring;
0884     struct sk_buff *skb;
0885     struct can_frame *cf;
0886     u32 timestamp, rxovif;
0887     int err, i;
0888 
0889     stats->rx_over_errors++;
0890     stats->rx_errors++;
0891 
0892     err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
0893     if (err)
0894         return err;
0895 
0896     mcp251xfd_for_each_rx_ring(priv, ring, i) {
0897         if (!(rxovif & BIT(ring->fifo_nr)))
0898             continue;
0899 
0900         /* If SERRIF is active, there was a RX MAB overflow. */
0901         if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
0902             if (net_ratelimit())
0903                 netdev_dbg(priv->ndev,
0904                        "RX-%d: MAB overflow detected.\n",
0905                        ring->nr);
0906         } else {
0907             if (net_ratelimit())
0908                 netdev_dbg(priv->ndev,
0909                        "RX-%d: FIFO overflow.\n",
0910                        ring->nr);
0911         }
0912 
0913         err = regmap_update_bits(priv->map_reg,
0914                      MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
0915                      MCP251XFD_REG_FIFOSTA_RXOVIF,
0916                      0x0);
0917         if (err)
0918             return err;
0919     }
0920 
0921     skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &timestamp);
0922     if (!skb)
0923         return 0;
0924 
0925     cf->can_id |= CAN_ERR_CRTL;
0926     cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
0927 
0928     err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
0929     if (err)
0930         stats->rx_fifo_errors++;
0931 
0932     return 0;
0933 }
0934 
0935 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
0936 {
0937     netdev_info(priv->ndev, "%s\n", __func__);
0938 
0939     return 0;
0940 }
0941 
0942 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
0943 {
0944     struct net_device_stats *stats = &priv->ndev->stats;
0945     u32 bdiag1, timestamp;
0946     struct sk_buff *skb;
0947     struct can_frame *cf = NULL;
0948     int err;
0949 
0950     err = mcp251xfd_get_timestamp(priv, &timestamp);
0951     if (err)
0952         return err;
0953 
0954     err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
0955     if (err)
0956         return err;
0957 
0958     /* Write 0s to clear error bits, don't write 1s to non active
0959      * bits, as they will be set.
0960      */
0961     err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
0962     if (err)
0963         return err;
0964 
0965     priv->can.can_stats.bus_error++;
0966 
0967     skb = alloc_can_err_skb(priv->ndev, &cf);
0968     if (cf)
0969         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
0970 
0971     /* Controller misconfiguration */
0972     if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
0973         netdev_err(priv->ndev,
0974                "recv'd DLC is larger than PLSIZE of FIFO element.");
0975 
0976     /* RX errors */
0977     if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
0978               MCP251XFD_REG_BDIAG1_NCRCERR)) {
0979         netdev_dbg(priv->ndev, "CRC error\n");
0980 
0981         stats->rx_errors++;
0982         if (cf)
0983             cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
0984     }
0985     if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
0986               MCP251XFD_REG_BDIAG1_NSTUFERR)) {
0987         netdev_dbg(priv->ndev, "Stuff error\n");
0988 
0989         stats->rx_errors++;
0990         if (cf)
0991             cf->data[2] |= CAN_ERR_PROT_STUFF;
0992     }
0993     if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
0994               MCP251XFD_REG_BDIAG1_NFORMERR)) {
0995         netdev_dbg(priv->ndev, "Format error\n");
0996 
0997         stats->rx_errors++;
0998         if (cf)
0999             cf->data[2] |= CAN_ERR_PROT_FORM;
1000     }
1001 
1002     /* TX errors */
1003     if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1004         netdev_dbg(priv->ndev, "NACK error\n");
1005 
1006         stats->tx_errors++;
1007         if (cf) {
1008             cf->can_id |= CAN_ERR_ACK;
1009             cf->data[2] |= CAN_ERR_PROT_TX;
1010         }
1011     }
1012     if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1013               MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1014         netdev_dbg(priv->ndev, "Bit1 error\n");
1015 
1016         stats->tx_errors++;
1017         if (cf)
1018             cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1019     }
1020     if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1021               MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1022         netdev_dbg(priv->ndev, "Bit0 error\n");
1023 
1024         stats->tx_errors++;
1025         if (cf)
1026             cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1027     }
1028 
1029     if (!cf)
1030         return 0;
1031 
1032     mcp251xfd_skb_set_timestamp(priv, skb, timestamp);
1033     err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1034     if (err)
1035         stats->rx_fifo_errors++;
1036 
1037     return 0;
1038 }
1039 
1040 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1041 {
1042     struct net_device_stats *stats = &priv->ndev->stats;
1043     struct sk_buff *skb;
1044     struct can_frame *cf = NULL;
1045     enum can_state new_state, rx_state, tx_state;
1046     u32 trec, timestamp;
1047     int err;
1048 
1049     err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1050     if (err)
1051         return err;
1052 
1053     if (trec & MCP251XFD_REG_TREC_TXBO)
1054         tx_state = CAN_STATE_BUS_OFF;
1055     else if (trec & MCP251XFD_REG_TREC_TXBP)
1056         tx_state = CAN_STATE_ERROR_PASSIVE;
1057     else if (trec & MCP251XFD_REG_TREC_TXWARN)
1058         tx_state = CAN_STATE_ERROR_WARNING;
1059     else
1060         tx_state = CAN_STATE_ERROR_ACTIVE;
1061 
1062     if (trec & MCP251XFD_REG_TREC_RXBP)
1063         rx_state = CAN_STATE_ERROR_PASSIVE;
1064     else if (trec & MCP251XFD_REG_TREC_RXWARN)
1065         rx_state = CAN_STATE_ERROR_WARNING;
1066     else
1067         rx_state = CAN_STATE_ERROR_ACTIVE;
1068 
1069     new_state = max(tx_state, rx_state);
1070     if (new_state == priv->can.state)
1071         return 0;
1072 
1073     /* The skb allocation might fail, but can_change_state()
1074      * handles cf == NULL.
1075      */
1076     skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &timestamp);
1077     can_change_state(priv->ndev, cf, tx_state, rx_state);
1078 
1079     if (new_state == CAN_STATE_BUS_OFF) {
1080         /* As we're going to switch off the chip now, let's
1081          * save the error counters and return them to
1082          * userspace, if do_get_berr_counter() is called while
1083          * the chip is in Bus Off.
1084          */
1085         err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1086         if (err)
1087             return err;
1088 
1089         mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1090         can_bus_off(priv->ndev);
1091     }
1092 
1093     if (!skb)
1094         return 0;
1095 
1096     if (new_state != CAN_STATE_BUS_OFF) {
1097         struct can_berr_counter bec;
1098 
1099         err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1100         if (err)
1101             return err;
1102         cf->can_id |= CAN_ERR_CNT;
1103         cf->data[6] = bec.txerr;
1104         cf->data[7] = bec.rxerr;
1105     }
1106 
1107     err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1108     if (err)
1109         stats->rx_fifo_errors++;
1110 
1111     return 0;
1112 }
1113 
1114 static int
1115 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1116 {
1117     const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1118     u8 mode;
1119     int err;
1120 
1121     err = mcp251xfd_chip_get_mode(priv, &mode);
1122     if (err)
1123         return err;
1124 
1125     if (mode == mode_reference) {
1126         netdev_dbg(priv->ndev,
1127                "Controller changed into %s Mode (%u).\n",
1128                mcp251xfd_get_mode_str(mode), mode);
1129         return 0;
1130     }
1131 
1132     /* According to MCP2517FD errata DS80000792B 1., during a TX
1133      * MAB underflow, the controller will transition to Restricted
1134      * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1135      *
1136      * However this is not always the case. If SERR2LOM is
1137      * configured for Restricted Operation Mode (SERR2LOM not set)
1138      * the MCP2517FD will sometimes transition to Listen Only Mode
1139      * first. When polling this bit we see that it will transition
1140      * to Restricted Operation Mode shortly after.
1141      */
1142     if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1143         (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1144          mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1145         netdev_dbg(priv->ndev,
1146                "Controller changed into %s Mode (%u).\n",
1147                mcp251xfd_get_mode_str(mode), mode);
1148     else
1149         netdev_err(priv->ndev,
1150                "Controller changed into %s Mode (%u).\n",
1151                mcp251xfd_get_mode_str(mode), mode);
1152 
1153     /* After the application requests Normal mode, the controller
1154      * will automatically attempt to retransmit the message that
1155      * caused the TX MAB underflow.
1156      *
1157      * However, if there is an ECC error in the TX-RAM, we first
1158      * have to reload the tx-object before requesting Normal
1159      * mode. This is done later in mcp251xfd_handle_eccif().
1160      */
1161     if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1162         *set_normal_mode = true;
1163         return 0;
1164     }
1165 
1166     return mcp251xfd_chip_set_normal_mode_nowait(priv);
1167 }
1168 
1169 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1170 {
1171     struct mcp251xfd_ecc *ecc = &priv->ecc;
1172     struct net_device_stats *stats = &priv->ndev->stats;
1173     bool handled = false;
1174 
1175     /* TX MAB underflow
1176      *
1177      * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1178      * underflow is indicated by SERRIF and MODIF.
1179      *
1180      * In addition to the effects mentioned in the Errata, there
1181      * are Bus Errors due to the aborted CAN frame, so a IVMIF
1182      * will be seen as well.
1183      *
1184      * Sometimes there is an ECC error in the TX-RAM, which leads
1185      * to a TX MAB underflow.
1186      *
1187      * However, probably due to a race condition, there is no
1188      * associated MODIF pending.
1189      *
1190      * Further, there are situations, where the SERRIF is caused
1191      * by an ECC error in the TX-RAM, but not even the ECCIF is
1192      * set. This only seems to happen _after_ the first occurrence
1193      * of a ECCIF (which is tracked in ecc->cnt).
1194      *
1195      * Treat all as a known system errors..
1196      */
1197     if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1198          priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1199         priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1200         ecc->cnt) {
1201         const char *msg;
1202 
1203         if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1204             ecc->cnt)
1205             msg = "TX MAB underflow due to ECC error detected.";
1206         else
1207             msg = "TX MAB underflow detected.";
1208 
1209         if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1210             netdev_dbg(priv->ndev, "%s\n", msg);
1211         else
1212             netdev_info(priv->ndev, "%s\n", msg);
1213 
1214         stats->tx_aborted_errors++;
1215         stats->tx_errors++;
1216         handled = true;
1217     }
1218 
1219     /* RX MAB overflow
1220      *
1221      * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1222      * overflow is indicated by SERRIF.
1223      *
1224      * In addition to the effects mentioned in the Errata, (most
1225      * of the times) a RXOVIF is raised, if the FIFO that is being
1226      * received into has the RXOVIE activated (and we have enabled
1227      * RXOVIE on all FIFOs).
1228      *
1229      * Sometimes there is no RXOVIF just a RXIF is pending.
1230      *
1231      * Treat all as a known system errors..
1232      */
1233     if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1234         priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1235         stats->rx_dropped++;
1236         handled = true;
1237     }
1238 
1239     if (!handled)
1240         netdev_err(priv->ndev,
1241                "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1242                priv->regs_status.intf);
1243 
1244     return 0;
1245 }
1246 
1247 static int
1248 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1249 {
1250     struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1251     struct mcp251xfd_ecc *ecc = &priv->ecc;
1252     struct mcp251xfd_tx_obj *tx_obj;
1253     u8 chip_tx_tail, tx_tail, offset;
1254     u16 addr;
1255     int err;
1256 
1257     addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1258 
1259     err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1260     if (err)
1261         return err;
1262 
1263     tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1264     offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1265 
1266     /* Bail out if one of the following is met:
1267      * - tx_tail information is inconsistent
1268      * - for mcp2517fd: offset not 0
1269      * - for mcp2518fd: offset not 0 or 1
1270      */
1271     if (chip_tx_tail != tx_tail ||
1272         !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1273                           mcp251xfd_is_251863(priv))))) {
1274         netdev_err(priv->ndev,
1275                "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1276                addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1277                offset);
1278         return -EINVAL;
1279     }
1280 
1281     netdev_info(priv->ndev,
1282             "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1283             ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1284             "Single" : "Double",
1285             addr, nr, tx_ring->tail, tx_tail, offset);
1286 
1287     /* reload tx_obj into controller RAM ... */
1288     tx_obj = &tx_ring->obj[nr];
1289     err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1290     if (err)
1291         return err;
1292 
1293     /* ... and trigger retransmit */
1294     return mcp251xfd_chip_set_normal_mode(priv);
1295 }
1296 
1297 static int
1298 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1299 {
1300     struct mcp251xfd_ecc *ecc = &priv->ecc;
1301     const char *msg;
1302     bool in_tx_ram;
1303     u32 ecc_stat;
1304     u16 addr;
1305     u8 nr;
1306     int err;
1307 
1308     err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1309     if (err)
1310         return err;
1311 
1312     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1313                  MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1314     if (err)
1315         return err;
1316 
1317     /* Check if ECC error occurred in TX-RAM */
1318     addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1319     err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1320     if (!err)
1321         in_tx_ram = true;
1322     else if (err == -ENOENT)
1323         in_tx_ram = false;
1324     else
1325         return err;
1326 
1327     /* Errata Reference:
1328      * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1329      *
1330      * ECC single error correction does not work in all cases:
1331      *
1332      * Fix/Work Around:
1333      * Enable single error correction and double error detection
1334      * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1335      * detection interrupt and do not rely on the error
1336      * correction. Instead, handle both interrupts as a
1337      * notification that the RAM word at ERRADDR was corrupted.
1338      */
1339     if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1340         msg = "Single ECC Error detected at address";
1341     else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1342         msg = "Double ECC Error detected at address";
1343     else
1344         return -EINVAL;
1345 
1346     if (!in_tx_ram) {
1347         ecc->ecc_stat = 0;
1348 
1349         netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1350     } else {
1351         /* Re-occurring error? */
1352         if (ecc->ecc_stat == ecc_stat) {
1353             ecc->cnt++;
1354         } else {
1355             ecc->ecc_stat = ecc_stat;
1356             ecc->cnt = 1;
1357         }
1358 
1359         netdev_info(priv->ndev,
1360                 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1361                 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1362 
1363         if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1364             return mcp251xfd_handle_eccif_recover(priv, nr);
1365     }
1366 
1367     if (set_normal_mode)
1368         return mcp251xfd_chip_set_normal_mode_nowait(priv);
1369 
1370     return 0;
1371 }
1372 
1373 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1374 {
1375     int err;
1376     u32 crc;
1377 
1378     err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1379     if (err)
1380         return err;
1381 
1382     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1383                  MCP251XFD_REG_CRC_IF_MASK,
1384                  ~crc);
1385     if (err)
1386         return err;
1387 
1388     if (crc & MCP251XFD_REG_CRC_FERRIF)
1389         netdev_notice(priv->ndev, "CRC write command format error.\n");
1390     else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1391         netdev_notice(priv->ndev,
1392                   "CRC write error detected. CRC=0x%04lx.\n",
1393                   FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1394 
1395     return 0;
1396 }
1397 
1398 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1399 {
1400     const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1401     size_t len;
1402 
1403     if (priv->rx_ring_num == 1)
1404         len = sizeof(priv->regs_status.intf);
1405     else
1406         len = sizeof(priv->regs_status);
1407 
1408     return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1409                 &priv->regs_status, len / val_bytes);
1410 }
1411 
1412 #define mcp251xfd_handle(priv, irq, ...) \
1413 ({ \
1414     struct mcp251xfd_priv *_priv = (priv); \
1415     int err; \
1416 \
1417     err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1418     if (err) \
1419         netdev_err(_priv->ndev, \
1420             "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1421             __stringify(irq), err); \
1422     err; \
1423 })
1424 
1425 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1426 {
1427     struct mcp251xfd_priv *priv = dev_id;
1428     irqreturn_t handled = IRQ_NONE;
1429     int err;
1430 
1431     if (priv->rx_int)
1432         do {
1433             int rx_pending;
1434 
1435             rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1436             if (!rx_pending)
1437                 break;
1438 
1439             /* Assume 1st RX-FIFO pending, if other FIFOs
1440              * are pending the main IRQ handler will take
1441              * care.
1442              */
1443             priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1444             err = mcp251xfd_handle(priv, rxif);
1445             if (err)
1446                 goto out_fail;
1447 
1448             handled = IRQ_HANDLED;
1449 
1450             /* We don't know which RX-FIFO is pending, but only
1451              * handle the 1st RX-FIFO. Leave loop here if we have
1452              * more than 1 RX-FIFO to avoid starvation.
1453              */
1454         } while (priv->rx_ring_num == 1);
1455 
1456     do {
1457         u32 intf_pending, intf_pending_clearable;
1458         bool set_normal_mode = false;
1459 
1460         err = mcp251xfd_read_regs_status(priv);
1461         if (err)
1462             goto out_fail;
1463 
1464         intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1465                      priv->regs_status.intf) &
1466             FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1467                   priv->regs_status.intf);
1468 
1469         if (!(intf_pending)) {
1470             can_rx_offload_threaded_irq_finish(&priv->offload);
1471             return handled;
1472         }
1473 
1474         /* Some interrupts must be ACKed in the
1475          * MCP251XFD_REG_INT register.
1476          * - First ACK then handle, to avoid lost-IRQ race
1477          *   condition on fast re-occurring interrupts.
1478          * - Write "0" to clear active IRQs, "1" to all other,
1479          *   to avoid r/m/w race condition on the
1480          *   MCP251XFD_REG_INT register.
1481          */
1482         intf_pending_clearable = intf_pending &
1483             MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1484         if (intf_pending_clearable) {
1485             err = regmap_update_bits(priv->map_reg,
1486                          MCP251XFD_REG_INT,
1487                          MCP251XFD_REG_INT_IF_MASK,
1488                          ~intf_pending_clearable);
1489             if (err)
1490                 goto out_fail;
1491         }
1492 
1493         if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1494             err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1495             if (err)
1496                 goto out_fail;
1497         }
1498 
1499         if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1500             err = mcp251xfd_handle(priv, rxif);
1501             if (err)
1502                 goto out_fail;
1503         }
1504 
1505         if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1506             err = mcp251xfd_handle(priv, tefif);
1507             if (err)
1508                 goto out_fail;
1509         }
1510 
1511         if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1512             err = mcp251xfd_handle(priv, rxovif);
1513             if (err)
1514                 goto out_fail;
1515         }
1516 
1517         if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1518             err = mcp251xfd_handle(priv, txatif);
1519             if (err)
1520                 goto out_fail;
1521         }
1522 
1523         if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1524             err = mcp251xfd_handle(priv, ivmif);
1525             if (err)
1526                 goto out_fail;
1527         }
1528 
1529         if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1530             err = mcp251xfd_handle(priv, serrif);
1531             if (err)
1532                 goto out_fail;
1533         }
1534 
1535         if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1536             err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1537             if (err)
1538                 goto out_fail;
1539         }
1540 
1541         if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1542             err = mcp251xfd_handle(priv, spicrcif);
1543             if (err)
1544                 goto out_fail;
1545         }
1546 
1547         /* On the MCP2527FD and MCP2518FD, we don't get a
1548          * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1549          * ERROR_ACTIVE.
1550          */
1551         if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1552             priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1553             err = mcp251xfd_handle(priv, cerrif);
1554             if (err)
1555                 goto out_fail;
1556 
1557             /* In Bus Off we completely shut down the
1558              * controller. Every subsequent register read
1559              * will read bogus data, and if
1560              * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1561              * check will fail, too. So leave IRQ handler
1562              * directly.
1563              */
1564             if (priv->can.state == CAN_STATE_BUS_OFF) {
1565                 can_rx_offload_threaded_irq_finish(&priv->offload);
1566                 return IRQ_HANDLED;
1567             }
1568         }
1569 
1570         handled = IRQ_HANDLED;
1571     } while (1);
1572 
1573  out_fail:
1574     can_rx_offload_threaded_irq_finish(&priv->offload);
1575 
1576     netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1577            err, priv->regs_status.intf);
1578     mcp251xfd_dump(priv);
1579     mcp251xfd_chip_interrupts_disable(priv);
1580     mcp251xfd_timestamp_stop(priv);
1581 
1582     return handled;
1583 }
1584 
1585 static int mcp251xfd_open(struct net_device *ndev)
1586 {
1587     struct mcp251xfd_priv *priv = netdev_priv(ndev);
1588     const struct spi_device *spi = priv->spi;
1589     int err;
1590 
1591     err = open_candev(ndev);
1592     if (err)
1593         return err;
1594 
1595     err = pm_runtime_resume_and_get(ndev->dev.parent);
1596     if (err)
1597         goto out_close_candev;
1598 
1599     err = mcp251xfd_ring_alloc(priv);
1600     if (err)
1601         goto out_pm_runtime_put;
1602 
1603     err = mcp251xfd_transceiver_enable(priv);
1604     if (err)
1605         goto out_mcp251xfd_ring_free;
1606 
1607     err = mcp251xfd_chip_start(priv);
1608     if (err)
1609         goto out_transceiver_disable;
1610 
1611     mcp251xfd_timestamp_init(priv);
1612     clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1613     can_rx_offload_enable(&priv->offload);
1614 
1615     err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1616                    IRQF_SHARED | IRQF_ONESHOT,
1617                    dev_name(&spi->dev), priv);
1618     if (err)
1619         goto out_can_rx_offload_disable;
1620 
1621     err = mcp251xfd_chip_interrupts_enable(priv);
1622     if (err)
1623         goto out_free_irq;
1624 
1625     netif_start_queue(ndev);
1626 
1627     return 0;
1628 
1629  out_free_irq:
1630     free_irq(spi->irq, priv);
1631  out_can_rx_offload_disable:
1632     can_rx_offload_disable(&priv->offload);
1633     set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1634     mcp251xfd_timestamp_stop(priv);
1635  out_transceiver_disable:
1636     mcp251xfd_transceiver_disable(priv);
1637  out_mcp251xfd_ring_free:
1638     mcp251xfd_ring_free(priv);
1639  out_pm_runtime_put:
1640     mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1641     pm_runtime_put(ndev->dev.parent);
1642  out_close_candev:
1643     close_candev(ndev);
1644 
1645     return err;
1646 }
1647 
1648 static int mcp251xfd_stop(struct net_device *ndev)
1649 {
1650     struct mcp251xfd_priv *priv = netdev_priv(ndev);
1651 
1652     netif_stop_queue(ndev);
1653     set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1654     hrtimer_cancel(&priv->rx_irq_timer);
1655     hrtimer_cancel(&priv->tx_irq_timer);
1656     mcp251xfd_chip_interrupts_disable(priv);
1657     free_irq(ndev->irq, priv);
1658     can_rx_offload_disable(&priv->offload);
1659     mcp251xfd_timestamp_stop(priv);
1660     mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1661     mcp251xfd_transceiver_disable(priv);
1662     mcp251xfd_ring_free(priv);
1663     close_candev(ndev);
1664 
1665     pm_runtime_put(ndev->dev.parent);
1666 
1667     return 0;
1668 }
1669 
1670 static const struct net_device_ops mcp251xfd_netdev_ops = {
1671     .ndo_open = mcp251xfd_open,
1672     .ndo_stop = mcp251xfd_stop,
1673     .ndo_start_xmit = mcp251xfd_start_xmit,
1674     .ndo_eth_ioctl = can_eth_ioctl_hwts,
1675     .ndo_change_mtu = can_change_mtu,
1676 };
1677 
1678 static void
1679 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1680 {
1681     const struct spi_device *spi = priv->spi;
1682     const struct spi_controller *ctlr = spi->controller;
1683 
1684     if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1685         priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1686 }
1687 
1688 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1689 {
1690     const struct net_device *ndev = priv->ndev;
1691     const struct mcp251xfd_devtype_data *devtype_data;
1692     u32 osc;
1693     int err;
1694 
1695     /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1696      * so use it to autodetect the model.
1697      */
1698     err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1699                  MCP251XFD_REG_OSC_LPMEN,
1700                  MCP251XFD_REG_OSC_LPMEN);
1701     if (err)
1702         return err;
1703 
1704     err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1705     if (err)
1706         return err;
1707 
1708     if (osc & MCP251XFD_REG_OSC_LPMEN) {
1709         /* We cannot distinguish between MCP2518FD and
1710          * MCP251863. If firmware specifies MCP251863, keep
1711          * it, otherwise set to MCP2518FD.
1712          */
1713         if (mcp251xfd_is_251863(priv))
1714             devtype_data = &mcp251xfd_devtype_data_mcp251863;
1715         else
1716             devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1717     } else {
1718         devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1719     }
1720 
1721     if (!mcp251xfd_is_251XFD(priv) &&
1722         priv->devtype_data.model != devtype_data->model) {
1723         netdev_info(ndev,
1724                 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1725                 __mcp251xfd_get_model_str(devtype_data->model),
1726                 mcp251xfd_get_model_str(priv));
1727     }
1728     priv->devtype_data = *devtype_data;
1729 
1730     /* We need to preserve the Half Duplex Quirk. */
1731     mcp251xfd_register_quirks(priv);
1732 
1733     /* Re-init regmap with quirks of detected model. */
1734     return mcp251xfd_regmap_init(priv);
1735 }
1736 
1737 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1738 {
1739     int err, rx_pending;
1740 
1741     if (!priv->rx_int)
1742         return 0;
1743 
1744     err = mcp251xfd_chip_rx_int_enable(priv);
1745     if (err)
1746         return err;
1747 
1748     /* Check if RX_INT is properly working. The RX_INT should not
1749      * be active after a softreset.
1750      */
1751     rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1752 
1753     err = mcp251xfd_chip_rx_int_disable(priv);
1754     if (err)
1755         return err;
1756 
1757     if (!rx_pending)
1758         return 0;
1759 
1760     netdev_info(priv->ndev,
1761             "RX_INT active after softreset, disabling RX_INT support.\n");
1762     devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1763     priv->rx_int = NULL;
1764 
1765     return 0;
1766 }
1767 
1768 static int
1769 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1770                   u32 *effective_speed_hz_slow,
1771                   u32 *effective_speed_hz_fast)
1772 {
1773     struct mcp251xfd_map_buf_nocrc *buf_rx;
1774     struct mcp251xfd_map_buf_nocrc *buf_tx;
1775     struct spi_transfer xfer[2] = { };
1776     int err;
1777 
1778     buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1779     if (!buf_rx)
1780         return -ENOMEM;
1781 
1782     buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1783     if (!buf_tx) {
1784         err = -ENOMEM;
1785         goto out_kfree_buf_rx;
1786     }
1787 
1788     xfer[0].tx_buf = buf_tx;
1789     xfer[0].len = sizeof(buf_tx->cmd);
1790     xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1791     xfer[1].rx_buf = buf_rx->data;
1792     xfer[1].len = sizeof(*dev_id);
1793     xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1794 
1795     mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1796 
1797     err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1798     if (err)
1799         goto out_kfree_buf_tx;
1800 
1801     *dev_id = get_unaligned_le32(buf_rx->data);
1802     *effective_speed_hz_slow = xfer[0].effective_speed_hz;
1803     *effective_speed_hz_fast = xfer[1].effective_speed_hz;
1804 
1805  out_kfree_buf_tx:
1806     kfree(buf_tx);
1807  out_kfree_buf_rx:
1808     kfree(buf_rx);
1809 
1810     return err;
1811 }
1812 
1813 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
1814     (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1815 
1816 static int
1817 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1818 {
1819     u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1820     unsigned long clk_rate;
1821     int err;
1822 
1823     err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1824                         &effective_speed_hz_slow,
1825                         &effective_speed_hz_fast);
1826     if (err)
1827         return err;
1828 
1829     clk_rate = clk_get_rate(priv->clk);
1830 
1831     netdev_info(priv->ndev,
1832             "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1833             mcp251xfd_get_model_str(priv),
1834             FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1835             FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1836             priv->rx_int ? '+' : '-',
1837             priv->pll_enable ? '+' : '-',
1838             MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1839             MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1840             MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1841             MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1842             MCP251XFD_QUIRK_ACTIVE(ECC),
1843             MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1844             clk_rate / 1000000,
1845             clk_rate % 1000000 / 1000 / 10,
1846             priv->can.clock.freq / 1000000,
1847             priv->can.clock.freq % 1000000 / 1000 / 10,
1848             priv->spi_max_speed_hz_orig / 1000000,
1849             priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1850             priv->spi_max_speed_hz_slow / 1000000,
1851             priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1852             effective_speed_hz_slow / 1000000,
1853             effective_speed_hz_slow % 1000000 / 1000 / 10,
1854             priv->spi_max_speed_hz_fast / 1000000,
1855             priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1856             effective_speed_hz_fast / 1000000,
1857             effective_speed_hz_fast % 1000000 / 1000 / 10);
1858 
1859     return 0;
1860 }
1861 
1862 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1863 {
1864     struct net_device *ndev = priv->ndev;
1865     int err;
1866 
1867     err = mcp251xfd_clks_and_vdd_enable(priv);
1868     if (err)
1869         return err;
1870 
1871     pm_runtime_get_noresume(ndev->dev.parent);
1872     err = pm_runtime_set_active(ndev->dev.parent);
1873     if (err)
1874         goto out_runtime_put_noidle;
1875     pm_runtime_enable(ndev->dev.parent);
1876 
1877     mcp251xfd_register_quirks(priv);
1878 
1879     err = mcp251xfd_chip_softreset(priv);
1880     if (err == -ENODEV)
1881         goto out_runtime_disable;
1882     if (err)
1883         goto out_chip_sleep;
1884 
1885     err = mcp251xfd_chip_clock_init(priv);
1886     if (err == -ENODEV)
1887         goto out_runtime_disable;
1888     if (err)
1889         goto out_chip_sleep;
1890 
1891     err = mcp251xfd_register_chip_detect(priv);
1892     if (err)
1893         goto out_chip_sleep;
1894 
1895     err = mcp251xfd_register_check_rx_int(priv);
1896     if (err)
1897         goto out_chip_sleep;
1898 
1899     mcp251xfd_ethtool_init(priv);
1900 
1901     err = register_candev(ndev);
1902     if (err)
1903         goto out_chip_sleep;
1904 
1905     err = mcp251xfd_register_done(priv);
1906     if (err)
1907         goto out_unregister_candev;
1908 
1909     /* Put controller into sleep mode and let pm_runtime_put()
1910      * disable the clocks and vdd. If CONFIG_PM is not enabled,
1911      * the clocks and vdd will stay powered.
1912      */
1913     err = mcp251xfd_chip_sleep(priv);
1914     if (err)
1915         goto out_unregister_candev;
1916 
1917     pm_runtime_put(ndev->dev.parent);
1918 
1919     return 0;
1920 
1921  out_unregister_candev:
1922     unregister_candev(ndev);
1923  out_chip_sleep:
1924     mcp251xfd_chip_sleep(priv);
1925  out_runtime_disable:
1926     pm_runtime_disable(ndev->dev.parent);
1927  out_runtime_put_noidle:
1928     pm_runtime_put_noidle(ndev->dev.parent);
1929     mcp251xfd_clks_and_vdd_disable(priv);
1930 
1931     return err;
1932 }
1933 
1934 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1935 {
1936     struct net_device *ndev = priv->ndev;
1937 
1938     unregister_candev(ndev);
1939 
1940     if (pm_runtime_enabled(ndev->dev.parent))
1941         pm_runtime_disable(ndev->dev.parent);
1942     else
1943         mcp251xfd_clks_and_vdd_disable(priv);
1944 }
1945 
1946 static const struct of_device_id mcp251xfd_of_match[] = {
1947     {
1948         .compatible = "microchip,mcp2517fd",
1949         .data = &mcp251xfd_devtype_data_mcp2517fd,
1950     }, {
1951         .compatible = "microchip,mcp2518fd",
1952         .data = &mcp251xfd_devtype_data_mcp2518fd,
1953     }, {
1954         .compatible = "microchip,mcp251863",
1955         .data = &mcp251xfd_devtype_data_mcp251863,
1956     }, {
1957         .compatible = "microchip,mcp251xfd",
1958         .data = &mcp251xfd_devtype_data_mcp251xfd,
1959     }, {
1960         /* sentinel */
1961     },
1962 };
1963 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
1964 
1965 static const struct spi_device_id mcp251xfd_id_table[] = {
1966     {
1967         .name = "mcp2517fd",
1968         .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
1969     }, {
1970         .name = "mcp2518fd",
1971         .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
1972     }, {
1973         .name = "mcp251863",
1974         .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
1975     }, {
1976         .name = "mcp251xfd",
1977         .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
1978     }, {
1979         /* sentinel */
1980     },
1981 };
1982 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
1983 
1984 static int mcp251xfd_probe(struct spi_device *spi)
1985 {
1986     const void *match;
1987     struct net_device *ndev;
1988     struct mcp251xfd_priv *priv;
1989     struct gpio_desc *rx_int;
1990     struct regulator *reg_vdd, *reg_xceiver;
1991     struct clk *clk;
1992     bool pll_enable = false;
1993     u32 freq = 0;
1994     int err;
1995 
1996     if (!spi->irq)
1997         return dev_err_probe(&spi->dev, -ENXIO,
1998                      "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
1999 
2000     rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2001                      GPIOD_IN);
2002     if (IS_ERR(rx_int))
2003         return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2004                      "Failed to get RX-INT!\n");
2005 
2006     reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2007     if (PTR_ERR(reg_vdd) == -ENODEV)
2008         reg_vdd = NULL;
2009     else if (IS_ERR(reg_vdd))
2010         return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2011                      "Failed to get VDD regulator!\n");
2012 
2013     reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2014     if (PTR_ERR(reg_xceiver) == -ENODEV)
2015         reg_xceiver = NULL;
2016     else if (IS_ERR(reg_xceiver))
2017         return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2018                      "Failed to get Transceiver regulator!\n");
2019 
2020     clk = devm_clk_get_optional(&spi->dev, NULL);
2021     if (IS_ERR(clk))
2022         return dev_err_probe(&spi->dev, PTR_ERR(clk),
2023                      "Failed to get Oscillator (clock)!\n");
2024     if (clk) {
2025         freq = clk_get_rate(clk);
2026     } else {
2027         err = device_property_read_u32(&spi->dev, "clock-frequency",
2028                            &freq);
2029         if (err)
2030             return dev_err_probe(&spi->dev, err,
2031                          "Failed to get clock-frequency!\n");
2032     }
2033 
2034     /* Sanity check */
2035     if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2036         freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2037         dev_err(&spi->dev,
2038             "Oscillator frequency (%u Hz) is too low or high.\n",
2039             freq);
2040         return -ERANGE;
2041     }
2042 
2043     if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2044         pll_enable = true;
2045 
2046     ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2047                 MCP251XFD_TX_OBJ_NUM_MAX);
2048     if (!ndev)
2049         return -ENOMEM;
2050 
2051     SET_NETDEV_DEV(ndev, &spi->dev);
2052 
2053     ndev->netdev_ops = &mcp251xfd_netdev_ops;
2054     ndev->irq = spi->irq;
2055     ndev->flags |= IFF_ECHO;
2056 
2057     priv = netdev_priv(ndev);
2058     spi_set_drvdata(spi, priv);
2059     priv->can.clock.freq = freq;
2060     if (pll_enable)
2061         priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2062     priv->can.do_set_mode = mcp251xfd_set_mode;
2063     priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2064     priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2065     priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2066     priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2067         CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2068         CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2069         CAN_CTRLMODE_CC_LEN8_DLC;
2070     set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2071     priv->ndev = ndev;
2072     priv->spi = spi;
2073     priv->rx_int = rx_int;
2074     priv->clk = clk;
2075     priv->pll_enable = pll_enable;
2076     priv->reg_vdd = reg_vdd;
2077     priv->reg_xceiver = reg_xceiver;
2078 
2079     match = device_get_match_data(&spi->dev);
2080     if (match)
2081         priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2082     else
2083         priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2084             spi_get_device_id(spi)->driver_data;
2085 
2086     /* Errata Reference:
2087      * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4.
2088      *
2089      * The SPI can write corrupted data to the RAM at fast SPI
2090      * speeds:
2091      *
2092      * Simultaneous activity on the CAN bus while writing data to
2093      * RAM via the SPI interface, with high SCK frequency, can
2094      * lead to corrupted data being written to RAM.
2095      *
2096      * Fix/Work Around:
2097      * Ensure that FSCK is less than or equal to 0.85 *
2098      * (FSYSCLK/2).
2099      *
2100      * Known good combinations are:
2101      *
2102      * MCP  ext-clk SoC         SPI         SPI-clk     max-clk parent-clk  config
2103      *
2104      * 2518 20 MHz  allwinner,sun8i-h3  allwinner,sun8i-h3-spi   8333333 Hz  83.33% 600000000 Hz    assigned-clocks = <&ccu CLK_SPIx>
2105      * 2518 40 MHz  allwinner,sun8i-h3  allwinner,sun8i-h3-spi  16666667 Hz  83.33% 600000000 Hz    assigned-clocks = <&ccu CLK_SPIx>
2106      * 2517 40 MHz  atmel,sama5d27      atmel,at91rm9200-spi    16400000 Hz  82.00%  82000000 Hz    default
2107      * 2518 40 MHz  atmel,sama5d27      atmel,at91rm9200-spi    16400000 Hz  82.00%  82000000 Hz    default
2108      * 2518 40 MHz  fsl,imx6dl      fsl,imx51-ecspi     15000000 Hz  75.00%  30000000 Hz    default
2109      * 2517 20 MHz  fsl,imx8mm      fsl,imx51-ecspi      8333333 Hz  83.33%  16666667 Hz    assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2110      *
2111      */
2112     priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2113     priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2114                       freq / 2 / 1000 * 850);
2115     if (priv->pll_enable)
2116         priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2117                           freq *
2118                           MCP251XFD_OSC_PLL_MULTIPLIER /
2119                           2 / 1000 * 850);
2120     else
2121         priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2122     spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2123     spi->bits_per_word = 8;
2124     spi->rt = true;
2125     err = spi_setup(spi);
2126     if (err)
2127         goto out_free_candev;
2128 
2129     err = mcp251xfd_regmap_init(priv);
2130     if (err)
2131         goto out_free_candev;
2132 
2133     err = can_rx_offload_add_manual(ndev, &priv->offload,
2134                     MCP251XFD_NAPI_WEIGHT);
2135     if (err)
2136         goto out_free_candev;
2137 
2138     err = mcp251xfd_register(priv);
2139     if (err) {
2140         dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2141                   mcp251xfd_get_model_str(priv));
2142         goto out_can_rx_offload_del;
2143     }
2144 
2145     return 0;
2146 
2147  out_can_rx_offload_del:
2148     can_rx_offload_del(&priv->offload);
2149  out_free_candev:
2150     spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2151 
2152     free_candev(ndev);
2153 
2154     return err;
2155 }
2156 
2157 static void mcp251xfd_remove(struct spi_device *spi)
2158 {
2159     struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2160     struct net_device *ndev = priv->ndev;
2161 
2162     can_rx_offload_del(&priv->offload);
2163     mcp251xfd_unregister(priv);
2164     spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2165     free_candev(ndev);
2166 }
2167 
2168 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2169 {
2170     const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2171 
2172     return mcp251xfd_clks_and_vdd_disable(priv);
2173 }
2174 
2175 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2176 {
2177     const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2178 
2179     return mcp251xfd_clks_and_vdd_enable(priv);
2180 }
2181 
2182 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2183     SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2184                mcp251xfd_runtime_resume, NULL)
2185 };
2186 
2187 static struct spi_driver mcp251xfd_driver = {
2188     .driver = {
2189         .name = DEVICE_NAME,
2190         .pm = &mcp251xfd_pm_ops,
2191         .of_match_table = mcp251xfd_of_match,
2192     },
2193     .probe = mcp251xfd_probe,
2194     .remove = mcp251xfd_remove,
2195     .id_table = mcp251xfd_id_table,
2196 };
2197 module_spi_driver(mcp251xfd_driver);
2198 
2199 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2200 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2201 MODULE_LICENSE("GPL v2");
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