can/softing/softing.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * softing common interfaces
0004  *
0005  * by Kurt Van Dijck, 2008-2010
0006  */
0007
0008 #include <linux/atomic.h>
0009 #include <linux/netdevice.h>
0010 #include <linux/ktime.h>
0011 #include <linux/mutex.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/can.h>
0014 #include <linux/can/dev.h>
0015
0016 #include "softing_platform.h"
0017
0018 struct softing;
0019
0020 struct softing_priv {
0021     struct can_priv can; /* must be the first member! */
0022     struct net_device *netdev;
0023     struct softing *card;
0024     struct {
0025         int pending;
0026         /* variables which hold the circular buffer */
0027         int echo_put;
0028         int echo_get;
0029     } tx;
0030     struct can_bittiming_const btr_const;
0031     int index;
0032     uint8_t output;
0033     uint16_t chip;
0034 };
0035 #define netdev2softing(netdev)  ((struct softing_priv *)netdev_priv(netdev))
0036
0037 struct softing {
0038     const struct softing_platform_data *pdat;
0039     struct platform_device *pdev;
0040     struct net_device *net[2];
0041     spinlock_t spin; /* protect this structure & DPRAM access */
0042     ktime_t ts_ref;
0043     ktime_t ts_overflow; /* timestamp overflow value, in ktime */
0044
0045     struct {
0046         /* indication of firmware status */
0047         int up;
0048         /* protection of the 'up' variable */
0049         struct mutex lock;
0050     } fw;
0051     struct {
0052         int nr;
0053         int requested;
0054         int svc_count;
0055         unsigned int dpram_position;
0056     } irq;
0057     struct {
0058         int pending;
0059         int last_bus;
0060         /*
0061          * keep the bus that last tx'd a message,
0062          * in order to let every netdev queue resume
0063          */
0064     } tx;
0065     __iomem uint8_t *dpram;
0066     unsigned long dpram_phys;
0067     unsigned long dpram_size;
0068     struct {
0069         uint16_t fw_version, hw_version, license, serial;
0070         uint16_t chip[2];
0071         unsigned int freq; /* remote cpu's operating frequency */
0072     } id;
0073 };
0074
0075 int softing_default_output(struct net_device *netdev);
0076
0077 ktime_t softing_raw2ktime(struct softing *card, u32 raw);
0078
0079 int softing_chip_poweron(struct softing *card);
0080
0081 int softing_bootloader_command(struct softing *card, int16_t cmd,
0082                    const char *msg);
0083
0084 /* Load firmware after reset */
0085 int softing_load_fw(const char *file, struct softing *card,
0086             __iomem uint8_t *virt, unsigned int size, int offset);
0087
0088 /* Load final application firmware after bootloader */
0089 int softing_load_app_fw(const char *file, struct softing *card);
0090
0091 /*
0092  * enable or disable irq
0093  * only called with fw.lock locked
0094  */
0095 int softing_enable_irq(struct softing *card, int enable);
0096
0097 /* start/stop 1 bus on card */
0098 int softing_startstop(struct net_device *netdev, int up);
0099
0100 /* netif_rx() */
0101 int softing_netdev_rx(struct net_device *netdev, const struct can_frame *msg,
0102               ktime_t ktime);
0103
0104 /* SOFTING DPRAM mappings */
0105 #define DPRAM_RX        0x0000
0106     #define DPRAM_RX_SIZE   32
0107     #define DPRAM_RX_CNT    16
0108 #define DPRAM_RX_RD     0x0201  /* uint8_t */
0109 #define DPRAM_RX_WR     0x0205  /* uint8_t */
0110 #define DPRAM_RX_LOST       0x0207  /* uint8_t */
0111
0112 #define DPRAM_FCT_PARAM     0x0300  /* int16_t [20] */
0113 #define DPRAM_FCT_RESULT    0x0328  /* int16_t */
0114 #define DPRAM_FCT_HOST      0x032b  /* uint16_t */
0115
0116 #define DPRAM_INFO_BUSSTATE 0x0331  /* uint16_t */
0117 #define DPRAM_INFO_BUSSTATE2    0x0335  /* uint16_t */
0118 #define DPRAM_INFO_ERRSTATE 0x0339  /* uint16_t */
0119 #define DPRAM_INFO_ERRSTATE2    0x033d  /* uint16_t */
0120 #define DPRAM_RESET     0x0341  /* uint16_t */
0121 #define DPRAM_CLR_RECV_FIFO 0x0345  /* uint16_t */
0122 #define DPRAM_RESET_TIME    0x034d  /* uint16_t */
0123 #define DPRAM_TIME      0x0350  /* uint64_t */
0124 #define DPRAM_WR_START      0x0358  /* uint8_t */
0125 #define DPRAM_WR_END        0x0359  /* uint8_t */
0126 #define DPRAM_RESET_RX_FIFO 0x0361  /* uint16_t */
0127 #define DPRAM_RESET_TX_FIFO 0x0364  /* uint8_t */
0128 #define DPRAM_READ_FIFO_LEVEL   0x0365  /* uint8_t */
0129 #define DPRAM_RX_FIFO_LEVEL 0x0366  /* uint16_t */
0130 #define DPRAM_TX_FIFO_LEVEL 0x0366  /* uint16_t */
0131
0132 #define DPRAM_TX        0x0400  /* uint16_t */
0133     #define DPRAM_TX_SIZE   16
0134     #define DPRAM_TX_CNT    32
0135 #define DPRAM_TX_RD     0x0601  /* uint8_t */
0136 #define DPRAM_TX_WR     0x0605  /* uint8_t */
0137
0138 #define DPRAM_COMMAND       0x07e0  /* uint16_t */
0139 #define DPRAM_RECEIPT       0x07f0  /* uint16_t */
0140 #define DPRAM_IRQ_TOHOST    0x07fe  /* uint8_t */
0141 #define DPRAM_IRQ_TOCARD    0x07ff  /* uint8_t */
0142
0143 #define DPRAM_V2_RESET      0x0e00  /* uint8_t */
0144 #define DPRAM_V2_IRQ_TOHOST 0x0e02  /* uint8_t */
0145
0146 #define TXMAX   (DPRAM_TX_CNT - 1)
0147
0148 /* DPRAM return codes */
0149 #define RES_NONE    0
0150 #define RES_OK      1
0151 #define RES_NOK     2
0152 #define RES_UNKNOWN 3
0153 /* DPRAM flags */
0154 #define CMD_TX      0x01
0155 #define CMD_ACK     0x02
0156 #define CMD_XTD     0x04
0157 #define CMD_RTR     0x08
0158 #define CMD_ERR     0x10
0159 #define CMD_BUS2    0x80
0160
0161 /* returned fifo entry bus state masks */
0162 #define SF_MASK_BUSOFF      0x80
0163 #define SF_MASK_EPASSIVE    0x60
0164
0165 /* bus states */
0166 #define STATE_BUSOFF    2
0167 #define STATE_EPASSIVE  1
0168 #define STATE_EACTIVE   0