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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
0004  *
0005  * Derived from the ems_pci.c driver:
0006  *  Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
0007  *  Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
0008  *  Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/delay.h>
0016 #include <linux/slab.h>
0017 #include <linux/pci.h>
0018 #include <linux/can/dev.h>
0019 #include <linux/io.h>
0020 
0021 #include "sja1000.h"
0022 
0023 #define DRV_NAME  "sja1000_plx_pci"
0024 
0025 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
0026 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
0027            "the SJA1000 chips");
0028 MODULE_LICENSE("GPL v2");
0029 
0030 #define PLX_PCI_MAX_CHAN 2
0031 
0032 struct plx_pci_card {
0033     int channels;           /* detected channels count */
0034     struct net_device *net_dev[PLX_PCI_MAX_CHAN];
0035     void __iomem *conf_addr;
0036 
0037     /* Pointer to device-dependent reset function */
0038     void (*reset_func)(struct pci_dev *pdev);
0039 };
0040 
0041 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
0042 
0043 /* PLX9030/9050/9052 registers */
0044 #define PLX_INTCSR  0x4c        /* Interrupt Control/Status */
0045 #define PLX_CNTRL   0x50        /* User I/O, Direct Slave Response,
0046                      * Serial EEPROM, and Initialization
0047                      * Control register
0048                      */
0049 
0050 #define PLX_LINT1_EN    0x1     /* Local interrupt 1 enable */
0051 #define PLX_LINT1_POL   (1 << 1)    /* Local interrupt 1 polarity */
0052 #define PLX_LINT2_EN    (1 << 3)    /* Local interrupt 2 enable */
0053 #define PLX_LINT2_POL   (1 << 4)    /* Local interrupt 2 polarity */
0054 #define PLX_PCI_INT_EN  (1 << 6)    /* PCI Interrupt Enable */
0055 #define PLX_PCI_RESET   (1 << 30)   /* PCI Adapter Software Reset */
0056 
0057 /* PLX9056 registers */
0058 #define PLX9056_INTCSR  0x68        /* Interrupt Control/Status */
0059 #define PLX9056_CNTRL   0x6c        /* Control / Software Reset */
0060 
0061 #define PLX9056_LINTI   (1 << 11)
0062 #define PLX9056_PCI_INT_EN (1 << 8)
0063 #define PLX9056_PCI_RCR (1 << 29)   /* Read Configuration Registers */
0064 
0065 /*
0066  * The board configuration is probably following:
0067  * RX1 is connected to ground.
0068  * TX1 is not connected.
0069  * CLKO is not connected.
0070  * Setting the OCR register to 0xDA is a good idea.
0071  * This means normal output mode, push-pull and the correct polarity.
0072  */
0073 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
0074 
0075 /* OCR setting for ASEM Dual CAN raw */
0076 #define ASEM_PCI_OCR    0xfe
0077 
0078 /*
0079  * In the CDR register, you should set CBP to 1.
0080  * You will probably also want to set the clock divider value to 7
0081  * (meaning direct oscillator output) because the second SJA1000 chip
0082  * is driven by the first one CLKOUT output.
0083  */
0084 #define PLX_PCI_CDR         (CDR_CBP | CDR_CLKOUT_MASK)
0085 
0086 /* SJA1000 Control Register in the BasicCAN Mode */
0087 #define REG_CR              0x00
0088 
0089 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
0090 #define REG_CR_BASICCAN_INITIAL     0x21
0091 #define REG_CR_BASICCAN_INITIAL_MASK    0xa1
0092 #define REG_SR_BASICCAN_INITIAL     0x0c
0093 #define REG_IR_BASICCAN_INITIAL     0xe0
0094 
0095 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
0096 #define REG_MOD_PELICAN_INITIAL     0x01
0097 #define REG_SR_PELICAN_INITIAL      0x3c
0098 #define REG_IR_PELICAN_INITIAL      0x00
0099 
0100 #define ADLINK_PCI_VENDOR_ID        0x144A
0101 #define ADLINK_PCI_DEVICE_ID        0x7841
0102 
0103 #define ESD_PCI_SUB_SYS_ID_PCI200   0x0004
0104 #define ESD_PCI_SUB_SYS_ID_PCI266   0x0009
0105 #define ESD_PCI_SUB_SYS_ID_PMC266   0x000e
0106 #define ESD_PCI_SUB_SYS_ID_CPCI200  0x010b
0107 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200
0108 #define ESD_PCI_SUB_SYS_ID_PCI104200    0x0501
0109 
0110 #define CAN200PCI_DEVICE_ID     0x9030
0111 #define CAN200PCI_VENDOR_ID     0x10b5
0112 #define CAN200PCI_SUB_DEVICE_ID     0x0301
0113 #define CAN200PCI_SUB_VENDOR_ID     0xe1c5
0114 
0115 #define IXXAT_PCI_VENDOR_ID     0x10b5
0116 #define IXXAT_PCI_DEVICE_ID     0x9050
0117 #define IXXAT_PCI_SUB_SYS_ID        0x2540
0118 
0119 #define MARATHON_PCI_DEVICE_ID      0x2715
0120 #define MARATHON_PCIE_DEVICE_ID     0x3432
0121 
0122 #define TEWS_PCI_VENDOR_ID      0x1498
0123 #define TEWS_PCI_DEVICE_ID_TMPC810  0x032A
0124 
0125 #define CTI_PCI_VENDOR_ID       0x12c4
0126 #define CTI_PCI_DEVICE_ID_CRG001    0x0900
0127 
0128 #define MOXA_PCI_VENDOR_ID      0x1393
0129 #define MOXA_PCI_DEVICE_ID      0x0100
0130 
0131 #define ASEM_RAW_CAN_VENDOR_ID      0x10b5
0132 #define ASEM_RAW_CAN_DEVICE_ID      0x9030
0133 #define ASEM_RAW_CAN_SUB_VENDOR_ID  0x3000
0134 #define ASEM_RAW_CAN_SUB_DEVICE_ID  0x1001
0135 #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS  0x1002
0136 #define ASEM_RAW_CAN_RST_REGISTER   0x54
0137 #define ASEM_RAW_CAN_RST_MASK_CAN1  0x20
0138 #define ASEM_RAW_CAN_RST_MASK_CAN2  0x04
0139 
0140 static void plx_pci_reset_common(struct pci_dev *pdev);
0141 static void plx9056_pci_reset_common(struct pci_dev *pdev);
0142 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
0143 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
0144 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev);
0145 
0146 struct plx_pci_channel_map {
0147     u32 bar;
0148     u32 offset;
0149     u32 size;       /* 0x00 - auto, e.g. length of entire bar */
0150 };
0151 
0152 struct plx_pci_card_info {
0153     const char *name;
0154     int channel_count;
0155     u32 can_clock;
0156     u8 ocr;         /* output control register */
0157     u8 cdr;         /* clock divider register */
0158 
0159     /* Parameters for mapping local configuration space */
0160     struct plx_pci_channel_map conf_map;
0161 
0162     /* Parameters for mapping the SJA1000 chips */
0163     struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
0164 
0165     /* Pointer to device-dependent reset function */
0166     void (*reset_func)(struct pci_dev *pdev);
0167 };
0168 
0169 static struct plx_pci_card_info plx_pci_card_info_adlink = {
0170     "Adlink PCI-7841/cPCI-7841", 2,
0171     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0172     {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
0173     &plx_pci_reset_common
0174     /* based on PLX9052 */
0175 };
0176 
0177 static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
0178     "Adlink PCI-7841/cPCI-7841 SE", 2,
0179     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0180     {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
0181     &plx_pci_reset_common
0182     /* based on PLX9052 */
0183 };
0184 
0185 static struct plx_pci_card_info plx_pci_card_info_esd200 = {
0186     "esd CAN-PCI/CPCI/PCI104/200", 2,
0187     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0188     {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
0189     &plx_pci_reset_common
0190     /* based on PLX9030/9050 */
0191 };
0192 
0193 static struct plx_pci_card_info plx_pci_card_info_esd266 = {
0194     "esd CAN-PCI/PMC/266", 2,
0195     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0196     {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
0197     &plx9056_pci_reset_common
0198     /* based on PLX9056 */
0199 };
0200 
0201 static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
0202     "esd CAN-PCIe/2000", 2,
0203     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0204     {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
0205     &plx9056_pci_reset_common
0206     /* based on PEX8311 */
0207 };
0208 
0209 static struct plx_pci_card_info plx_pci_card_info_ixxat = {
0210     "IXXAT PC-I 04/PCI", 2,
0211     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0212     {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
0213     &plx_pci_reset_common
0214     /* based on PLX9050 */
0215 };
0216 
0217 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = {
0218     "Marathon CAN-bus-PCI", 2,
0219     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0220     {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
0221     &plx_pci_reset_marathon_pci
0222     /* based on PLX9052 */
0223 };
0224 
0225 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = {
0226     "Marathon CAN-bus-PCIe", 2,
0227     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0228     {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} },
0229     &plx_pci_reset_marathon_pcie
0230     /* based on PEX8311 */
0231 };
0232 
0233 static struct plx_pci_card_info plx_pci_card_info_tews = {
0234     "TEWS TECHNOLOGIES TPMC810", 2,
0235     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0236     {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
0237     &plx_pci_reset_common
0238     /* based on PLX9030 */
0239 };
0240 
0241 static struct plx_pci_card_info plx_pci_card_info_cti = {
0242     "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
0243     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0244     {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
0245     &plx_pci_reset_common
0246     /* based on PLX9030 */
0247 };
0248 
0249 static struct plx_pci_card_info plx_pci_card_info_elcus = {
0250     "Eclus CAN-200-PCI", 2,
0251     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0252     {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
0253     &plx_pci_reset_common
0254     /* based on PLX9030 */
0255 };
0256 
0257 static struct plx_pci_card_info plx_pci_card_info_moxa = {
0258     "MOXA", 2,
0259     PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
0260     {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} },
0261     &plx_pci_reset_common
0262      /* based on PLX9052 */
0263 };
0264 
0265 static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = {
0266     "ASEM Dual CAN raw PCI", 2,
0267     PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR,
0268     {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
0269     &plx_pci_reset_asem_dual_can_raw
0270     /* based on PLX9030 */
0271 };
0272 
0273 static const struct pci_device_id plx_pci_tbl[] = {
0274     {
0275         /* Adlink PCI-7841/cPCI-7841 */
0276         ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
0277         PCI_ANY_ID, PCI_ANY_ID,
0278         PCI_CLASS_NETWORK_OTHER << 8, ~0,
0279         (kernel_ulong_t)&plx_pci_card_info_adlink
0280     },
0281     {
0282         /* Adlink PCI-7841/cPCI-7841 SE */
0283         ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
0284         PCI_ANY_ID, PCI_ANY_ID,
0285         PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
0286         (kernel_ulong_t)&plx_pci_card_info_adlink_se
0287     },
0288     {
0289         /* esd CAN-PCI/200 */
0290         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
0291         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
0292         0, 0,
0293         (kernel_ulong_t)&plx_pci_card_info_esd200
0294     },
0295     {
0296         /* esd CAN-CPCI/200 */
0297         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
0298         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
0299         0, 0,
0300         (kernel_ulong_t)&plx_pci_card_info_esd200
0301     },
0302     {
0303         /* esd CAN-PCI104/200 */
0304         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
0305         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
0306         0, 0,
0307         (kernel_ulong_t)&plx_pci_card_info_esd200
0308     },
0309     {
0310         /* esd CAN-PCI/266 */
0311         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
0312         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
0313         0, 0,
0314         (kernel_ulong_t)&plx_pci_card_info_esd266
0315     },
0316     {
0317         /* esd CAN-PMC/266 */
0318         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
0319         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
0320         0, 0,
0321         (kernel_ulong_t)&plx_pci_card_info_esd266
0322     },
0323     {
0324         /* esd CAN-PCIE/2000 */
0325         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
0326         PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
0327         0, 0,
0328         (kernel_ulong_t)&plx_pci_card_info_esd2000
0329     },
0330     {
0331         /* IXXAT PC-I 04/PCI card */
0332         IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
0333         PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
0334         0, 0,
0335         (kernel_ulong_t)&plx_pci_card_info_ixxat
0336     },
0337     {
0338         /* Marathon CAN-bus-PCI card */
0339         PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
0340         PCI_ANY_ID, PCI_ANY_ID,
0341         0, 0,
0342         (kernel_ulong_t)&plx_pci_card_info_marathon_pci
0343     },
0344     {
0345         /* Marathon CAN-bus-PCIe card */
0346         PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID,
0347         PCI_ANY_ID, PCI_ANY_ID,
0348         0, 0,
0349         (kernel_ulong_t)&plx_pci_card_info_marathon_pcie
0350     },
0351     {
0352         /* TEWS TECHNOLOGIES TPMC810 card */
0353         TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
0354         PCI_ANY_ID, PCI_ANY_ID,
0355         0, 0,
0356         (kernel_ulong_t)&plx_pci_card_info_tews
0357     },
0358     {
0359         /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
0360         PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
0361         CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001,
0362         0, 0,
0363         (kernel_ulong_t)&plx_pci_card_info_cti
0364     },
0365     {
0366         /* Elcus CAN-200-PCI */
0367         CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID,
0368         CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID,
0369         0, 0,
0370         (kernel_ulong_t)&plx_pci_card_info_elcus
0371     },
0372     {
0373         /* moxa */
0374         MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID,
0375         PCI_ANY_ID, PCI_ANY_ID,
0376         0, 0,
0377         (kernel_ulong_t)&plx_pci_card_info_moxa
0378     },
0379     {
0380         /* ASEM Dual CAN raw */
0381         ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
0382         ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID,
0383         0, 0,
0384         (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
0385     },
0386     {
0387         /* ASEM Dual CAN raw -new model */
0388         ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
0389         ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS,
0390         0, 0,
0391         (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
0392     },
0393     { 0,}
0394 };
0395 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
0396 
0397 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
0398 {
0399     return ioread8(priv->reg_base + port);
0400 }
0401 
0402 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
0403 {
0404     iowrite8(val, priv->reg_base + port);
0405 }
0406 
0407 /*
0408  * Check if a CAN controller is present at the specified location
0409  * by trying to switch 'em from the Basic mode into the PeliCAN mode.
0410  * Also check states of some registers in reset mode.
0411  */
0412 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
0413 {
0414     int flag = 0;
0415 
0416     /*
0417      * Check registers after hardware reset (the Basic mode)
0418      * See states on p. 10 of the Datasheet.
0419      */
0420     if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
0421         REG_CR_BASICCAN_INITIAL &&
0422         (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
0423         (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
0424         flag = 1;
0425 
0426     /* Bring the SJA1000 into the PeliCAN mode*/
0427     priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
0428 
0429     /*
0430      * Check registers after reset in the PeliCAN mode.
0431      * See states on p. 23 of the Datasheet.
0432      */
0433     if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
0434         priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
0435         priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
0436         return flag;
0437 
0438     return 0;
0439 }
0440 
0441 /*
0442  * PLX9030/50/52 software reset
0443  * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
0444  * For most cards it's enough for reset the SJA1000 chips.
0445  */
0446 static void plx_pci_reset_common(struct pci_dev *pdev)
0447 {
0448     struct plx_pci_card *card = pci_get_drvdata(pdev);
0449     u32 cntrl;
0450 
0451     cntrl = ioread32(card->conf_addr + PLX_CNTRL);
0452     cntrl |= PLX_PCI_RESET;
0453     iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
0454     udelay(100);
0455     cntrl ^= PLX_PCI_RESET;
0456     iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
0457 };
0458 
0459 /*
0460  * PLX9056 software reset
0461  * Assert LRESET# and reset device(s) on the Local Bus (if wired).
0462  */
0463 static void plx9056_pci_reset_common(struct pci_dev *pdev)
0464 {
0465     struct plx_pci_card *card = pci_get_drvdata(pdev);
0466     u32 cntrl;
0467 
0468     /* issue a local bus reset */
0469     cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
0470     cntrl |= PLX_PCI_RESET;
0471     iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
0472     udelay(100);
0473     cntrl ^= PLX_PCI_RESET;
0474     iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
0475 
0476     /* reload local configuration from EEPROM */
0477     cntrl |= PLX9056_PCI_RCR;
0478     iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
0479 
0480     /*
0481      * There is no safe way to poll for the end
0482      * of reconfiguration process. Waiting for 10ms
0483      * is safe.
0484      */
0485     mdelay(10);
0486 
0487     cntrl ^= PLX9056_PCI_RCR;
0488     iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
0489 };
0490 
0491 /* Special reset function for Marathon CAN-bus-PCI card */
0492 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev)
0493 {
0494     void __iomem *reset_addr;
0495     int i;
0496     static const int reset_bar[2] = {3, 5};
0497 
0498     plx_pci_reset_common(pdev);
0499 
0500     for (i = 0; i < 2; i++) {
0501         reset_addr = pci_iomap(pdev, reset_bar[i], 0);
0502         if (!reset_addr) {
0503             dev_err(&pdev->dev, "Failed to remap reset "
0504                 "space %d (BAR%d)\n", i, reset_bar[i]);
0505         } else {
0506             /* reset the SJA1000 chip */
0507             iowrite8(0x1, reset_addr);
0508             udelay(100);
0509             pci_iounmap(pdev, reset_addr);
0510         }
0511     }
0512 }
0513 
0514 /* Special reset function for Marathon CAN-bus-PCIe card */
0515 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev)
0516 {
0517     void __iomem *addr;
0518     void __iomem *reset_addr;
0519     int i;
0520 
0521     plx9056_pci_reset_common(pdev);
0522 
0523     for (i = 0; i < 2; i++) {
0524         struct plx_pci_channel_map *chan_map =
0525             &plx_pci_card_info_marathon_pcie.chan_map_tbl[i];
0526         addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
0527         if (!addr) {
0528             dev_err(&pdev->dev, "Failed to remap reset "
0529                 "space %d (BAR%d)\n", i, chan_map->bar);
0530         } else {
0531             /* reset the SJA1000 chip */
0532             #define MARATHON_PCIE_RESET_OFFSET 32
0533             reset_addr = addr + chan_map->offset +
0534                          MARATHON_PCIE_RESET_OFFSET;
0535             iowrite8(0x1, reset_addr);
0536             udelay(100);
0537             pci_iounmap(pdev, addr);
0538         }
0539     }
0540 }
0541 
0542 /* Special reset function for ASEM Dual CAN raw card */
0543 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev)
0544 {
0545     void __iomem *bar0_addr;
0546     u8 tmpval;
0547 
0548     plx_pci_reset_common(pdev);
0549 
0550     bar0_addr = pci_iomap(pdev, 0, 0);
0551     if (!bar0_addr) {
0552         dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n");
0553         return;
0554     }
0555 
0556     /* reset the two SJA1000 chips */
0557     tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
0558     tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2);
0559     iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
0560     usleep_range(300, 400);
0561     tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2;
0562     iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
0563     usleep_range(300, 400);
0564     pci_iounmap(pdev, bar0_addr);
0565 }
0566 
0567 static void plx_pci_del_card(struct pci_dev *pdev)
0568 {
0569     struct plx_pci_card *card = pci_get_drvdata(pdev);
0570     struct net_device *dev;
0571     struct sja1000_priv *priv;
0572     int i = 0;
0573 
0574     for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
0575         dev = card->net_dev[i];
0576         if (!dev)
0577             continue;
0578 
0579         dev_info(&pdev->dev, "Removing %s\n", dev->name);
0580         unregister_sja1000dev(dev);
0581         priv = netdev_priv(dev);
0582         if (priv->reg_base)
0583             pci_iounmap(pdev, priv->reg_base);
0584         free_sja1000dev(dev);
0585     }
0586 
0587     card->reset_func(pdev);
0588 
0589     /*
0590      * Disable interrupts from PCI-card and disable local
0591      * interrupts
0592      */
0593     if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
0594         pdev->device != MARATHON_PCIE_DEVICE_ID)
0595         iowrite32(0x0, card->conf_addr + PLX_INTCSR);
0596     else
0597         iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
0598 
0599     if (card->conf_addr)
0600         pci_iounmap(pdev, card->conf_addr);
0601 
0602     kfree(card);
0603 
0604     pci_disable_device(pdev);
0605 }
0606 
0607 /*
0608  * Probe PLX90xx based device for the SJA1000 chips and register each
0609  * available CAN channel to SJA1000 Socket-CAN subsystem.
0610  */
0611 static int plx_pci_add_card(struct pci_dev *pdev,
0612                 const struct pci_device_id *ent)
0613 {
0614     struct sja1000_priv *priv;
0615     struct net_device *dev;
0616     struct plx_pci_card *card;
0617     struct plx_pci_card_info *ci;
0618     int err, i;
0619     u32 val;
0620     void __iomem *addr;
0621 
0622     ci = (struct plx_pci_card_info *)ent->driver_data;
0623 
0624     if (pci_enable_device(pdev) < 0) {
0625         dev_err(&pdev->dev, "Failed to enable PCI device\n");
0626         return -ENODEV;
0627     }
0628 
0629     dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
0630          ci->name, PCI_SLOT(pdev->devfn));
0631 
0632     /* Allocate card structures to hold addresses, ... */
0633     card = kzalloc(sizeof(*card), GFP_KERNEL);
0634     if (!card) {
0635         pci_disable_device(pdev);
0636         return -ENOMEM;
0637     }
0638 
0639     pci_set_drvdata(pdev, card);
0640 
0641     card->channels = 0;
0642 
0643     /* Remap PLX90xx configuration space */
0644     addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
0645     if (!addr) {
0646         err = -ENOMEM;
0647         dev_err(&pdev->dev, "Failed to remap configuration space "
0648             "(BAR%d)\n", ci->conf_map.bar);
0649         goto failure_cleanup;
0650     }
0651     card->conf_addr = addr + ci->conf_map.offset;
0652 
0653     ci->reset_func(pdev);
0654     card->reset_func = ci->reset_func;
0655 
0656     /* Detect available channels */
0657     for (i = 0; i < ci->channel_count; i++) {
0658         struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
0659 
0660         dev = alloc_sja1000dev(0);
0661         if (!dev) {
0662             err = -ENOMEM;
0663             goto failure_cleanup;
0664         }
0665 
0666         card->net_dev[i] = dev;
0667         priv = netdev_priv(dev);
0668         priv->priv = card;
0669         priv->irq_flags = IRQF_SHARED;
0670 
0671         dev->irq = pdev->irq;
0672 
0673         /*
0674          * Remap IO space of the SJA1000 chips
0675          * This is device-dependent mapping
0676          */
0677         addr = pci_iomap(pdev, cm->bar, cm->size);
0678         if (!addr) {
0679             err = -ENOMEM;
0680             dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
0681             goto failure_cleanup;
0682         }
0683 
0684         priv->reg_base = addr + cm->offset;
0685         priv->read_reg = plx_pci_read_reg;
0686         priv->write_reg = plx_pci_write_reg;
0687 
0688         /* Check if channel is present */
0689         if (plx_pci_check_sja1000(priv)) {
0690             priv->can.clock.freq = ci->can_clock;
0691             priv->ocr = ci->ocr;
0692             priv->cdr = ci->cdr;
0693 
0694             SET_NETDEV_DEV(dev, &pdev->dev);
0695             dev->dev_id = i;
0696 
0697             /* Register SJA1000 device */
0698             err = register_sja1000dev(dev);
0699             if (err) {
0700                 dev_err(&pdev->dev, "Registering device failed "
0701                     "(err=%d)\n", err);
0702                 goto failure_cleanup;
0703             }
0704 
0705             card->channels++;
0706 
0707             dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
0708                  "registered as %s\n", i + 1, priv->reg_base,
0709                  dev->irq, dev->name);
0710         } else {
0711             dev_err(&pdev->dev, "Channel #%d not detected\n",
0712                 i + 1);
0713             free_sja1000dev(dev);
0714             card->net_dev[i] = NULL;
0715         }
0716     }
0717 
0718     if (!card->channels) {
0719         err = -ENODEV;
0720         goto failure_cleanup;
0721     }
0722 
0723     /*
0724      * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
0725      * Local_2 interrupts from the SJA1000 chips
0726      */
0727     if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
0728         pdev->device != MARATHON_PCIE_DEVICE_ID) {
0729         val = ioread32(card->conf_addr + PLX_INTCSR);
0730         if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
0731             val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
0732         else
0733             val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
0734         iowrite32(val, card->conf_addr + PLX_INTCSR);
0735     } else {
0736         iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
0737               card->conf_addr + PLX9056_INTCSR);
0738     }
0739     return 0;
0740 
0741 failure_cleanup:
0742     dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
0743 
0744     plx_pci_del_card(pdev);
0745 
0746     return err;
0747 }
0748 
0749 static struct pci_driver plx_pci_driver = {
0750     .name = DRV_NAME,
0751     .id_table = plx_pci_tbl,
0752     .probe = plx_pci_add_card,
0753     .remove = plx_pci_del_card,
0754 };
0755 
0756 module_pci_driver(plx_pci_driver);
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