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0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/delay.h>
0016 #include <linux/pci.h>
0017 #include <linux/io.h>
0018 #include <linux/i2c.h>
0019 #include <linux/i2c-algo-bit.h>
0020 #include <linux/can.h>
0021 #include <linux/can/dev.h>
0022
0023 #include "sja1000.h"
0024
0025 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
0026 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards");
0027 MODULE_LICENSE("GPL v2");
0028
0029 #define DRV_NAME "peak_pci"
0030
0031
0032 #define PEAK_VER_REG1 0x40
0033 #define PEAK_VER_REG2 0x44
0034
0035 struct peak_pciec_card;
0036 struct peak_pci_chan {
0037 void __iomem *cfg_base;
0038 struct net_device *prev_dev;
0039 u16 icr_mask;
0040 struct peak_pciec_card *pciec_card;
0041 };
0042
0043 #define PEAK_PCI_CAN_CLOCK (16000000 / 2)
0044
0045 #define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
0046 #define PEAK_PCI_OCR OCR_TX0_PUSHPULL
0047
0048
0049 #define PITA_ICR 0x00
0050 #define PITA_GPIOICR 0x18
0051 #define PITA_MISC 0x1C
0052
0053 #define PEAK_PCI_CFG_SIZE 0x1000
0054 #define PEAK_PCI_CHAN_SIZE 0x0400
0055
0056 #define PEAK_PCI_VENDOR_ID 0x001C
0057 #define PEAK_PCI_DEVICE_ID 0x0001
0058 #define PEAK_PCIEC_DEVICE_ID 0x0002
0059 #define PEAK_PCIE_DEVICE_ID 0x0003
0060 #define PEAK_CPCI_DEVICE_ID 0x0004
0061 #define PEAK_MPCI_DEVICE_ID 0x0005
0062 #define PEAK_PC_104P_DEVICE_ID 0x0006
0063 #define PEAK_PCI_104E_DEVICE_ID 0x0007
0064 #define PEAK_MPCIE_DEVICE_ID 0x0008
0065 #define PEAK_PCIE_OEM_ID 0x0009
0066 #define PEAK_PCIEC34_DEVICE_ID 0x000A
0067
0068 #define PEAK_PCI_CHAN_MAX 4
0069
0070 static const u16 peak_pci_icr_masks[PEAK_PCI_CHAN_MAX] = {
0071 0x02, 0x01, 0x40, 0x80
0072 };
0073
0074 static const struct pci_device_id peak_pci_tbl[] = {
0075 {
0076 PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0077 .driver_data = (kernel_ulong_t)"PCAN-PCI",
0078 }, {
0079 PEAK_PCI_VENDOR_ID, PEAK_PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0080 .driver_data = (kernel_ulong_t)"PCAN-PCI Express",
0081 }, {
0082 PEAK_PCI_VENDOR_ID, PEAK_MPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0083 .driver_data = (kernel_ulong_t)"PCAN-miniPCI",
0084 }, {
0085 PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0086 .driver_data = (kernel_ulong_t)"PCAN-miniPCIe",
0087 }, {
0088 PEAK_PCI_VENDOR_ID, PEAK_PC_104P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0089 .driver_data = (kernel_ulong_t)"PCAN-PC/104-Plus Quad",
0090 }, {
0091 PEAK_PCI_VENDOR_ID, PEAK_PCI_104E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0092 .driver_data = (kernel_ulong_t)"PCAN-PCI/104-Express",
0093 }, {
0094 PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0095 .driver_data = (kernel_ulong_t)"PCAN-cPCI",
0096 }, {
0097 PEAK_PCI_VENDOR_ID, PEAK_PCIE_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,
0098 .driver_data = (kernel_ulong_t)"PCAN-Chip PCIe",
0099 },
0100 #ifdef CONFIG_CAN_PEAK_PCIEC
0101 {
0102 PEAK_PCI_VENDOR_ID, PEAK_PCIEC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0103 .driver_data = (kernel_ulong_t)"PCAN-ExpressCard",
0104 }, {
0105 PEAK_PCI_VENDOR_ID, PEAK_PCIEC34_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
0106 .driver_data = (kernel_ulong_t)"PCAN-ExpressCard 34",
0107 },
0108 #endif
0109 { }
0110 };
0111
0112 MODULE_DEVICE_TABLE(pci, peak_pci_tbl);
0113
0114 #ifdef CONFIG_CAN_PEAK_PCIEC
0115
0116
0117
0118 #define PITA_GPOUT 0x18
0119 #define PITA_GPIN 0x19
0120 #define PITA_GPOEN 0x1A
0121
0122
0123 #define PITA_GPIN_SCL 0x01
0124 #define PITA_GPIN_SDA 0x04
0125
0126 #define PCA9553_1_SLAVEADDR (0xC4 >> 1)
0127
0128
0129 enum {
0130 PCA9553_LOW,
0131 PCA9553_HIGHZ,
0132 PCA9553_PWM0,
0133 PCA9553_PWM1
0134 };
0135
0136
0137 #define PCA9553_ON PCA9553_LOW
0138 #define PCA9553_OFF PCA9553_HIGHZ
0139 #define PCA9553_SLOW PCA9553_PWM0
0140 #define PCA9553_FAST PCA9553_PWM1
0141
0142 #define PCA9553_LED(c) (1 << (c))
0143 #define PCA9553_LED_STATE(s, c) ((s) << ((c) << 1))
0144
0145 #define PCA9553_LED_ON(c) PCA9553_LED_STATE(PCA9553_ON, c)
0146 #define PCA9553_LED_OFF(c) PCA9553_LED_STATE(PCA9553_OFF, c)
0147 #define PCA9553_LED_SLOW(c) PCA9553_LED_STATE(PCA9553_SLOW, c)
0148 #define PCA9553_LED_FAST(c) PCA9553_LED_STATE(PCA9553_FAST, c)
0149 #define PCA9553_LED_MASK(c) PCA9553_LED_STATE(0x03, c)
0150
0151 #define PCA9553_LED_OFF_ALL (PCA9553_LED_OFF(0) | PCA9553_LED_OFF(1))
0152
0153 #define PCA9553_LS0_INIT 0x40
0154
0155 struct peak_pciec_chan {
0156 struct net_device *netdev;
0157 unsigned long prev_rx_bytes;
0158 unsigned long prev_tx_bytes;
0159 };
0160
0161 struct peak_pciec_card {
0162 void __iomem *cfg_base;
0163 void __iomem *reg_base;
0164 u8 led_cache;
0165
0166
0167 struct i2c_algo_bit_data i2c_bit;
0168 struct i2c_adapter led_chip;
0169 struct delayed_work led_work;
0170 int chan_count;
0171 struct peak_pciec_chan channel[PEAK_PCI_CHAN_MAX];
0172 };
0173
0174
0175 static void peak_pci_write_reg(const struct sja1000_priv *priv,
0176 int port, u8 val);
0177
0178 static inline void pita_set_scl_highz(struct peak_pciec_card *card)
0179 {
0180 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL;
0181
0182 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
0183 }
0184
0185 static inline void pita_set_sda_highz(struct peak_pciec_card *card)
0186 {
0187 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA;
0188
0189 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
0190 }
0191
0192 static void peak_pciec_init_pita_gpio(struct peak_pciec_card *card)
0193 {
0194
0195 pita_set_scl_highz(card);
0196 pita_set_sda_highz(card);
0197 }
0198
0199 static void pita_setsda(void *data, int state)
0200 {
0201 struct peak_pciec_card *card = (struct peak_pciec_card *)data;
0202 u8 gp_out, gp_outen;
0203
0204
0205 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA;
0206 writeb(gp_out, card->cfg_base + PITA_GPOUT);
0207
0208
0209 gp_outen = readb(card->cfg_base + PITA_GPOEN);
0210 if (state)
0211 gp_outen &= ~PITA_GPIN_SDA;
0212 else
0213 gp_outen |= PITA_GPIN_SDA;
0214
0215 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
0216 }
0217
0218 static void pita_setscl(void *data, int state)
0219 {
0220 struct peak_pciec_card *card = (struct peak_pciec_card *)data;
0221 u8 gp_out, gp_outen;
0222
0223
0224 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SCL;
0225 writeb(gp_out, card->cfg_base + PITA_GPOUT);
0226
0227
0228 gp_outen = readb(card->cfg_base + PITA_GPOEN);
0229 if (state)
0230 gp_outen &= ~PITA_GPIN_SCL;
0231 else
0232 gp_outen |= PITA_GPIN_SCL;
0233
0234 writeb(gp_outen, card->cfg_base + PITA_GPOEN);
0235 }
0236
0237 static int pita_getsda(void *data)
0238 {
0239 struct peak_pciec_card *card = (struct peak_pciec_card *)data;
0240
0241
0242 pita_set_sda_highz(card);
0243
0244 return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SDA) ? 1 : 0;
0245 }
0246
0247 static int pita_getscl(void *data)
0248 {
0249 struct peak_pciec_card *card = (struct peak_pciec_card *)data;
0250
0251
0252 pita_set_scl_highz(card);
0253
0254 return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SCL) ? 1 : 0;
0255 }
0256
0257
0258 static int peak_pciec_write_pca9553(struct peak_pciec_card *card,
0259 u8 offset, u8 data)
0260 {
0261 u8 buffer[2] = {
0262 offset,
0263 data
0264 };
0265 struct i2c_msg msg = {
0266 .addr = PCA9553_1_SLAVEADDR,
0267 .len = 2,
0268 .buf = buffer,
0269 };
0270 int ret;
0271
0272
0273 if (offset == 5 && data == card->led_cache)
0274 return 0;
0275
0276 ret = i2c_transfer(&card->led_chip, &msg, 1);
0277 if (ret < 0)
0278 return ret;
0279
0280 if (offset == 5)
0281 card->led_cache = data;
0282
0283 return 0;
0284 }
0285
0286
0287 static void peak_pciec_led_work(struct work_struct *work)
0288 {
0289 struct peak_pciec_card *card =
0290 container_of(work, struct peak_pciec_card, led_work.work);
0291 struct net_device *netdev;
0292 u8 new_led = card->led_cache;
0293 int i, up_count = 0;
0294
0295
0296 for (i = 0; i < card->chan_count; i++) {
0297
0298 new_led &= ~PCA9553_LED_MASK(i);
0299 new_led |= PCA9553_LED_ON(i);
0300
0301 netdev = card->channel[i].netdev;
0302 if (!netdev || !(netdev->flags & IFF_UP))
0303 continue;
0304
0305 up_count++;
0306
0307
0308 new_led &= ~PCA9553_LED_MASK(i);
0309 new_led |= PCA9553_LED_SLOW(i);
0310
0311
0312 if (netdev->stats.rx_bytes != card->channel[i].prev_rx_bytes) {
0313 card->channel[i].prev_rx_bytes = netdev->stats.rx_bytes;
0314 new_led &= ~PCA9553_LED_MASK(i);
0315 new_led |= PCA9553_LED_FAST(i);
0316 }
0317 if (netdev->stats.tx_bytes != card->channel[i].prev_tx_bytes) {
0318 card->channel[i].prev_tx_bytes = netdev->stats.tx_bytes;
0319 new_led &= ~PCA9553_LED_MASK(i);
0320 new_led |= PCA9553_LED_FAST(i);
0321 }
0322 }
0323
0324
0325 peak_pciec_write_pca9553(card, 5, new_led);
0326
0327
0328 if (up_count)
0329 schedule_delayed_work(&card->led_work, HZ);
0330 }
0331
0332
0333 static void peak_pciec_set_leds(struct peak_pciec_card *card, u8 led_mask, u8 s)
0334 {
0335 u8 new_led = card->led_cache;
0336 int i;
0337
0338
0339 for (i = 0; i < card->chan_count; i++)
0340 if (led_mask & PCA9553_LED(i)) {
0341 new_led &= ~PCA9553_LED_MASK(i);
0342 new_led |= PCA9553_LED_STATE(s, i);
0343 }
0344
0345
0346 peak_pciec_write_pca9553(card, 5, new_led);
0347 }
0348
0349
0350 static void peak_pciec_start_led_work(struct peak_pciec_card *card)
0351 {
0352 schedule_delayed_work(&card->led_work, HZ);
0353 }
0354
0355
0356 static void peak_pciec_stop_led_work(struct peak_pciec_card *card)
0357 {
0358 cancel_delayed_work_sync(&card->led_work);
0359 }
0360
0361
0362 static int peak_pciec_init_leds(struct peak_pciec_card *card)
0363 {
0364 int err;
0365
0366
0367 err = peak_pciec_write_pca9553(card, 1, 44 / 1);
0368 if (err)
0369 return err;
0370
0371
0372 err = peak_pciec_write_pca9553(card, 2, 0x80);
0373 if (err)
0374 return err;
0375
0376
0377 err = peak_pciec_write_pca9553(card, 3, 44 / 5);
0378 if (err)
0379 return err;
0380
0381
0382 err = peak_pciec_write_pca9553(card, 4, 0x80);
0383 if (err)
0384 return err;
0385
0386
0387 return peak_pciec_write_pca9553(card, 5, PCA9553_LS0_INIT);
0388 }
0389
0390
0391 static void peak_pciec_leds_exit(struct peak_pciec_card *card)
0392 {
0393
0394 peak_pciec_write_pca9553(card, 5, PCA9553_LED_OFF_ALL);
0395 }
0396
0397
0398
0399
0400 static void peak_pciec_write_reg(const struct sja1000_priv *priv,
0401 int port, u8 val)
0402 {
0403 struct peak_pci_chan *chan = priv->priv;
0404 struct peak_pciec_card *card = chan->pciec_card;
0405 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE;
0406
0407
0408 if (port == SJA1000_MOD)
0409 switch (val) {
0410 case MOD_RM:
0411
0412 peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_ON);
0413 break;
0414 case 0x00:
0415
0416 peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_SLOW);
0417 peak_pciec_start_led_work(card);
0418 break;
0419 default:
0420 break;
0421 }
0422
0423
0424 peak_pci_write_reg(priv, port, val);
0425 }
0426
0427 static const struct i2c_algo_bit_data peak_pciec_i2c_bit_ops = {
0428 .setsda = pita_setsda,
0429 .setscl = pita_setscl,
0430 .getsda = pita_getsda,
0431 .getscl = pita_getscl,
0432 .udelay = 10,
0433 .timeout = HZ,
0434 };
0435
0436 static int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev)
0437 {
0438 struct sja1000_priv *priv = netdev_priv(dev);
0439 struct peak_pci_chan *chan = priv->priv;
0440 struct peak_pciec_card *card;
0441 int err;
0442
0443
0444 if (chan->prev_dev) {
0445 struct sja1000_priv *prev_priv = netdev_priv(chan->prev_dev);
0446 struct peak_pci_chan *prev_chan = prev_priv->priv;
0447
0448 card = prev_chan->pciec_card;
0449 if (!card)
0450 return -ENODEV;
0451
0452
0453 } else {
0454
0455 card = kzalloc(sizeof(*card), GFP_KERNEL);
0456 if (!card)
0457 return -ENOMEM;
0458
0459 card->cfg_base = chan->cfg_base;
0460 card->reg_base = priv->reg_base;
0461
0462 card->led_chip.owner = THIS_MODULE;
0463 card->led_chip.dev.parent = &pdev->dev;
0464 card->led_chip.algo_data = &card->i2c_bit;
0465 strncpy(card->led_chip.name, "peak_i2c",
0466 sizeof(card->led_chip.name));
0467
0468 card->i2c_bit = peak_pciec_i2c_bit_ops;
0469 card->i2c_bit.udelay = 10;
0470 card->i2c_bit.timeout = HZ;
0471 card->i2c_bit.data = card;
0472
0473 peak_pciec_init_pita_gpio(card);
0474
0475 err = i2c_bit_add_bus(&card->led_chip);
0476 if (err) {
0477 dev_err(&pdev->dev, "i2c init failed\n");
0478 goto pciec_init_err_1;
0479 }
0480
0481 err = peak_pciec_init_leds(card);
0482 if (err) {
0483 dev_err(&pdev->dev, "leds hardware init failed\n");
0484 goto pciec_init_err_2;
0485 }
0486
0487 INIT_DELAYED_WORK(&card->led_work, peak_pciec_led_work);
0488
0489 priv->write_reg = peak_pciec_write_reg;
0490 }
0491
0492 chan->pciec_card = card;
0493 card->channel[card->chan_count++].netdev = dev;
0494
0495 return 0;
0496
0497 pciec_init_err_2:
0498 i2c_del_adapter(&card->led_chip);
0499
0500 pciec_init_err_1:
0501 peak_pciec_init_pita_gpio(card);
0502 kfree(card);
0503
0504 return err;
0505 }
0506
0507 static void peak_pciec_remove(struct peak_pciec_card *card)
0508 {
0509 peak_pciec_stop_led_work(card);
0510 peak_pciec_leds_exit(card);
0511 i2c_del_adapter(&card->led_chip);
0512 peak_pciec_init_pita_gpio(card);
0513 kfree(card);
0514 }
0515
0516 #else
0517
0518
0519 static inline int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev)
0520 {
0521 return -ENODEV;
0522 }
0523
0524 static inline void peak_pciec_remove(struct peak_pciec_card *card)
0525 {
0526 }
0527 #endif
0528
0529 static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port)
0530 {
0531 return readb(priv->reg_base + (port << 2));
0532 }
0533
0534 static void peak_pci_write_reg(const struct sja1000_priv *priv,
0535 int port, u8 val)
0536 {
0537 writeb(val, priv->reg_base + (port << 2));
0538 }
0539
0540 static void peak_pci_post_irq(const struct sja1000_priv *priv)
0541 {
0542 struct peak_pci_chan *chan = priv->priv;
0543 u16 icr;
0544
0545
0546 icr = readw(chan->cfg_base + PITA_ICR);
0547 if (icr & chan->icr_mask)
0548 writew(chan->icr_mask, chan->cfg_base + PITA_ICR);
0549 }
0550
0551 static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0552 {
0553 struct sja1000_priv *priv;
0554 struct peak_pci_chan *chan;
0555 struct net_device *dev, *prev_dev;
0556 void __iomem *cfg_base, *reg_base;
0557 u16 sub_sys_id, icr;
0558 int i, err, channels;
0559 char fw_str[14] = "";
0560
0561 err = pci_enable_device(pdev);
0562 if (err)
0563 return err;
0564
0565 err = pci_request_regions(pdev, DRV_NAME);
0566 if (err)
0567 goto failure_disable_pci;
0568
0569 err = pci_read_config_word(pdev, 0x2e, &sub_sys_id);
0570 if (err)
0571 goto failure_release_regions;
0572
0573 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n",
0574 pdev->vendor, pdev->device, sub_sys_id);
0575
0576 err = pci_write_config_word(pdev, 0x44, 0);
0577 if (err)
0578 goto failure_release_regions;
0579
0580 if (sub_sys_id >= 12)
0581 channels = 4;
0582 else if (sub_sys_id >= 10)
0583 channels = 3;
0584 else if (sub_sys_id >= 4)
0585 channels = 2;
0586 else
0587 channels = 1;
0588
0589 cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE);
0590 if (!cfg_base) {
0591 dev_err(&pdev->dev, "failed to map PCI resource #0\n");
0592 err = -ENOMEM;
0593 goto failure_release_regions;
0594 }
0595
0596 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels);
0597 if (!reg_base) {
0598 dev_err(&pdev->dev, "failed to map PCI resource #1\n");
0599 err = -ENOMEM;
0600 goto failure_unmap_cfg_base;
0601 }
0602
0603
0604 writew(0x0005, cfg_base + PITA_GPIOICR + 2);
0605
0606 writeb(0x00, cfg_base + PITA_GPIOICR);
0607
0608 writeb(0x05, cfg_base + PITA_MISC + 3);
0609 usleep_range(5000, 6000);
0610
0611 writeb(0x04, cfg_base + PITA_MISC + 3);
0612
0613
0614 if (readl(cfg_base + PEAK_VER_REG1)) {
0615
0616 u32 fw_ver = readl(cfg_base + PEAK_VER_REG2);
0617
0618 snprintf(fw_str, sizeof(fw_str), " FW v%u.%u.%u",
0619 (fw_ver >> 12) & 0xf,
0620 (fw_ver >> 8) & 0xf,
0621 (fw_ver >> 4) & 0xf);
0622 }
0623
0624
0625 dev_info(&pdev->dev, "%ux CAN %s%s\n",
0626 channels, (const char *)ent->driver_data, fw_str);
0627
0628 icr = readw(cfg_base + PITA_ICR + 2);
0629
0630 for (i = 0; i < channels; i++) {
0631 dev = alloc_sja1000dev(sizeof(struct peak_pci_chan));
0632 if (!dev) {
0633 err = -ENOMEM;
0634 goto failure_remove_channels;
0635 }
0636
0637 priv = netdev_priv(dev);
0638 chan = priv->priv;
0639
0640 chan->cfg_base = cfg_base;
0641 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE;
0642
0643 priv->read_reg = peak_pci_read_reg;
0644 priv->write_reg = peak_pci_write_reg;
0645 priv->post_irq = peak_pci_post_irq;
0646
0647 priv->can.clock.freq = PEAK_PCI_CAN_CLOCK;
0648 priv->ocr = PEAK_PCI_OCR;
0649 priv->cdr = PEAK_PCI_CDR;
0650
0651 if (channels == 1 || i > 0)
0652 priv->cdr |= CDR_CLK_OFF;
0653
0654
0655 priv->irq_flags = IRQF_SHARED;
0656 dev->irq = pdev->irq;
0657
0658 chan->icr_mask = peak_pci_icr_masks[i];
0659 icr |= chan->icr_mask;
0660
0661 SET_NETDEV_DEV(dev, &pdev->dev);
0662 dev->dev_id = i;
0663
0664
0665 chan->prev_dev = pci_get_drvdata(pdev);
0666 pci_set_drvdata(pdev, dev);
0667
0668
0669
0670
0671
0672 if (pdev->device == PEAK_PCIEC_DEVICE_ID ||
0673 pdev->device == PEAK_PCIEC34_DEVICE_ID) {
0674 err = peak_pciec_probe(pdev, dev);
0675 if (err) {
0676 dev_err(&pdev->dev,
0677 "failed to probe device (err %d)\n",
0678 err);
0679 goto failure_free_dev;
0680 }
0681 }
0682
0683 err = register_sja1000dev(dev);
0684 if (err) {
0685 dev_err(&pdev->dev, "failed to register device\n");
0686 goto failure_free_dev;
0687 }
0688
0689 dev_info(&pdev->dev,
0690 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n",
0691 dev->name, priv->reg_base, chan->cfg_base, dev->irq);
0692 }
0693
0694
0695 writew(icr, cfg_base + PITA_ICR + 2);
0696
0697 return 0;
0698
0699 failure_free_dev:
0700 pci_set_drvdata(pdev, chan->prev_dev);
0701 free_sja1000dev(dev);
0702
0703 failure_remove_channels:
0704
0705 writew(0x0, cfg_base + PITA_ICR + 2);
0706
0707 chan = NULL;
0708 for (dev = pci_get_drvdata(pdev); dev; dev = prev_dev) {
0709 priv = netdev_priv(dev);
0710 chan = priv->priv;
0711 prev_dev = chan->prev_dev;
0712
0713 unregister_sja1000dev(dev);
0714 free_sja1000dev(dev);
0715 }
0716
0717
0718 if (chan && chan->pciec_card)
0719 peak_pciec_remove(chan->pciec_card);
0720
0721 pci_iounmap(pdev, reg_base);
0722
0723 failure_unmap_cfg_base:
0724 pci_iounmap(pdev, cfg_base);
0725
0726 failure_release_regions:
0727 pci_release_regions(pdev);
0728
0729 failure_disable_pci:
0730 pci_disable_device(pdev);
0731
0732
0733
0734
0735
0736 return pcibios_err_to_errno(err);
0737 }
0738
0739 static void peak_pci_remove(struct pci_dev *pdev)
0740 {
0741 struct net_device *dev = pci_get_drvdata(pdev);
0742 struct sja1000_priv *priv = netdev_priv(dev);
0743 struct peak_pci_chan *chan = priv->priv;
0744 void __iomem *cfg_base = chan->cfg_base;
0745 void __iomem *reg_base = priv->reg_base;
0746
0747
0748 writew(0x0, cfg_base + PITA_ICR + 2);
0749
0750
0751 while (1) {
0752 struct net_device *prev_dev = chan->prev_dev;
0753
0754 dev_info(&pdev->dev, "removing device %s\n", dev->name);
0755
0756 if (!prev_dev && chan->pciec_card)
0757 peak_pciec_remove(chan->pciec_card);
0758 unregister_sja1000dev(dev);
0759 free_sja1000dev(dev);
0760 dev = prev_dev;
0761
0762 if (!dev)
0763 break;
0764 priv = netdev_priv(dev);
0765 chan = priv->priv;
0766 }
0767
0768 pci_iounmap(pdev, reg_base);
0769 pci_iounmap(pdev, cfg_base);
0770 pci_release_regions(pdev);
0771 pci_disable_device(pdev);
0772 }
0773
0774 static struct pci_driver peak_pci_driver = {
0775 .name = DRV_NAME,
0776 .id_table = peak_pci_tbl,
0777 .probe = peak_pci_probe,
0778 .remove = peak_pci_remove,
0779 };
0780
0781 module_pci_driver(peak_pci_driver);