can/sja1000/ems_pci.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
0004  * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
0005  * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/netdevice.h>
0012 #include <linux/delay.h>
0013 #include <linux/slab.h>
0014 #include <linux/pci.h>
0015 #include <linux/can/dev.h>
0016 #include <linux/io.h>
0017
0018 #include "sja1000.h"
0019
0020 #define DRV_NAME  "ems_pci"
0021
0022 MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
0023 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
0024 MODULE_LICENSE("GPL v2");
0025
0026 #define EMS_PCI_V1_MAX_CHAN 2
0027 #define EMS_PCI_V2_MAX_CHAN 4
0028 #define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN
0029
0030 struct ems_pci_card {
0031     int version;
0032     int channels;
0033
0034     struct pci_dev *pci_dev;
0035     struct net_device *net_dev[EMS_PCI_MAX_CHAN];
0036
0037     void __iomem *conf_addr;
0038     void __iomem *base_addr;
0039 };
0040
0041 #define EMS_PCI_CAN_CLOCK (16000000 / 2)
0042
0043 /*
0044  * Register definitions and descriptions are from LinCAN 0.3.3.
0045  *
0046  * PSB4610 PITA-2 bridge control registers
0047  */
0048 #define PITA2_ICR           0x00    /* Interrupt Control Register */
0049 #define PITA2_ICR_INT0      0x00000002  /* [RC] INT0 Active/Clear */
0050 #define PITA2_ICR_INT0_EN   0x00020000  /* [RW] Enable INT0 */
0051
0052 #define PITA2_MISC          0x1c    /* Miscellaneous Register */
0053 #define PITA2_MISC_CONFIG   0x04000000  /* Multiplexed parallel interface */
0054
0055 /*
0056  * Register definitions for the PLX 9030
0057  */
0058 #define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
0059 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
0060 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
0061 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
0062 #define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
0063                  PLX_ICSR_LINTI1_CLR)
0064
0065 /*
0066  * The board configuration is probably following:
0067  * RX1 is connected to ground.
0068  * TX1 is not connected.
0069  * CLKO is not connected.
0070  * Setting the OCR register to 0xDA is a good idea.
0071  * This means normal output mode, push-pull and the correct polarity.
0072  */
0073 #define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
0074
0075 /*
0076  * In the CDR register, you should set CBP to 1.
0077  * You will probably also want to set the clock divider value to 7
0078  * (meaning direct oscillator output) because the second SJA1000 chip
0079  * is driven by the first one CLKOUT output.
0080  */
0081 #define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)
0082
0083 #define EMS_PCI_V1_BASE_BAR     1
0084 #define EMS_PCI_V1_CONF_SIZE    4096 /* size of PITA control area */
0085 #define EMS_PCI_V2_BASE_BAR     2
0086 #define EMS_PCI_V2_CONF_SIZE    128 /* size of PLX control area */
0087 #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
0088 #define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */
0089
0090 #define EMS_PCI_BASE_SIZE  4096 /* size of controller area */
0091
0092 static const struct pci_device_id ems_pci_tbl[] = {
0093     /* CPC-PCI v1 */
0094     {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
0095     /* CPC-PCI v2 */
0096     {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
0097     /* CPC-104P v2 */
0098     {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
0099     {0,}
0100 };
0101 MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
0102
0103 /*
0104  * Helper to read internal registers from card logic (not CAN)
0105  */
0106 static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
0107 {
0108     return readb(card->base_addr + (port * 4));
0109 }
0110
0111 static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
0112 {
0113     return readb(priv->reg_base + (port * 4));
0114 }
0115
0116 static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
0117                  int port, u8 val)
0118 {
0119     writeb(val, priv->reg_base + (port * 4));
0120 }
0121
0122 static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
0123 {
0124     struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
0125
0126     /* reset int flag of pita */
0127     writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
0128            card->conf_addr + PITA2_ICR);
0129 }
0130
0131 static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
0132 {
0133     return readb(priv->reg_base + port);
0134 }
0135
0136 static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
0137                  int port, u8 val)
0138 {
0139     writeb(val, priv->reg_base + port);
0140 }
0141
0142 static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
0143 {
0144     struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
0145
0146     writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
0147 }
0148
0149 /*
0150  * Check if a CAN controller is present at the specified location
0151  * by trying to set 'em into the PeliCAN mode
0152  */
0153 static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
0154 {
0155     unsigned char res;
0156
0157     /* Make sure SJA1000 is in reset mode */
0158     priv->write_reg(priv, SJA1000_MOD, 1);
0159
0160     priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
0161
0162     /* read reset-values */
0163     res = priv->read_reg(priv, SJA1000_CDR);
0164
0165     if (res == CDR_PELICAN)
0166         return 1;
0167
0168     return 0;
0169 }
0170
0171 static void ems_pci_del_card(struct pci_dev *pdev)
0172 {
0173     struct ems_pci_card *card = pci_get_drvdata(pdev);
0174     struct net_device *dev;
0175     int i = 0;
0176
0177     for (i = 0; i < card->channels; i++) {
0178         dev = card->net_dev[i];
0179
0180         if (!dev)
0181             continue;
0182
0183         dev_info(&pdev->dev, "Removing %s.\n", dev->name);
0184         unregister_sja1000dev(dev);
0185         free_sja1000dev(dev);
0186     }
0187
0188     if (card->base_addr != NULL)
0189         pci_iounmap(card->pci_dev, card->base_addr);
0190
0191     if (card->conf_addr != NULL)
0192         pci_iounmap(card->pci_dev, card->conf_addr);
0193
0194     kfree(card);
0195
0196     pci_disable_device(pdev);
0197 }
0198
0199 static void ems_pci_card_reset(struct ems_pci_card *card)
0200 {
0201     /* Request board reset */
0202     writeb(0, card->base_addr);
0203 }
0204
0205 /*
0206  * Probe PCI device for EMS CAN signature and register each available
0207  * CAN channel to SJA1000 Socket-CAN subsystem.
0208  */
0209 static int ems_pci_add_card(struct pci_dev *pdev,
0210                 const struct pci_device_id *ent)
0211 {
0212     struct sja1000_priv *priv;
0213     struct net_device *dev;
0214     struct ems_pci_card *card;
0215     int max_chan, conf_size, base_bar;
0216     int err, i;
0217
0218     /* Enabling PCI device */
0219     if (pci_enable_device(pdev) < 0) {
0220         dev_err(&pdev->dev, "Enabling PCI device failed\n");
0221         return -ENODEV;
0222     }
0223
0224     /* Allocating card structures to hold addresses, ... */
0225     card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
0226     if (card == NULL) {
0227         pci_disable_device(pdev);
0228         return -ENOMEM;
0229     }
0230
0231     pci_set_drvdata(pdev, card);
0232
0233     card->pci_dev = pdev;
0234
0235     card->channels = 0;
0236
0237     if (pdev->vendor == PCI_VENDOR_ID_PLX) {
0238         card->version = 2; /* CPC-PCI v2 */
0239         max_chan = EMS_PCI_V2_MAX_CHAN;
0240         base_bar = EMS_PCI_V2_BASE_BAR;
0241         conf_size = EMS_PCI_V2_CONF_SIZE;
0242     } else {
0243         card->version = 1; /* CPC-PCI v1 */
0244         max_chan = EMS_PCI_V1_MAX_CHAN;
0245         base_bar = EMS_PCI_V1_BASE_BAR;
0246         conf_size = EMS_PCI_V1_CONF_SIZE;
0247     }
0248
0249     /* Remap configuration space and controller memory area */
0250     card->conf_addr = pci_iomap(pdev, 0, conf_size);
0251     if (card->conf_addr == NULL) {
0252         err = -ENOMEM;
0253         goto failure_cleanup;
0254     }
0255
0256     card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
0257     if (card->base_addr == NULL) {
0258         err = -ENOMEM;
0259         goto failure_cleanup;
0260     }
0261
0262     if (card->version == 1) {
0263         /* Configure PITA-2 parallel interface (enable MUX) */
0264         writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
0265
0266         /* Check for unique EMS CAN signature */
0267         if (ems_pci_v1_readb(card, 0) != 0x55 ||
0268             ems_pci_v1_readb(card, 1) != 0xAA ||
0269             ems_pci_v1_readb(card, 2) != 0x01 ||
0270             ems_pci_v1_readb(card, 3) != 0xCB ||
0271             ems_pci_v1_readb(card, 4) != 0x11) {
0272             dev_err(&pdev->dev,
0273                 "Not EMS Dr. Thomas Wuensche interface\n");
0274             err = -ENODEV;
0275             goto failure_cleanup;
0276         }
0277     }
0278
0279     ems_pci_card_reset(card);
0280
0281     /* Detect available channels */
0282     for (i = 0; i < max_chan; i++) {
0283         dev = alloc_sja1000dev(0);
0284         if (dev == NULL) {
0285             err = -ENOMEM;
0286             goto failure_cleanup;
0287         }
0288
0289         card->net_dev[i] = dev;
0290         priv = netdev_priv(dev);
0291         priv->priv = card;
0292         priv->irq_flags = IRQF_SHARED;
0293
0294         dev->irq = pdev->irq;
0295         priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
0296                     + (i * EMS_PCI_CAN_CTRL_SIZE);
0297         if (card->version == 1) {
0298             priv->read_reg  = ems_pci_v1_read_reg;
0299             priv->write_reg = ems_pci_v1_write_reg;
0300             priv->post_irq  = ems_pci_v1_post_irq;
0301         } else {
0302             priv->read_reg  = ems_pci_v2_read_reg;
0303             priv->write_reg = ems_pci_v2_write_reg;
0304             priv->post_irq  = ems_pci_v2_post_irq;
0305         }
0306
0307         /* Check if channel is present */
0308         if (ems_pci_check_chan(priv)) {
0309             priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
0310             priv->ocr = EMS_PCI_OCR;
0311             priv->cdr = EMS_PCI_CDR;
0312
0313             SET_NETDEV_DEV(dev, &pdev->dev);
0314             dev->dev_id = i;
0315
0316             if (card->version == 1)
0317                 /* reset int flag of pita */
0318                 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
0319                        card->conf_addr + PITA2_ICR);
0320             else
0321                 /* enable IRQ in PLX 9030 */
0322                 writel(PLX_ICSR_ENA_CLR,
0323                        card->conf_addr + PLX_ICSR);
0324
0325             /* Register SJA1000 device */
0326             err = register_sja1000dev(dev);
0327             if (err) {
0328                 dev_err(&pdev->dev, "Registering device failed "
0329                             "(err=%d)\n", err);
0330                 free_sja1000dev(dev);
0331                 goto failure_cleanup;
0332             }
0333
0334             card->channels++;
0335
0336             dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
0337                     i + 1, priv->reg_base, dev->irq);
0338         } else {
0339             free_sja1000dev(dev);
0340         }
0341     }
0342
0343     return 0;
0344
0345 failure_cleanup:
0346     dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
0347
0348     ems_pci_del_card(pdev);
0349
0350     return err;
0351 }
0352
0353 static struct pci_driver ems_pci_driver = {
0354     .name = DRV_NAME,
0355     .id_table = ems_pci_tbl,
0356     .probe = ems_pci_add_card,
0357     .remove = ems_pci_del_card,
0358 };
0359
0360 module_pci_driver(ems_pci_driver);