can/rcar/rcar_can.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Renesas R-Car CAN device driver
0003  *
0004  * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>
0005  * Copyright (C) 2013 Renesas Solutions Corp.
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/kernel.h>
0010 #include <linux/types.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/errno.h>
0013 #include <linux/ethtool.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/can/dev.h>
0017 #include <linux/clk.h>
0018 #include <linux/of.h>
0019
0020 #define RCAR_CAN_DRV_NAME   "rcar_can"
0021
0022 /* Clock Select Register settings */
0023 enum CLKR {
0024     CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */
0025     CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */
0026     CLKR_CLKEXT = 3, /* Externally input clock */
0027 };
0028
0029 #define RCAR_SUPPORTED_CLOCKS   (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \
0030                  BIT(CLKR_CLKEXT))
0031
0032 /* Mailbox configuration:
0033  * mailbox 60 - 63 - Rx FIFO mailboxes
0034  * mailbox 56 - 59 - Tx FIFO mailboxes
0035  * non-FIFO mailboxes are not used
0036  */
0037 #define RCAR_CAN_N_MBX      64 /* Number of mailboxes in non-FIFO mode */
0038 #define RCAR_CAN_RX_FIFO_MBX    60 /* Mailbox - window to Rx FIFO */
0039 #define RCAR_CAN_TX_FIFO_MBX    56 /* Mailbox - window to Tx FIFO */
0040 #define RCAR_CAN_FIFO_DEPTH 4
0041
0042 /* Mailbox registers structure */
0043 struct rcar_can_mbox_regs {
0044     u32 id;     /* IDE and RTR bits, SID and EID */
0045     u8 stub;    /* Not used */
0046     u8 dlc;     /* Data Length Code - bits [0..3] */
0047     u8 data[8]; /* Data Bytes */
0048     u8 tsh;     /* Time Stamp Higher Byte */
0049     u8 tsl;     /* Time Stamp Lower Byte */
0050 };
0051
0052 struct rcar_can_regs {
0053     struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */
0054     u32 mkr_2_9[8]; /* Mask Registers 2-9 */
0055     u32 fidcr[2];   /* FIFO Received ID Compare Register */
0056     u32 mkivlr1;    /* Mask Invalid Register 1 */
0057     u32 mier1;  /* Mailbox Interrupt Enable Register 1 */
0058     u32 mkr_0_1[2]; /* Mask Registers 0-1 */
0059     u32 mkivlr0;    /* Mask Invalid Register 0*/
0060     u32 mier0;      /* Mailbox Interrupt Enable Register 0 */
0061     u8 pad_440[0x3c0];
0062     u8 mctl[64];    /* Message Control Registers */
0063     u16 ctlr;   /* Control Register */
0064     u16 str;    /* Status register */
0065     u8 bcr[3];  /* Bit Configuration Register */
0066     u8 clkr;    /* Clock Select Register */
0067     u8 rfcr;    /* Receive FIFO Control Register */
0068     u8 rfpcr;   /* Receive FIFO Pointer Control Register */
0069     u8 tfcr;    /* Transmit FIFO Control Register */
0070     u8 tfpcr;       /* Transmit FIFO Pointer Control Register */
0071     u8 eier;    /* Error Interrupt Enable Register */
0072     u8 eifr;    /* Error Interrupt Factor Judge Register */
0073     u8 recr;    /* Receive Error Count Register */
0074     u8 tecr;        /* Transmit Error Count Register */
0075     u8 ecsr;    /* Error Code Store Register */
0076     u8 cssr;    /* Channel Search Support Register */
0077     u8 mssr;    /* Mailbox Search Status Register */
0078     u8 msmr;    /* Mailbox Search Mode Register */
0079     u16 tsr;    /* Time Stamp Register */
0080     u8 afsr;    /* Acceptance Filter Support Register */
0081     u8 pad_857;
0082     u8 tcr;     /* Test Control Register */
0083     u8 pad_859[7];
0084     u8 ier;     /* Interrupt Enable Register */
0085     u8 isr;     /* Interrupt Status Register */
0086     u8 pad_862;
0087     u8 mbsmr;   /* Mailbox Search Mask Register */
0088 };
0089
0090 struct rcar_can_priv {
0091     struct can_priv can;    /* Must be the first member! */
0092     struct net_device *ndev;
0093     struct napi_struct napi;
0094     struct rcar_can_regs __iomem *regs;
0095     struct clk *clk;
0096     struct clk *can_clk;
0097     u32 tx_head;
0098     u32 tx_tail;
0099     u8 clock_select;
0100     u8 ier;
0101 };
0102
0103 static const struct can_bittiming_const rcar_can_bittiming_const = {
0104     .name = RCAR_CAN_DRV_NAME,
0105     .tseg1_min = 4,
0106     .tseg1_max = 16,
0107     .tseg2_min = 2,
0108     .tseg2_max = 8,
0109     .sjw_max = 4,
0110     .brp_min = 1,
0111     .brp_max = 1024,
0112     .brp_inc = 1,
0113 };
0114
0115 /* Control Register bits */
0116 #define RCAR_CAN_CTLR_BOM   (3 << 11) /* Bus-Off Recovery Mode Bits */
0117 #define RCAR_CAN_CTLR_BOM_ENT   (1 << 11) /* Entry to halt mode */
0118                     /* at bus-off entry */
0119 #define RCAR_CAN_CTLR_SLPM  (1 << 10)
0120 #define RCAR_CAN_CTLR_CANM  (3 << 8) /* Operating Mode Select Bit */
0121 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9)
0122 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8)
0123 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)
0124 #define RCAR_CAN_CTLR_MLM   (1 << 3) /* Message Lost Mode Select */
0125 #define RCAR_CAN_CTLR_IDFM  (3 << 1) /* ID Format Mode Select Bits */
0126 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */
0127 #define RCAR_CAN_CTLR_MBM   (1 << 0) /* Mailbox Mode select */
0128
0129 /* Status Register bits */
0130 #define RCAR_CAN_STR_RSTST  (1 << 8) /* Reset Status Bit */
0131
0132 /* FIFO Received ID Compare Registers 0 and 1 bits */
0133 #define RCAR_CAN_FIDCR_IDE  (1 << 31) /* ID Extension Bit */
0134 #define RCAR_CAN_FIDCR_RTR  (1 << 30) /* Remote Transmission Request Bit */
0135
0136 /* Receive FIFO Control Register bits */
0137 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */
0138 #define RCAR_CAN_RFCR_RFE   (1 << 0) /* Receive FIFO Enable */
0139
0140 /* Transmit FIFO Control Register bits */
0141 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */
0142                     /* Number Status Bits */
0143 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */
0144                     /* Message Number Status Bits */
0145 #define RCAR_CAN_TFCR_TFE   (1 << 0) /* Transmit FIFO Enable */
0146
0147 #define RCAR_CAN_N_RX_MKREGS1   2   /* Number of mask registers */
0148                     /* for Rx mailboxes 0-31 */
0149 #define RCAR_CAN_N_RX_MKREGS2   8
0150
0151 /* Bit Configuration Register settings */
0152 #define RCAR_CAN_BCR_TSEG1(x)   (((x) & 0x0f) << 20)
0153 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
0154 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
0155 #define RCAR_CAN_BCR_TSEG2(x)   ((x) & 0x07)
0156
0157 /* Mailbox and Mask Registers bits */
0158 #define RCAR_CAN_IDE        (1 << 31)
0159 #define RCAR_CAN_RTR        (1 << 30)
0160 #define RCAR_CAN_SID_SHIFT  18
0161
0162 /* Mailbox Interrupt Enable Register 1 bits */
0163 #define RCAR_CAN_MIER1_RXFIE    (1 << 28) /* Receive  FIFO Interrupt Enable */
0164 #define RCAR_CAN_MIER1_TXFIE    (1 << 24) /* Transmit FIFO Interrupt Enable */
0165
0166 /* Interrupt Enable Register bits */
0167 #define RCAR_CAN_IER_ERSIE  (1 << 5) /* Error (ERS) Interrupt Enable Bit */
0168 #define RCAR_CAN_IER_RXFIE  (1 << 4) /* Reception FIFO Interrupt */
0169                     /* Enable Bit */
0170 #define RCAR_CAN_IER_TXFIE  (1 << 3) /* Transmission FIFO Interrupt */
0171                     /* Enable Bit */
0172 /* Interrupt Status Register bits */
0173 #define RCAR_CAN_ISR_ERSF   (1 << 5) /* Error (ERS) Interrupt Status Bit */
0174 #define RCAR_CAN_ISR_RXFF   (1 << 4) /* Reception FIFO Interrupt */
0175                     /* Status Bit */
0176 #define RCAR_CAN_ISR_TXFF   (1 << 3) /* Transmission FIFO Interrupt */
0177                     /* Status Bit */
0178
0179 /* Error Interrupt Enable Register bits */
0180 #define RCAR_CAN_EIER_BLIE  (1 << 7) /* Bus Lock Interrupt Enable */
0181 #define RCAR_CAN_EIER_OLIE  (1 << 6) /* Overload Frame Transmit */
0182                     /* Interrupt Enable */
0183 #define RCAR_CAN_EIER_ORIE  (1 << 5) /* Receive Overrun  Interrupt Enable */
0184 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */
0185 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */
0186 #define RCAR_CAN_EIER_EPIE  (1 << 2) /* Error Passive Interrupt Enable */
0187 #define RCAR_CAN_EIER_EWIE  (1 << 1) /* Error Warning Interrupt Enable */
0188 #define RCAR_CAN_EIER_BEIE  (1 << 0) /* Bus Error Interrupt Enable */
0189
0190 /* Error Interrupt Factor Judge Register bits */
0191 #define RCAR_CAN_EIFR_BLIF  (1 << 7) /* Bus Lock Detect Flag */
0192 #define RCAR_CAN_EIFR_OLIF  (1 << 6) /* Overload Frame Transmission */
0193                      /* Detect Flag */
0194 #define RCAR_CAN_EIFR_ORIF  (1 << 5) /* Receive Overrun Detect Flag */
0195 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */
0196 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */
0197 #define RCAR_CAN_EIFR_EPIF  (1 << 2) /* Error Passive Detect Flag */
0198 #define RCAR_CAN_EIFR_EWIF  (1 << 1) /* Error Warning Detect Flag */
0199 #define RCAR_CAN_EIFR_BEIF  (1 << 0) /* Bus Error Detect Flag */
0200
0201 /* Error Code Store Register bits */
0202 #define RCAR_CAN_ECSR_EDPM  (1 << 7) /* Error Display Mode Select Bit */
0203 #define RCAR_CAN_ECSR_ADEF  (1 << 6) /* ACK Delimiter Error Flag */
0204 #define RCAR_CAN_ECSR_BE0F  (1 << 5) /* Bit Error (dominant) Flag */
0205 #define RCAR_CAN_ECSR_BE1F  (1 << 4) /* Bit Error (recessive) Flag */
0206 #define RCAR_CAN_ECSR_CEF   (1 << 3) /* CRC Error Flag */
0207 #define RCAR_CAN_ECSR_AEF   (1 << 2) /* ACK Error Flag */
0208 #define RCAR_CAN_ECSR_FEF   (1 << 1) /* Form Error Flag */
0209 #define RCAR_CAN_ECSR_SEF   (1 << 0) /* Stuff Error Flag */
0210
0211 #define RCAR_CAN_NAPI_WEIGHT    4
0212 #define MAX_STR_READS       0x100
0213
0214 static void tx_failure_cleanup(struct net_device *ndev)
0215 {
0216     int i;
0217
0218     for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++)
0219         can_free_echo_skb(ndev, i, NULL);
0220 }
0221
0222 static void rcar_can_error(struct net_device *ndev)
0223 {
0224     struct rcar_can_priv *priv = netdev_priv(ndev);
0225     struct can_frame *cf;
0226     struct sk_buff *skb;
0227     u8 eifr, txerr = 0, rxerr = 0;
0228
0229     /* Propagate the error condition to the CAN stack */
0230     skb = alloc_can_err_skb(ndev, &cf);
0231
0232     eifr = readb(&priv->regs->eifr);
0233     if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {
0234         txerr = readb(&priv->regs->tecr);
0235         rxerr = readb(&priv->regs->recr);
0236         if (skb)
0237             cf->can_id |= CAN_ERR_CRTL;
0238     }
0239     if (eifr & RCAR_CAN_EIFR_BEIF) {
0240         int rx_errors = 0, tx_errors = 0;
0241         u8 ecsr;
0242
0243         netdev_dbg(priv->ndev, "Bus error interrupt:\n");
0244         if (skb)
0245             cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
0246
0247         ecsr = readb(&priv->regs->ecsr);
0248         if (ecsr & RCAR_CAN_ECSR_ADEF) {
0249             netdev_dbg(priv->ndev, "ACK Delimiter Error\n");
0250             tx_errors++;
0251             writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr);
0252             if (skb)
0253                 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL;
0254         }
0255         if (ecsr & RCAR_CAN_ECSR_BE0F) {
0256             netdev_dbg(priv->ndev, "Bit Error (dominant)\n");
0257             tx_errors++;
0258             writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr);
0259             if (skb)
0260                 cf->data[2] |= CAN_ERR_PROT_BIT0;
0261         }
0262         if (ecsr & RCAR_CAN_ECSR_BE1F) {
0263             netdev_dbg(priv->ndev, "Bit Error (recessive)\n");
0264             tx_errors++;
0265             writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr);
0266             if (skb)
0267                 cf->data[2] |= CAN_ERR_PROT_BIT1;
0268         }
0269         if (ecsr & RCAR_CAN_ECSR_CEF) {
0270             netdev_dbg(priv->ndev, "CRC Error\n");
0271             rx_errors++;
0272             writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr);
0273             if (skb)
0274                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
0275         }
0276         if (ecsr & RCAR_CAN_ECSR_AEF) {
0277             netdev_dbg(priv->ndev, "ACK Error\n");
0278             tx_errors++;
0279             writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr);
0280             if (skb) {
0281                 cf->can_id |= CAN_ERR_ACK;
0282                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
0283             }
0284         }
0285         if (ecsr & RCAR_CAN_ECSR_FEF) {
0286             netdev_dbg(priv->ndev, "Form Error\n");
0287             rx_errors++;
0288             writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr);
0289             if (skb)
0290                 cf->data[2] |= CAN_ERR_PROT_FORM;
0291         }
0292         if (ecsr & RCAR_CAN_ECSR_SEF) {
0293             netdev_dbg(priv->ndev, "Stuff Error\n");
0294             rx_errors++;
0295             writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr);
0296             if (skb)
0297                 cf->data[2] |= CAN_ERR_PROT_STUFF;
0298         }
0299
0300         priv->can.can_stats.bus_error++;
0301         ndev->stats.rx_errors += rx_errors;
0302         ndev->stats.tx_errors += tx_errors;
0303         writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr);
0304     }
0305     if (eifr & RCAR_CAN_EIFR_EWIF) {
0306         netdev_dbg(priv->ndev, "Error warning interrupt\n");
0307         priv->can.state = CAN_STATE_ERROR_WARNING;
0308         priv->can.can_stats.error_warning++;
0309         /* Clear interrupt condition */
0310         writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr);
0311         if (skb)
0312             cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
0313                           CAN_ERR_CRTL_RX_WARNING;
0314     }
0315     if (eifr & RCAR_CAN_EIFR_EPIF) {
0316         netdev_dbg(priv->ndev, "Error passive interrupt\n");
0317         priv->can.state = CAN_STATE_ERROR_PASSIVE;
0318         priv->can.can_stats.error_passive++;
0319         /* Clear interrupt condition */
0320         writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr);
0321         if (skb)
0322             cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
0323                           CAN_ERR_CRTL_RX_PASSIVE;
0324     }
0325     if (eifr & RCAR_CAN_EIFR_BOEIF) {
0326         netdev_dbg(priv->ndev, "Bus-off entry interrupt\n");
0327         tx_failure_cleanup(ndev);
0328         priv->ier = RCAR_CAN_IER_ERSIE;
0329         writeb(priv->ier, &priv->regs->ier);
0330         priv->can.state = CAN_STATE_BUS_OFF;
0331         /* Clear interrupt condition */
0332         writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr);
0333         priv->can.can_stats.bus_off++;
0334         can_bus_off(ndev);
0335         if (skb)
0336             cf->can_id |= CAN_ERR_BUSOFF;
0337     } else if (skb) {
0338         cf->can_id |= CAN_ERR_CNT;
0339         cf->data[6] = txerr;
0340         cf->data[7] = rxerr;
0341     }
0342     if (eifr & RCAR_CAN_EIFR_ORIF) {
0343         netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");
0344         ndev->stats.rx_over_errors++;
0345         ndev->stats.rx_errors++;
0346         writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr);
0347         if (skb) {
0348             cf->can_id |= CAN_ERR_CRTL;
0349             cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
0350         }
0351     }
0352     if (eifr & RCAR_CAN_EIFR_OLIF) {
0353         netdev_dbg(priv->ndev,
0354                "Overload Frame Transmission error interrupt\n");
0355         ndev->stats.rx_over_errors++;
0356         ndev->stats.rx_errors++;
0357         writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr);
0358         if (skb) {
0359             cf->can_id |= CAN_ERR_PROT;
0360             cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
0361         }
0362     }
0363
0364     if (skb)
0365         netif_rx(skb);
0366 }
0367
0368 static void rcar_can_tx_done(struct net_device *ndev)
0369 {
0370     struct rcar_can_priv *priv = netdev_priv(ndev);
0371     struct net_device_stats *stats = &ndev->stats;
0372     u8 isr;
0373
0374     while (1) {
0375         u8 unsent = readb(&priv->regs->tfcr);
0376
0377         unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
0378               RCAR_CAN_TFCR_TFUST_SHIFT;
0379         if (priv->tx_head - priv->tx_tail <= unsent)
0380             break;
0381         stats->tx_packets++;
0382         stats->tx_bytes +=
0383             can_get_echo_skb(ndev,
0384                      priv->tx_tail % RCAR_CAN_FIFO_DEPTH,
0385                      NULL);
0386
0387         priv->tx_tail++;
0388         netif_wake_queue(ndev);
0389     }
0390     /* Clear interrupt */
0391     isr = readb(&priv->regs->isr);
0392     writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr);
0393 }
0394
0395 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id)
0396 {
0397     struct net_device *ndev = dev_id;
0398     struct rcar_can_priv *priv = netdev_priv(ndev);
0399     u8 isr;
0400
0401     isr = readb(&priv->regs->isr);
0402     if (!(isr & priv->ier))
0403         return IRQ_NONE;
0404
0405     if (isr & RCAR_CAN_ISR_ERSF)
0406         rcar_can_error(ndev);
0407
0408     if (isr & RCAR_CAN_ISR_TXFF)
0409         rcar_can_tx_done(ndev);
0410
0411     if (isr & RCAR_CAN_ISR_RXFF) {
0412         if (napi_schedule_prep(&priv->napi)) {
0413             /* Disable Rx FIFO interrupts */
0414             priv->ier &= ~RCAR_CAN_IER_RXFIE;
0415             writeb(priv->ier, &priv->regs->ier);
0416             __napi_schedule(&priv->napi);
0417         }
0418     }
0419
0420     return IRQ_HANDLED;
0421 }
0422
0423 static void rcar_can_set_bittiming(struct net_device *dev)
0424 {
0425     struct rcar_can_priv *priv = netdev_priv(dev);
0426     struct can_bittiming *bt = &priv->can.bittiming;
0427     u32 bcr;
0428
0429     bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |
0430           RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |
0431           RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);
0432     /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
0433      * All the registers are big-endian but they get byte-swapped on 32-bit
0434      * read/write (but not on 8-bit, contrary to the manuals)...
0435      */
0436     writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);
0437 }
0438
0439 static void rcar_can_start(struct net_device *ndev)
0440 {
0441     struct rcar_can_priv *priv = netdev_priv(ndev);
0442     u16 ctlr;
0443     int i;
0444
0445     /* Set controller to known mode:
0446      * - FIFO mailbox mode
0447      * - accept all messages
0448      * - overrun mode
0449      * CAN is in sleep mode after MCU hardware or software reset.
0450      */
0451     ctlr = readw(&priv->regs->ctlr);
0452     ctlr &= ~RCAR_CAN_CTLR_SLPM;
0453     writew(ctlr, &priv->regs->ctlr);
0454     /* Go to reset mode */
0455     ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
0456     writew(ctlr, &priv->regs->ctlr);
0457     for (i = 0; i < MAX_STR_READS; i++) {
0458         if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
0459             break;
0460     }
0461     rcar_can_set_bittiming(ndev);
0462     ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
0463     ctlr |= RCAR_CAN_CTLR_BOM_ENT;  /* Entry to halt mode automatically */
0464                     /* at bus-off */
0465     ctlr |= RCAR_CAN_CTLR_MBM;  /* Select FIFO mailbox mode */
0466     ctlr |= RCAR_CAN_CTLR_MLM;  /* Overrun mode */
0467     writew(ctlr, &priv->regs->ctlr);
0468
0469     /* Accept all SID and EID */
0470     writel(0, &priv->regs->mkr_2_9[6]);
0471     writel(0, &priv->regs->mkr_2_9[7]);
0472     /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
0473     writel(0, &priv->regs->mkivlr1);
0474     /* Accept all frames */
0475     writel(0, &priv->regs->fidcr[0]);
0476     writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);
0477     /* Enable and configure FIFO mailbox interrupts */
0478     writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);
0479
0480     priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE |
0481             RCAR_CAN_IER_TXFIE;
0482     writeb(priv->ier, &priv->regs->ier);
0483
0484     /* Accumulate error codes */
0485     writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr);
0486     /* Enable error interrupts */
0487     writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE |
0488            (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ?
0489            RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE |
0490            RCAR_CAN_EIER_OLIE, &priv->regs->eier);
0491     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0492
0493     /* Go to operation mode */
0494     writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr);
0495     for (i = 0; i < MAX_STR_READS; i++) {
0496         if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST))
0497             break;
0498     }
0499     /* Enable Rx and Tx FIFO */
0500     writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);
0501     writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr);
0502 }
0503
0504 static int rcar_can_open(struct net_device *ndev)
0505 {
0506     struct rcar_can_priv *priv = netdev_priv(ndev);
0507     int err;
0508
0509     err = clk_prepare_enable(priv->clk);
0510     if (err) {
0511         netdev_err(ndev,
0512                "failed to enable peripheral clock, error %d\n",
0513                err);
0514         goto out;
0515     }
0516     err = clk_prepare_enable(priv->can_clk);
0517     if (err) {
0518         netdev_err(ndev, "failed to enable CAN clock, error %d\n",
0519                err);
0520         goto out_clock;
0521     }
0522     err = open_candev(ndev);
0523     if (err) {
0524         netdev_err(ndev, "open_candev() failed, error %d\n", err);
0525         goto out_can_clock;
0526     }
0527     napi_enable(&priv->napi);
0528     err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);
0529     if (err) {
0530         netdev_err(ndev, "request_irq(%d) failed, error %d\n",
0531                ndev->irq, err);
0532         goto out_close;
0533     }
0534     rcar_can_start(ndev);
0535     netif_start_queue(ndev);
0536     return 0;
0537 out_close:
0538     napi_disable(&priv->napi);
0539     close_candev(ndev);
0540 out_can_clock:
0541     clk_disable_unprepare(priv->can_clk);
0542 out_clock:
0543     clk_disable_unprepare(priv->clk);
0544 out:
0545     return err;
0546 }
0547
0548 static void rcar_can_stop(struct net_device *ndev)
0549 {
0550     struct rcar_can_priv *priv = netdev_priv(ndev);
0551     u16 ctlr;
0552     int i;
0553
0554     /* Go to (force) reset mode */
0555     ctlr = readw(&priv->regs->ctlr);
0556     ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
0557     writew(ctlr, &priv->regs->ctlr);
0558     for (i = 0; i < MAX_STR_READS; i++) {
0559         if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
0560             break;
0561     }
0562     writel(0, &priv->regs->mier0);
0563     writel(0, &priv->regs->mier1);
0564     writeb(0, &priv->regs->ier);
0565     writeb(0, &priv->regs->eier);
0566     /* Go to sleep mode */
0567     ctlr |= RCAR_CAN_CTLR_SLPM;
0568     writew(ctlr, &priv->regs->ctlr);
0569     priv->can.state = CAN_STATE_STOPPED;
0570 }
0571
0572 static int rcar_can_close(struct net_device *ndev)
0573 {
0574     struct rcar_can_priv *priv = netdev_priv(ndev);
0575
0576     netif_stop_queue(ndev);
0577     rcar_can_stop(ndev);
0578     free_irq(ndev->irq, ndev);
0579     napi_disable(&priv->napi);
0580     clk_disable_unprepare(priv->can_clk);
0581     clk_disable_unprepare(priv->clk);
0582     close_candev(ndev);
0583     return 0;
0584 }
0585
0586 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb,
0587                        struct net_device *ndev)
0588 {
0589     struct rcar_can_priv *priv = netdev_priv(ndev);
0590     struct can_frame *cf = (struct can_frame *)skb->data;
0591     u32 data, i;
0592
0593     if (can_dropped_invalid_skb(ndev, skb))
0594         return NETDEV_TX_OK;
0595
0596     if (cf->can_id & CAN_EFF_FLAG)  /* Extended frame format */
0597         data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE;
0598     else                /* Standard frame format */
0599         data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT;
0600
0601     if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */
0602         data |= RCAR_CAN_RTR;
0603     } else {
0604         for (i = 0; i < cf->len; i++)
0605             writeb(cf->data[i],
0606                    &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]);
0607     }
0608
0609     writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);
0610
0611     writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc);
0612
0613     can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0);
0614     priv->tx_head++;
0615     /* Start Tx: write 0xff to the TFPCR register to increment
0616      * the CPU-side pointer for the transmit FIFO to the next
0617      * mailbox location
0618      */
0619     writeb(0xff, &priv->regs->tfpcr);
0620     /* Stop the queue if we've filled all FIFO entries */
0621     if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH)
0622         netif_stop_queue(ndev);
0623
0624     return NETDEV_TX_OK;
0625 }
0626
0627 static const struct net_device_ops rcar_can_netdev_ops = {
0628     .ndo_open = rcar_can_open,
0629     .ndo_stop = rcar_can_close,
0630     .ndo_start_xmit = rcar_can_start_xmit,
0631     .ndo_change_mtu = can_change_mtu,
0632 };
0633
0634 static const struct ethtool_ops rcar_can_ethtool_ops = {
0635     .get_ts_info = ethtool_op_get_ts_info,
0636 };
0637
0638 static void rcar_can_rx_pkt(struct rcar_can_priv *priv)
0639 {
0640     struct net_device_stats *stats = &priv->ndev->stats;
0641     struct can_frame *cf;
0642     struct sk_buff *skb;
0643     u32 data;
0644     u8 dlc;
0645
0646     skb = alloc_can_skb(priv->ndev, &cf);
0647     if (!skb) {
0648         stats->rx_dropped++;
0649         return;
0650     }
0651
0652     data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id);
0653     if (data & RCAR_CAN_IDE)
0654         cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
0655     else
0656         cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK;
0657
0658     dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc);
0659     cf->len = can_cc_dlc2len(dlc);
0660     if (data & RCAR_CAN_RTR) {
0661         cf->can_id |= CAN_RTR_FLAG;
0662     } else {
0663         for (dlc = 0; dlc < cf->len; dlc++)
0664             cf->data[dlc] =
0665             readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]);
0666
0667         stats->rx_bytes += cf->len;
0668     }
0669     stats->rx_packets++;
0670
0671     netif_receive_skb(skb);
0672 }
0673
0674 static int rcar_can_rx_poll(struct napi_struct *napi, int quota)
0675 {
0676     struct rcar_can_priv *priv = container_of(napi,
0677                           struct rcar_can_priv, napi);
0678     int num_pkts;
0679
0680     for (num_pkts = 0; num_pkts < quota; num_pkts++) {
0681         u8 rfcr, isr;
0682
0683         isr = readb(&priv->regs->isr);
0684         /* Clear interrupt bit */
0685         if (isr & RCAR_CAN_ISR_RXFF)
0686             writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr);
0687         rfcr = readb(&priv->regs->rfcr);
0688         if (rfcr & RCAR_CAN_RFCR_RFEST)
0689             break;
0690         rcar_can_rx_pkt(priv);
0691         /* Write 0xff to the RFPCR register to increment
0692          * the CPU-side pointer for the receive FIFO
0693          * to the next mailbox location
0694          */
0695         writeb(0xff, &priv->regs->rfpcr);
0696     }
0697     /* All packets processed */
0698     if (num_pkts < quota) {
0699         napi_complete_done(napi, num_pkts);
0700         priv->ier |= RCAR_CAN_IER_RXFIE;
0701         writeb(priv->ier, &priv->regs->ier);
0702     }
0703     return num_pkts;
0704 }
0705
0706 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
0707 {
0708     switch (mode) {
0709     case CAN_MODE_START:
0710         rcar_can_start(ndev);
0711         netif_wake_queue(ndev);
0712         return 0;
0713     default:
0714         return -EOPNOTSUPP;
0715     }
0716 }
0717
0718 static int rcar_can_get_berr_counter(const struct net_device *dev,
0719                      struct can_berr_counter *bec)
0720 {
0721     struct rcar_can_priv *priv = netdev_priv(dev);
0722     int err;
0723
0724     err = clk_prepare_enable(priv->clk);
0725     if (err)
0726         return err;
0727     bec->txerr = readb(&priv->regs->tecr);
0728     bec->rxerr = readb(&priv->regs->recr);
0729     clk_disable_unprepare(priv->clk);
0730     return 0;
0731 }
0732
0733 static const char * const clock_names[] = {
0734     [CLKR_CLKP1]    = "clkp1",
0735     [CLKR_CLKP2]    = "clkp2",
0736     [CLKR_CLKEXT]   = "can_clk",
0737 };
0738
0739 static int rcar_can_probe(struct platform_device *pdev)
0740 {
0741     struct rcar_can_priv *priv;
0742     struct net_device *ndev;
0743     void __iomem *addr;
0744     u32 clock_select = CLKR_CLKP1;
0745     int err = -ENODEV;
0746     int irq;
0747
0748     of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select",
0749                  &clock_select);
0750
0751     irq = platform_get_irq(pdev, 0);
0752     if (irq < 0) {
0753         err = irq;
0754         goto fail;
0755     }
0756
0757     addr = devm_platform_ioremap_resource(pdev, 0);
0758     if (IS_ERR(addr)) {
0759         err = PTR_ERR(addr);
0760         goto fail;
0761     }
0762
0763     ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH);
0764     if (!ndev) {
0765         dev_err(&pdev->dev, "alloc_candev() failed\n");
0766         err = -ENOMEM;
0767         goto fail;
0768     }
0769
0770     priv = netdev_priv(ndev);
0771
0772     priv->clk = devm_clk_get(&pdev->dev, "clkp1");
0773     if (IS_ERR(priv->clk)) {
0774         err = PTR_ERR(priv->clk);
0775         dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
0776             err);
0777         goto fail_clk;
0778     }
0779
0780     if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) {
0781         err = -EINVAL;
0782         dev_err(&pdev->dev, "invalid CAN clock selected\n");
0783         goto fail_clk;
0784     }
0785     priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]);
0786     if (IS_ERR(priv->can_clk)) {
0787         err = PTR_ERR(priv->can_clk);
0788         dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err);
0789         goto fail_clk;
0790     }
0791
0792     ndev->netdev_ops = &rcar_can_netdev_ops;
0793     ndev->ethtool_ops = &rcar_can_ethtool_ops;
0794     ndev->irq = irq;
0795     ndev->flags |= IFF_ECHO;
0796     priv->ndev = ndev;
0797     priv->regs = addr;
0798     priv->clock_select = clock_select;
0799     priv->can.clock.freq = clk_get_rate(priv->can_clk);
0800     priv->can.bittiming_const = &rcar_can_bittiming_const;
0801     priv->can.do_set_mode = rcar_can_do_set_mode;
0802     priv->can.do_get_berr_counter = rcar_can_get_berr_counter;
0803     priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
0804     platform_set_drvdata(pdev, ndev);
0805     SET_NETDEV_DEV(ndev, &pdev->dev);
0806
0807     netif_napi_add_weight(ndev, &priv->napi, rcar_can_rx_poll,
0808                   RCAR_CAN_NAPI_WEIGHT);
0809     err = register_candev(ndev);
0810     if (err) {
0811         dev_err(&pdev->dev, "register_candev() failed, error %d\n",
0812             err);
0813         goto fail_candev;
0814     }
0815
0816     dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq);
0817
0818     return 0;
0819 fail_candev:
0820     netif_napi_del(&priv->napi);
0821 fail_clk:
0822     free_candev(ndev);
0823 fail:
0824     return err;
0825 }
0826
0827 static int rcar_can_remove(struct platform_device *pdev)
0828 {
0829     struct net_device *ndev = platform_get_drvdata(pdev);
0830     struct rcar_can_priv *priv = netdev_priv(ndev);
0831
0832     unregister_candev(ndev);
0833     netif_napi_del(&priv->napi);
0834     free_candev(ndev);
0835     return 0;
0836 }
0837
0838 static int __maybe_unused rcar_can_suspend(struct device *dev)
0839 {
0840     struct net_device *ndev = dev_get_drvdata(dev);
0841     struct rcar_can_priv *priv = netdev_priv(ndev);
0842     u16 ctlr;
0843
0844     if (!netif_running(ndev))
0845         return 0;
0846
0847     netif_stop_queue(ndev);
0848     netif_device_detach(ndev);
0849
0850     ctlr = readw(&priv->regs->ctlr);
0851     ctlr |= RCAR_CAN_CTLR_CANM_HALT;
0852     writew(ctlr, &priv->regs->ctlr);
0853     ctlr |= RCAR_CAN_CTLR_SLPM;
0854     writew(ctlr, &priv->regs->ctlr);
0855     priv->can.state = CAN_STATE_SLEEPING;
0856
0857     clk_disable(priv->clk);
0858     return 0;
0859 }
0860
0861 static int __maybe_unused rcar_can_resume(struct device *dev)
0862 {
0863     struct net_device *ndev = dev_get_drvdata(dev);
0864     struct rcar_can_priv *priv = netdev_priv(ndev);
0865     u16 ctlr;
0866     int err;
0867
0868     if (!netif_running(ndev))
0869         return 0;
0870
0871     err = clk_enable(priv->clk);
0872     if (err) {
0873         netdev_err(ndev, "clk_enable() failed, error %d\n", err);
0874         return err;
0875     }
0876
0877     ctlr = readw(&priv->regs->ctlr);
0878     ctlr &= ~RCAR_CAN_CTLR_SLPM;
0879     writew(ctlr, &priv->regs->ctlr);
0880     ctlr &= ~RCAR_CAN_CTLR_CANM;
0881     writew(ctlr, &priv->regs->ctlr);
0882     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0883
0884     netif_device_attach(ndev);
0885     netif_start_queue(ndev);
0886
0887     return 0;
0888 }
0889
0890 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);
0891
0892 static const struct of_device_id rcar_can_of_table[] __maybe_unused = {
0893     { .compatible = "renesas,can-r8a7778" },
0894     { .compatible = "renesas,can-r8a7779" },
0895     { .compatible = "renesas,can-r8a7790" },
0896     { .compatible = "renesas,can-r8a7791" },
0897     { .compatible = "renesas,rcar-gen1-can" },
0898     { .compatible = "renesas,rcar-gen2-can" },
0899     { .compatible = "renesas,rcar-gen3-can" },
0900     { }
0901 };
0902 MODULE_DEVICE_TABLE(of, rcar_can_of_table);
0903
0904 static struct platform_driver rcar_can_driver = {
0905     .driver = {
0906         .name = RCAR_CAN_DRV_NAME,
0907         .of_match_table = of_match_ptr(rcar_can_of_table),
0908         .pm = &rcar_can_pm_ops,
0909     },
0910     .probe = rcar_can_probe,
0911     .remove = rcar_can_remove,
0912 };
0913
0914 module_platform_driver(rcar_can_driver);
0915
0916 MODULE_AUTHOR("Cogent Embedded, Inc.");
0917 MODULE_LICENSE("GPL");
0918 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");
0919 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME);