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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com>
0003  * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com>
0004  *
0005  * Derived from the PCAN project file driver/src/pcan_pci.c:
0006  *
0007  * Copyright (C) 2001-2006  PEAK System-Technik GmbH
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/netdevice.h>
0014 #include <linux/delay.h>
0015 #include <linux/pci.h>
0016 #include <linux/io.h>
0017 #include <linux/can.h>
0018 #include <linux/can/dev.h>
0019 
0020 #include "peak_canfd_user.h"
0021 
0022 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
0023 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards");
0024 MODULE_LICENSE("GPL v2");
0025 
0026 #define PCIEFD_DRV_NAME     "peak_pciefd"
0027 
0028 #define PEAK_PCI_VENDOR_ID  0x001c  /* The PCI device and vendor IDs */
0029 #define PEAK_PCIEFD_ID      0x0013  /* for PCIe slot cards */
0030 #define PCAN_CPCIEFD_ID     0x0014  /* for Compact-PCI Serial slot cards */
0031 #define PCAN_PCIE104FD_ID   0x0017  /* for PCIe-104 Express slot cards */
0032 #define PCAN_MINIPCIEFD_ID      0x0018  /* for mini-PCIe slot cards */
0033 #define PCAN_PCIEFD_OEM_ID      0x0019  /* for PCIe slot OEM cards */
0034 #define PCAN_M2_ID      0x001a  /* for M2 slot cards */
0035 
0036 /* PEAK PCIe board access description */
0037 #define PCIEFD_BAR0_SIZE        (64 * 1024)
0038 #define PCIEFD_RX_DMA_SIZE      (4 * 1024)
0039 #define PCIEFD_TX_DMA_SIZE      (4 * 1024)
0040 
0041 #define PCIEFD_TX_PAGE_SIZE     (2 * 1024)
0042 
0043 /* System Control Registers */
0044 #define PCIEFD_REG_SYS_CTL_SET      0x0000  /* set bits */
0045 #define PCIEFD_REG_SYS_CTL_CLR      0x0004  /* clear bits */
0046 
0047 /* Version info registers */
0048 #define PCIEFD_REG_SYS_VER1     0x0040  /* version reg #1 */
0049 #define PCIEFD_REG_SYS_VER2     0x0044  /* version reg #2 */
0050 
0051 #define PCIEFD_FW_VERSION(x, y, z)  (((u32)(x) << 24) | \
0052                      ((u32)(y) << 16) | \
0053                      ((u32)(z) << 8))
0054 
0055 /* System Control Registers Bits */
0056 #define PCIEFD_SYS_CTL_TS_RST       0x00000001  /* timestamp clock */
0057 #define PCIEFD_SYS_CTL_CLK_EN       0x00000002  /* system clock */
0058 
0059 /* CAN-FD channel addresses */
0060 #define PCIEFD_CANX_OFF(c)      (((c) + 1) * 0x1000)
0061 
0062 #define PCIEFD_ECHO_SKB_MAX     PCANFD_ECHO_SKB_DEF
0063 
0064 /* CAN-FD channel registers */
0065 #define PCIEFD_REG_CAN_MISC     0x0000  /* Misc. control */
0066 #define PCIEFD_REG_CAN_CLK_SEL      0x0008  /* Clock selector */
0067 #define PCIEFD_REG_CAN_CMD_PORT_L   0x0010  /* 64-bits command port */
0068 #define PCIEFD_REG_CAN_CMD_PORT_H   0x0014
0069 #define PCIEFD_REG_CAN_TX_REQ_ACC   0x0020  /* Tx request accumulator */
0070 #define PCIEFD_REG_CAN_TX_CTL_SET   0x0030  /* Tx control set register */
0071 #define PCIEFD_REG_CAN_TX_CTL_CLR   0x0038  /* Tx control clear register */
0072 #define PCIEFD_REG_CAN_TX_DMA_ADDR_L    0x0040  /* 64-bits addr for Tx DMA */
0073 #define PCIEFD_REG_CAN_TX_DMA_ADDR_H    0x0044
0074 #define PCIEFD_REG_CAN_RX_CTL_SET   0x0050  /* Rx control set register */
0075 #define PCIEFD_REG_CAN_RX_CTL_CLR   0x0058  /* Rx control clear register */
0076 #define PCIEFD_REG_CAN_RX_CTL_WRT   0x0060  /* Rx control write register */
0077 #define PCIEFD_REG_CAN_RX_CTL_ACK   0x0068  /* Rx control ACK register */
0078 #define PCIEFD_REG_CAN_RX_DMA_ADDR_L    0x0070  /* 64-bits addr for Rx DMA */
0079 #define PCIEFD_REG_CAN_RX_DMA_ADDR_H    0x0074
0080 
0081 /* CAN-FD channel misc register bits */
0082 #define CANFD_MISC_TS_RST       0x00000001  /* timestamp cnt rst */
0083 
0084 /* CAN-FD channel Clock SELector Source & DIVider */
0085 #define CANFD_CLK_SEL_DIV_MASK      0x00000007
0086 #define CANFD_CLK_SEL_DIV_60MHZ     0x00000000  /* SRC=240MHz only */
0087 #define CANFD_CLK_SEL_DIV_40MHZ     0x00000001  /* SRC=240MHz only */
0088 #define CANFD_CLK_SEL_DIV_30MHZ     0x00000002  /* SRC=240MHz only */
0089 #define CANFD_CLK_SEL_DIV_24MHZ     0x00000003  /* SRC=240MHz only */
0090 #define CANFD_CLK_SEL_DIV_20MHZ     0x00000004  /* SRC=240MHz only */
0091 
0092 #define CANFD_CLK_SEL_SRC_MASK      0x00000008  /* 0=80MHz, 1=240MHz */
0093 #define CANFD_CLK_SEL_SRC_240MHZ    0x00000008
0094 #define CANFD_CLK_SEL_SRC_80MHZ     (~CANFD_CLK_SEL_SRC_240MHZ & \
0095                             CANFD_CLK_SEL_SRC_MASK)
0096 
0097 #define CANFD_CLK_SEL_20MHZ     (CANFD_CLK_SEL_SRC_240MHZ |\
0098                         CANFD_CLK_SEL_DIV_20MHZ)
0099 #define CANFD_CLK_SEL_24MHZ     (CANFD_CLK_SEL_SRC_240MHZ |\
0100                         CANFD_CLK_SEL_DIV_24MHZ)
0101 #define CANFD_CLK_SEL_30MHZ     (CANFD_CLK_SEL_SRC_240MHZ |\
0102                         CANFD_CLK_SEL_DIV_30MHZ)
0103 #define CANFD_CLK_SEL_40MHZ     (CANFD_CLK_SEL_SRC_240MHZ |\
0104                         CANFD_CLK_SEL_DIV_40MHZ)
0105 #define CANFD_CLK_SEL_60MHZ     (CANFD_CLK_SEL_SRC_240MHZ |\
0106                         CANFD_CLK_SEL_DIV_60MHZ)
0107 #define CANFD_CLK_SEL_80MHZ     (CANFD_CLK_SEL_SRC_80MHZ)
0108 
0109 /* CAN-FD channel Rx/Tx control register bits */
0110 #define CANFD_CTL_UNC_BIT       0x00010000  /* Uncached DMA mem */
0111 #define CANFD_CTL_RST_BIT       0x00020000  /* reset DMA action */
0112 #define CANFD_CTL_IEN_BIT       0x00040000  /* IRQ enable */
0113 
0114 /* Rx IRQ Count and Time Limits */
0115 #define CANFD_CTL_IRQ_CL_DEF    16  /* Rx msg max nb per IRQ in Rx DMA */
0116 #define CANFD_CTL_IRQ_TL_DEF    10  /* Time before IRQ if < CL (x100 µs) */
0117 
0118 /* Tx anticipation window (link logical address should be aligned on 2K
0119  * boundary)
0120  */
0121 #define PCIEFD_TX_PAGE_COUNT    (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE)
0122 
0123 #define CANFD_MSG_LNK_TX    0x1001  /* Tx msgs link */
0124 
0125 /* 32-bits IRQ status fields, heading Rx DMA area */
0126 static inline int pciefd_irq_tag(u32 irq_status)
0127 {
0128     return irq_status & 0x0000000f;
0129 }
0130 
0131 static inline int pciefd_irq_rx_cnt(u32 irq_status)
0132 {
0133     return (irq_status & 0x000007f0) >> 4;
0134 }
0135 
0136 static inline int pciefd_irq_is_lnk(u32 irq_status)
0137 {
0138     return irq_status & 0x00010000;
0139 }
0140 
0141 /* Rx record */
0142 struct pciefd_rx_dma {
0143     __le32 irq_status;
0144     __le32 sys_time_low;
0145     __le32 sys_time_high;
0146     struct pucan_rx_msg msg[];
0147 } __packed __aligned(4);
0148 
0149 /* Tx Link record */
0150 struct pciefd_tx_link {
0151     __le16 size;
0152     __le16 type;
0153     __le32 laddr_lo;
0154     __le32 laddr_hi;
0155 } __packed __aligned(4);
0156 
0157 /* Tx page descriptor */
0158 struct pciefd_page {
0159     void *vbase;            /* page virtual address */
0160     dma_addr_t lbase;       /* page logical address */
0161     u32 offset;
0162     u32 size;
0163 };
0164 
0165 /* CAN-FD channel object */
0166 struct pciefd_board;
0167 struct pciefd_can {
0168     struct peak_canfd_priv ucan;    /* must be the first member */
0169     void __iomem *reg_base;     /* channel config base addr */
0170     struct pciefd_board *board; /* reverse link */
0171 
0172     struct pucan_command pucan_cmd; /* command buffer */
0173 
0174     dma_addr_t rx_dma_laddr;    /* DMA virtual and logical addr */
0175     void *rx_dma_vaddr;     /* for Rx and Tx areas */
0176     dma_addr_t tx_dma_laddr;
0177     void *tx_dma_vaddr;
0178 
0179     struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT];
0180     u16 tx_pages_free;      /* free Tx pages counter */
0181     u16 tx_page_index;      /* current page used for Tx */
0182     spinlock_t tx_lock;
0183 
0184     u32 irq_status;
0185     u32 irq_tag;                /* next irq tag */
0186 };
0187 
0188 /* PEAK-PCIe FD board object */
0189 struct pciefd_board {
0190     void __iomem *reg_base;
0191     struct pci_dev *pci_dev;
0192     int can_count;
0193     spinlock_t cmd_lock;        /* 64-bits cmds must be atomic */
0194     struct pciefd_can *can[];   /* array of network devices */
0195 };
0196 
0197 /* supported device ids. */
0198 static const struct pci_device_id peak_pciefd_tbl[] = {
0199     {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
0200     {PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
0201     {PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,},
0202     {PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
0203     {PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,},
0204     {PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,},
0205     {0,}
0206 };
0207 
0208 MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl);
0209 
0210 /* read a 32 bits value from a SYS block register */
0211 static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg)
0212 {
0213     return readl(priv->reg_base + reg);
0214 }
0215 
0216 /* write a 32 bits value into a SYS block register */
0217 static inline void pciefd_sys_writereg(const struct pciefd_board *priv,
0218                        u32 val, u16 reg)
0219 {
0220     writel(val, priv->reg_base + reg);
0221 }
0222 
0223 /* read a 32 bits value from CAN-FD block register */
0224 static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg)
0225 {
0226     return readl(priv->reg_base + reg);
0227 }
0228 
0229 /* write a 32 bits value into a CAN-FD block register */
0230 static inline void pciefd_can_writereg(const struct pciefd_can *priv,
0231                        u32 val, u16 reg)
0232 {
0233     writel(val, priv->reg_base + reg);
0234 }
0235 
0236 /* give a channel logical Rx DMA address to the board */
0237 static void pciefd_can_setup_rx_dma(struct pciefd_can *priv)
0238 {
0239 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0240     const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32);
0241 #else
0242     const u32 dma_addr_h = 0;
0243 #endif
0244 
0245     /* (DMA must be reset for Rx) */
0246     pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
0247 
0248     /* write the logical address of the Rx DMA area for this channel */
0249     pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr,
0250                 PCIEFD_REG_CAN_RX_DMA_ADDR_L);
0251     pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
0252 
0253     /* also indicates that Rx DMA is cacheable */
0254     pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR);
0255 }
0256 
0257 /* clear channel logical Rx DMA address from the board */
0258 static void pciefd_can_clear_rx_dma(struct pciefd_can *priv)
0259 {
0260     /* DMA must be reset for Rx */
0261     pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
0262 
0263     /* clear the logical address of the Rx DMA area for this channel */
0264     pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L);
0265     pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
0266 }
0267 
0268 /* give a channel logical Tx DMA address to the board */
0269 static void pciefd_can_setup_tx_dma(struct pciefd_can *priv)
0270 {
0271 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0272     const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32);
0273 #else
0274     const u32 dma_addr_h = 0;
0275 #endif
0276 
0277     /* (DMA must be reset for Tx) */
0278     pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
0279 
0280     /* write the logical address of the Tx DMA area for this channel */
0281     pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr,
0282                 PCIEFD_REG_CAN_TX_DMA_ADDR_L);
0283     pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
0284 
0285     /* also indicates that Tx DMA is cacheable */
0286     pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
0287 }
0288 
0289 /* clear channel logical Tx DMA address from the board */
0290 static void pciefd_can_clear_tx_dma(struct pciefd_can *priv)
0291 {
0292     /* DMA must be reset for Tx */
0293     pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
0294 
0295     /* clear the logical address of the Tx DMA area for this channel */
0296     pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L);
0297     pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
0298 }
0299 
0300 static void pciefd_can_ack_rx_dma(struct pciefd_can *priv)
0301 {
0302     /* read value of current IRQ tag and inc it for next one */
0303     priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr);
0304     priv->irq_tag++;
0305     priv->irq_tag &= 0xf;
0306 
0307     /* write the next IRQ tag for this CAN */
0308     pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK);
0309 }
0310 
0311 /* IRQ handler */
0312 static irqreturn_t pciefd_irq_handler(int irq, void *arg)
0313 {
0314     struct pciefd_can *priv = arg;
0315     struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr;
0316 
0317     /* INTA mode only to sync with PCIe transaction */
0318     if (!pci_dev_msi_enabled(priv->board->pci_dev))
0319         (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
0320 
0321     /* read IRQ status from the first 32-bits of the Rx DMA area */
0322     priv->irq_status = le32_to_cpu(rx_dma->irq_status);
0323 
0324     /* check if this (shared) IRQ is for this CAN */
0325     if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag)
0326         return IRQ_NONE;
0327 
0328     /* handle rx messages (if any) */
0329     peak_canfd_handle_msgs_list(&priv->ucan,
0330                     rx_dma->msg,
0331                     pciefd_irq_rx_cnt(priv->irq_status));
0332 
0333     /* handle tx link interrupt (if any) */
0334     if (pciefd_irq_is_lnk(priv->irq_status)) {
0335         unsigned long flags;
0336 
0337         spin_lock_irqsave(&priv->tx_lock, flags);
0338         priv->tx_pages_free++;
0339         spin_unlock_irqrestore(&priv->tx_lock, flags);
0340 
0341         /* wake producer up (only if enough room in echo_skb array) */
0342         spin_lock_irqsave(&priv->ucan.echo_lock, flags);
0343         if (!priv->ucan.can.echo_skb[priv->ucan.echo_idx])
0344             netif_wake_queue(priv->ucan.ndev);
0345 
0346         spin_unlock_irqrestore(&priv->ucan.echo_lock, flags);
0347     }
0348 
0349     /* re-enable Rx DMA transfer for this CAN */
0350     pciefd_can_ack_rx_dma(priv);
0351 
0352     return IRQ_HANDLED;
0353 }
0354 
0355 static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan)
0356 {
0357     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0358     int i;
0359 
0360     /* initialize the Tx pages descriptors */
0361     priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1;
0362     priv->tx_page_index = 0;
0363 
0364     priv->tx_pages[0].vbase = priv->tx_dma_vaddr;
0365     priv->tx_pages[0].lbase = priv->tx_dma_laddr;
0366 
0367     for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) {
0368         priv->tx_pages[i].offset = 0;
0369         priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE -
0370                      sizeof(struct pciefd_tx_link);
0371         if (i) {
0372             priv->tx_pages[i].vbase =
0373                       priv->tx_pages[i - 1].vbase +
0374                       PCIEFD_TX_PAGE_SIZE;
0375             priv->tx_pages[i].lbase =
0376                       priv->tx_pages[i - 1].lbase +
0377                       PCIEFD_TX_PAGE_SIZE;
0378         }
0379     }
0380 
0381     /* setup Tx DMA addresses into IP core */
0382     pciefd_can_setup_tx_dma(priv);
0383 
0384     /* start (TX_RST=0) Tx Path */
0385     pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
0386 
0387     return 0;
0388 }
0389 
0390 /* board specific CANFD command pre-processing */
0391 static int pciefd_pre_cmd(struct peak_canfd_priv *ucan)
0392 {
0393     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0394     u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
0395     int err;
0396 
0397     /* pre-process command */
0398     switch (cmd) {
0399     case PUCAN_CMD_NORMAL_MODE:
0400     case PUCAN_CMD_LISTEN_ONLY_MODE:
0401 
0402         if (ucan->can.state == CAN_STATE_BUS_OFF)
0403             break;
0404 
0405         /* going into operational mode: setup IRQ handler */
0406         err = request_irq(priv->ucan.ndev->irq,
0407                   pciefd_irq_handler,
0408                   IRQF_SHARED,
0409                   PCIEFD_DRV_NAME,
0410                   priv);
0411         if (err)
0412             return err;
0413 
0414         /* setup Rx DMA address */
0415         pciefd_can_setup_rx_dma(priv);
0416 
0417         /* setup max count of msgs per IRQ */
0418         pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 |
0419                     CANFD_CTL_IRQ_CL_DEF,
0420                     PCIEFD_REG_CAN_RX_CTL_WRT);
0421 
0422         /* clear DMA RST for Rx (Rx start) */
0423         pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
0424                     PCIEFD_REG_CAN_RX_CTL_CLR);
0425 
0426         /* reset timestamps */
0427         pciefd_can_writereg(priv, !CANFD_MISC_TS_RST,
0428                     PCIEFD_REG_CAN_MISC);
0429 
0430         /* do an initial ACK */
0431         pciefd_can_ack_rx_dma(priv);
0432 
0433         /* enable IRQ for this CAN after having set next irq_tag */
0434         pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
0435                     PCIEFD_REG_CAN_RX_CTL_SET);
0436 
0437         /* Tx path will be setup as soon as RX_BARRIER is received */
0438         break;
0439     default:
0440         break;
0441     }
0442 
0443     return 0;
0444 }
0445 
0446 /* write a command */
0447 static int pciefd_write_cmd(struct peak_canfd_priv *ucan)
0448 {
0449     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0450     unsigned long flags;
0451 
0452     /* 64-bits command is atomic */
0453     spin_lock_irqsave(&priv->board->cmd_lock, flags);
0454 
0455     pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer,
0456                 PCIEFD_REG_CAN_CMD_PORT_L);
0457     pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4),
0458                 PCIEFD_REG_CAN_CMD_PORT_H);
0459 
0460     spin_unlock_irqrestore(&priv->board->cmd_lock, flags);
0461 
0462     return 0;
0463 }
0464 
0465 /* board specific CANFD command post-processing */
0466 static int pciefd_post_cmd(struct peak_canfd_priv *ucan)
0467 {
0468     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0469     u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
0470 
0471     switch (cmd) {
0472     case PUCAN_CMD_RESET_MODE:
0473 
0474         if (ucan->can.state == CAN_STATE_STOPPED)
0475             break;
0476 
0477         /* controller now in reset mode: */
0478 
0479         /* disable IRQ for this CAN */
0480         pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
0481                     PCIEFD_REG_CAN_RX_CTL_CLR);
0482 
0483         /* stop and reset DMA addresses in Tx/Rx engines */
0484         pciefd_can_clear_tx_dma(priv);
0485         pciefd_can_clear_rx_dma(priv);
0486 
0487         /* wait for above commands to complete (read cycle) */
0488         (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
0489 
0490         free_irq(priv->ucan.ndev->irq, priv);
0491 
0492         ucan->can.state = CAN_STATE_STOPPED;
0493 
0494         break;
0495     }
0496 
0497     return 0;
0498 }
0499 
0500 static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size,
0501                  int *room_left)
0502 {
0503     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0504     struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
0505     unsigned long flags;
0506     void *msg;
0507 
0508     spin_lock_irqsave(&priv->tx_lock, flags);
0509 
0510     if (page->offset + msg_size > page->size) {
0511         struct pciefd_tx_link *lk;
0512 
0513         /* not enough space in this page: try another one */
0514         if (!priv->tx_pages_free) {
0515             spin_unlock_irqrestore(&priv->tx_lock, flags);
0516 
0517             /* Tx overflow */
0518             return NULL;
0519         }
0520 
0521         priv->tx_pages_free--;
0522 
0523         /* keep address of the very last free slot of current page */
0524         lk = page->vbase + page->offset;
0525 
0526         /* next, move on a new free page */
0527         priv->tx_page_index = (priv->tx_page_index + 1) %
0528                       PCIEFD_TX_PAGE_COUNT;
0529         page = priv->tx_pages + priv->tx_page_index;
0530 
0531         /* put link record to this new page at the end of prev one */
0532         lk->size = cpu_to_le16(sizeof(*lk));
0533         lk->type = cpu_to_le16(CANFD_MSG_LNK_TX);
0534         lk->laddr_lo = cpu_to_le32(page->lbase);
0535 
0536 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0537         lk->laddr_hi = cpu_to_le32(page->lbase >> 32);
0538 #else
0539         lk->laddr_hi = 0;
0540 #endif
0541         /* next msgs will be put from the begininng of this new page */
0542         page->offset = 0;
0543     }
0544 
0545     *room_left = priv->tx_pages_free * page->size;
0546 
0547     spin_unlock_irqrestore(&priv->tx_lock, flags);
0548 
0549     msg = page->vbase + page->offset;
0550 
0551     /* give back room left in the tx ring */
0552     *room_left += page->size - (page->offset + msg_size);
0553 
0554     return msg;
0555 }
0556 
0557 static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan,
0558                    struct pucan_tx_msg *msg)
0559 {
0560     struct pciefd_can *priv = (struct pciefd_can *)ucan;
0561     struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
0562 
0563     /* this slot is now reserved for writing the frame */
0564     page->offset += le16_to_cpu(msg->size);
0565 
0566     /* tell the board a frame has been written in Tx DMA area */
0567     pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC);
0568 
0569     return 0;
0570 }
0571 
0572 /* probe for CAN-FD channel #pciefd_board->can_count */
0573 static int pciefd_can_probe(struct pciefd_board *pciefd)
0574 {
0575     struct net_device *ndev;
0576     struct pciefd_can *priv;
0577     u32 clk;
0578     int err;
0579 
0580     /* allocate the candev object with default isize of echo skbs ring */
0581     ndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count,
0582                     PCIEFD_ECHO_SKB_MAX);
0583     if (!ndev) {
0584         dev_err(&pciefd->pci_dev->dev,
0585             "failed to alloc candev object\n");
0586         goto failure;
0587     }
0588 
0589     priv = netdev_priv(ndev);
0590 
0591     /* fill-in candev private object: */
0592 
0593     /* setup PCIe-FD own callbacks */
0594     priv->ucan.pre_cmd = pciefd_pre_cmd;
0595     priv->ucan.write_cmd = pciefd_write_cmd;
0596     priv->ucan.post_cmd = pciefd_post_cmd;
0597     priv->ucan.enable_tx_path = pciefd_enable_tx_path;
0598     priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg;
0599     priv->ucan.write_tx_msg = pciefd_write_tx_msg;
0600 
0601     /* setup PCIe-FD own command buffer */
0602     priv->ucan.cmd_buffer = &priv->pucan_cmd;
0603     priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd);
0604 
0605     priv->board = pciefd;
0606 
0607     /* CAN config regs block address */
0608     priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index);
0609 
0610     /* allocate non-cacheable DMA'able 4KB memory area for Rx */
0611     priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
0612                          PCIEFD_RX_DMA_SIZE,
0613                          &priv->rx_dma_laddr,
0614                          GFP_KERNEL);
0615     if (!priv->rx_dma_vaddr) {
0616         dev_err(&pciefd->pci_dev->dev,
0617             "Rx dmam_alloc_coherent(%u) failure\n",
0618             PCIEFD_RX_DMA_SIZE);
0619         goto err_free_candev;
0620     }
0621 
0622     /* allocate non-cacheable DMA'able 4KB memory area for Tx */
0623     priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
0624                          PCIEFD_TX_DMA_SIZE,
0625                          &priv->tx_dma_laddr,
0626                          GFP_KERNEL);
0627     if (!priv->tx_dma_vaddr) {
0628         dev_err(&pciefd->pci_dev->dev,
0629             "Tx dmam_alloc_coherent(%u) failure\n",
0630             PCIEFD_TX_DMA_SIZE);
0631         goto err_free_candev;
0632     }
0633 
0634     /* CAN clock in RST mode */
0635     pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC);
0636 
0637     /* read current clock value */
0638     clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL);
0639     switch (clk) {
0640     case CANFD_CLK_SEL_20MHZ:
0641         priv->ucan.can.clock.freq = 20 * 1000 * 1000;
0642         break;
0643     case CANFD_CLK_SEL_24MHZ:
0644         priv->ucan.can.clock.freq = 24 * 1000 * 1000;
0645         break;
0646     case CANFD_CLK_SEL_30MHZ:
0647         priv->ucan.can.clock.freq = 30 * 1000 * 1000;
0648         break;
0649     case CANFD_CLK_SEL_40MHZ:
0650         priv->ucan.can.clock.freq = 40 * 1000 * 1000;
0651         break;
0652     case CANFD_CLK_SEL_60MHZ:
0653         priv->ucan.can.clock.freq = 60 * 1000 * 1000;
0654         break;
0655     default:
0656         pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ,
0657                     PCIEFD_REG_CAN_CLK_SEL);
0658 
0659         fallthrough;
0660     case CANFD_CLK_SEL_80MHZ:
0661         priv->ucan.can.clock.freq = 80 * 1000 * 1000;
0662         break;
0663     }
0664 
0665     ndev->irq = pciefd->pci_dev->irq;
0666 
0667     SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev);
0668 
0669     err = register_candev(ndev);
0670     if (err) {
0671         dev_err(&pciefd->pci_dev->dev,
0672             "couldn't register CAN device: %d\n", err);
0673         goto err_free_candev;
0674     }
0675 
0676     spin_lock_init(&priv->tx_lock);
0677 
0678     /* save the object address in the board structure */
0679     pciefd->can[pciefd->can_count] = priv;
0680 
0681     dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n",
0682          ndev->name, priv->reg_base, ndev->irq);
0683 
0684     return 0;
0685 
0686 err_free_candev:
0687     free_candev(ndev);
0688 
0689 failure:
0690     return -ENOMEM;
0691 }
0692 
0693 /* remove a CAN-FD channel by releasing all of its resources */
0694 static void pciefd_can_remove(struct pciefd_can *priv)
0695 {
0696     /* unregister (close) the can device to go back to RST mode first */
0697     unregister_candev(priv->ucan.ndev);
0698 
0699     /* finally, free the candev object */
0700     free_candev(priv->ucan.ndev);
0701 }
0702 
0703 /* remove all CAN-FD channels by releasing their own resources */
0704 static void pciefd_can_remove_all(struct pciefd_board *pciefd)
0705 {
0706     while (pciefd->can_count > 0)
0707         pciefd_can_remove(pciefd->can[--pciefd->can_count]);
0708 }
0709 
0710 /* probe for the entire device */
0711 static int peak_pciefd_probe(struct pci_dev *pdev,
0712                  const struct pci_device_id *ent)
0713 {
0714     struct pciefd_board *pciefd;
0715     int err, can_count;
0716     u16 sub_sys_id;
0717     u8 hw_ver_major;
0718     u8 hw_ver_minor;
0719     u8 hw_ver_sub;
0720     u32 v2;
0721 
0722     err = pci_enable_device(pdev);
0723     if (err)
0724         return err;
0725     err = pci_request_regions(pdev, PCIEFD_DRV_NAME);
0726     if (err)
0727         goto err_disable_pci;
0728 
0729     /* the number of channels depends on sub-system id */
0730     err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id);
0731     if (err)
0732         goto err_release_regions;
0733 
0734     dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n",
0735         pdev->vendor, pdev->device, sub_sys_id);
0736 
0737     if (sub_sys_id >= 0x0012)
0738         can_count = 4;
0739     else if (sub_sys_id >= 0x0010)
0740         can_count = 3;
0741     else if (sub_sys_id >= 0x0004)
0742         can_count = 2;
0743     else
0744         can_count = 1;
0745 
0746     /* allocate board structure object */
0747     pciefd = devm_kzalloc(&pdev->dev, struct_size(pciefd, can, can_count),
0748                   GFP_KERNEL);
0749     if (!pciefd) {
0750         err = -ENOMEM;
0751         goto err_release_regions;
0752     }
0753 
0754     /* initialize the board structure */
0755     pciefd->pci_dev = pdev;
0756     spin_lock_init(&pciefd->cmd_lock);
0757 
0758     /* save the PCI BAR0 virtual address for further system regs access */
0759     pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE);
0760     if (!pciefd->reg_base) {
0761         dev_err(&pdev->dev, "failed to map PCI resource #0\n");
0762         err = -ENOMEM;
0763         goto err_release_regions;
0764     }
0765 
0766     /* read the firmware version number */
0767     v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2);
0768 
0769     hw_ver_major = (v2 & 0x0000f000) >> 12;
0770     hw_ver_minor = (v2 & 0x00000f00) >> 8;
0771     hw_ver_sub = (v2 & 0x000000f0) >> 4;
0772 
0773     dev_info(&pdev->dev,
0774          "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count,
0775          hw_ver_major, hw_ver_minor, hw_ver_sub);
0776 
0777 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0778     /* FW < v3.3.0 DMA logic doesn't handle correctly the mix of 32-bit and
0779      * 64-bit logical addresses: this workaround forces usage of 32-bit
0780      * DMA addresses only when such a fw is detected.
0781      */
0782     if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) <
0783         PCIEFD_FW_VERSION(3, 3, 0)) {
0784         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
0785         if (err)
0786             dev_warn(&pdev->dev,
0787                  "warning: can't set DMA mask %llxh (err %d)\n",
0788                  DMA_BIT_MASK(32), err);
0789     }
0790 #endif
0791 
0792     /* stop system clock */
0793     pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
0794                 PCIEFD_REG_SYS_CTL_CLR);
0795 
0796     pci_set_master(pdev);
0797 
0798     /* create now the corresponding channels objects */
0799     while (pciefd->can_count < can_count) {
0800         err = pciefd_can_probe(pciefd);
0801         if (err)
0802             goto err_free_canfd;
0803 
0804         pciefd->can_count++;
0805     }
0806 
0807     /* set system timestamps counter in RST mode */
0808     pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
0809                 PCIEFD_REG_SYS_CTL_SET);
0810 
0811     /* wait a bit (read cycle) */
0812     (void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1);
0813 
0814     /* free all clocks */
0815     pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
0816                 PCIEFD_REG_SYS_CTL_CLR);
0817 
0818     /* start system clock */
0819     pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
0820                 PCIEFD_REG_SYS_CTL_SET);
0821 
0822     /* remember the board structure address in the device user data */
0823     pci_set_drvdata(pdev, pciefd);
0824 
0825     return 0;
0826 
0827 err_free_canfd:
0828     pciefd_can_remove_all(pciefd);
0829 
0830     pci_iounmap(pdev, pciefd->reg_base);
0831 
0832 err_release_regions:
0833     pci_release_regions(pdev);
0834 
0835 err_disable_pci:
0836     pci_disable_device(pdev);
0837 
0838     /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while
0839      * the probe() function must return a negative errno in case of failure
0840      * (err is unchanged if negative)
0841      */
0842     return pcibios_err_to_errno(err);
0843 }
0844 
0845 /* free the board structure object, as well as its resources: */
0846 static void peak_pciefd_remove(struct pci_dev *pdev)
0847 {
0848     struct pciefd_board *pciefd = pci_get_drvdata(pdev);
0849 
0850     /* release CAN-FD channels resources */
0851     pciefd_can_remove_all(pciefd);
0852 
0853     pci_iounmap(pdev, pciefd->reg_base);
0854 
0855     pci_release_regions(pdev);
0856     pci_disable_device(pdev);
0857 }
0858 
0859 static struct pci_driver peak_pciefd_driver = {
0860     .name = PCIEFD_DRV_NAME,
0861     .id_table = peak_pciefd_tbl,
0862     .probe = peak_pciefd_probe,
0863     .remove = peak_pciefd_remove,
0864 };
0865 
0866 module_pci_driver(peak_pciefd_driver);
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