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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 1999 - 2010 Intel Corporation.
0004  * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
0005  */
0006 
0007 #include <linux/interrupt.h>
0008 #include <linux/delay.h>
0009 #include <linux/ethtool.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/sched.h>
0013 #include <linux/pci.h>
0014 #include <linux/kernel.h>
0015 #include <linux/types.h>
0016 #include <linux/errno.h>
0017 #include <linux/netdevice.h>
0018 #include <linux/skbuff.h>
0019 #include <linux/can.h>
0020 #include <linux/can/dev.h>
0021 #include <linux/can/error.h>
0022 
0023 #define PCH_CTRL_INIT       BIT(0) /* The INIT bit of CANCONT register. */
0024 #define PCH_CTRL_IE     BIT(1) /* The IE bit of CAN control register */
0025 #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
0026 #define PCH_CTRL_CCE        BIT(6)
0027 #define PCH_CTRL_OPT        BIT(7) /* The OPT bit of CANCONT register. */
0028 #define PCH_OPT_SILENT      BIT(3) /* The Silent bit of CANOPT reg. */
0029 #define PCH_OPT_LBACK       BIT(4) /* The LoopBack bit of CANOPT reg. */
0030 
0031 #define PCH_CMASK_RX_TX_SET 0x00f3
0032 #define PCH_CMASK_RX_TX_GET 0x0073
0033 #define PCH_CMASK_ALL       0xff
0034 #define PCH_CMASK_NEWDAT    BIT(2)
0035 #define PCH_CMASK_CLRINTPND BIT(3)
0036 #define PCH_CMASK_CTRL      BIT(4)
0037 #define PCH_CMASK_ARB       BIT(5)
0038 #define PCH_CMASK_MASK      BIT(6)
0039 #define PCH_CMASK_RDWR      BIT(7)
0040 #define PCH_IF_MCONT_NEWDAT BIT(15)
0041 #define PCH_IF_MCONT_MSGLOST    BIT(14)
0042 #define PCH_IF_MCONT_INTPND BIT(13)
0043 #define PCH_IF_MCONT_UMASK  BIT(12)
0044 #define PCH_IF_MCONT_TXIE   BIT(11)
0045 #define PCH_IF_MCONT_RXIE   BIT(10)
0046 #define PCH_IF_MCONT_RMTEN  BIT(9)
0047 #define PCH_IF_MCONT_TXRQXT BIT(8)
0048 #define PCH_IF_MCONT_EOB    BIT(7)
0049 #define PCH_IF_MCONT_DLC    (BIT(0) | BIT(1) | BIT(2) | BIT(3))
0050 #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
0051 #define PCH_ID2_DIR     BIT(13)
0052 #define PCH_ID2_XTD     BIT(14)
0053 #define PCH_ID_MSGVAL       BIT(15)
0054 #define PCH_IF_CREQ_BUSY    BIT(15)
0055 
0056 #define PCH_STATUS_INT      0x8000
0057 #define PCH_RP          0x00008000
0058 #define PCH_REC         0x00007f00
0059 #define PCH_TEC         0x000000ff
0060 
0061 #define PCH_TX_OK       BIT(3)
0062 #define PCH_RX_OK       BIT(4)
0063 #define PCH_EPASSIV     BIT(5)
0064 #define PCH_EWARN       BIT(6)
0065 #define PCH_BUS_OFF     BIT(7)
0066 
0067 /* bit position of certain controller bits. */
0068 #define PCH_BIT_BRP_SHIFT   0
0069 #define PCH_BIT_SJW_SHIFT   6
0070 #define PCH_BIT_TSEG1_SHIFT 8
0071 #define PCH_BIT_TSEG2_SHIFT 12
0072 #define PCH_BIT_BRPE_BRPE_SHIFT 6
0073 
0074 #define PCH_MSK_BITT_BRP    0x3f
0075 #define PCH_MSK_BRPE_BRPE   0x3c0
0076 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
0077 #define PCH_COUNTER_LIMIT   10
0078 
0079 #define PCH_CAN_CLK     50000000    /* 50MHz */
0080 
0081 /*
0082  * Define the number of message object.
0083  * PCH CAN communications are done via Message RAM.
0084  * The Message RAM consists of 32 message objects.
0085  */
0086 #define PCH_RX_OBJ_NUM      26
0087 #define PCH_TX_OBJ_NUM      6
0088 #define PCH_RX_OBJ_START    1
0089 #define PCH_RX_OBJ_END      PCH_RX_OBJ_NUM
0090 #define PCH_TX_OBJ_START    (PCH_RX_OBJ_END + 1)
0091 #define PCH_TX_OBJ_END      (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
0092 
0093 #define PCH_FIFO_THRESH     16
0094 
0095 /* TxRqst2 show status of MsgObjNo.17~32 */
0096 #define PCH_TREQ2_TX_MASK   (((1 << PCH_TX_OBJ_NUM) - 1) <<\
0097                             (PCH_RX_OBJ_END - 16))
0098 
0099 enum pch_ifreg {
0100     PCH_RX_IFREG,
0101     PCH_TX_IFREG,
0102 };
0103 
0104 enum pch_can_err {
0105     PCH_STUF_ERR = 1,
0106     PCH_FORM_ERR,
0107     PCH_ACK_ERR,
0108     PCH_BIT1_ERR,
0109     PCH_BIT0_ERR,
0110     PCH_CRC_ERR,
0111     PCH_LEC_ALL,
0112 };
0113 
0114 enum pch_can_mode {
0115     PCH_CAN_ENABLE,
0116     PCH_CAN_DISABLE,
0117     PCH_CAN_ALL,
0118     PCH_CAN_NONE,
0119     PCH_CAN_STOP,
0120     PCH_CAN_RUN,
0121 };
0122 
0123 struct pch_can_if_regs {
0124     u32 creq;
0125     u32 cmask;
0126     u32 mask1;
0127     u32 mask2;
0128     u32 id1;
0129     u32 id2;
0130     u32 mcont;
0131     u32 data[4];
0132     u32 rsv[13];
0133 };
0134 
0135 struct pch_can_regs {
0136     u32 cont;
0137     u32 stat;
0138     u32 errc;
0139     u32 bitt;
0140     u32 intr;
0141     u32 opt;
0142     u32 brpe;
0143     u32 reserve;
0144     struct pch_can_if_regs ifregs[2]; /* [0]=if1  [1]=if2 */
0145     u32 reserve1[8];
0146     u32 treq1;
0147     u32 treq2;
0148     u32 reserve2[6];
0149     u32 data1;
0150     u32 data2;
0151     u32 reserve3[6];
0152     u32 canipend1;
0153     u32 canipend2;
0154     u32 reserve4[6];
0155     u32 canmval1;
0156     u32 canmval2;
0157     u32 reserve5[37];
0158     u32 srst;
0159 };
0160 
0161 struct pch_can_priv {
0162     struct can_priv can;
0163     struct pci_dev *dev;
0164     u32 tx_enable[PCH_TX_OBJ_END];
0165     u32 rx_enable[PCH_TX_OBJ_END];
0166     u32 rx_link[PCH_TX_OBJ_END];
0167     u32 int_enables;
0168     struct net_device *ndev;
0169     struct pch_can_regs __iomem *regs;
0170     struct napi_struct napi;
0171     int tx_obj; /* Point next Tx Obj index */
0172     int use_msi;
0173 };
0174 
0175 static const struct can_bittiming_const pch_can_bittiming_const = {
0176     .name = KBUILD_MODNAME,
0177     .tseg1_min = 2,
0178     .tseg1_max = 16,
0179     .tseg2_min = 1,
0180     .tseg2_max = 8,
0181     .sjw_max = 4,
0182     .brp_min = 1,
0183     .brp_max = 1024, /* 6bit + extended 4bit */
0184     .brp_inc = 1,
0185 };
0186 
0187 static const struct pci_device_id pch_pci_tbl[] = {
0188     {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
0189     {0,}
0190 };
0191 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
0192 
0193 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
0194 {
0195     iowrite32(ioread32(addr) | mask, addr);
0196 }
0197 
0198 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
0199 {
0200     iowrite32(ioread32(addr) & ~mask, addr);
0201 }
0202 
0203 static void pch_can_set_run_mode(struct pch_can_priv *priv,
0204                  enum pch_can_mode mode)
0205 {
0206     switch (mode) {
0207     case PCH_CAN_RUN:
0208         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
0209         break;
0210 
0211     case PCH_CAN_STOP:
0212         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
0213         break;
0214 
0215     default:
0216         netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
0217         break;
0218     }
0219 }
0220 
0221 static void pch_can_set_optmode(struct pch_can_priv *priv)
0222 {
0223     u32 reg_val = ioread32(&priv->regs->opt);
0224 
0225     if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
0226         reg_val |= PCH_OPT_SILENT;
0227 
0228     if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
0229         reg_val |= PCH_OPT_LBACK;
0230 
0231     pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
0232     iowrite32(reg_val, &priv->regs->opt);
0233 }
0234 
0235 static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
0236 {
0237     int counter = PCH_COUNTER_LIMIT;
0238     u32 ifx_creq;
0239 
0240     iowrite32(num, creq_addr);
0241     while (counter) {
0242         ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
0243         if (!ifx_creq)
0244             break;
0245         counter--;
0246         udelay(1);
0247     }
0248     if (!counter)
0249         pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
0250 }
0251 
0252 static void pch_can_set_int_enables(struct pch_can_priv *priv,
0253                     enum pch_can_mode interrupt_no)
0254 {
0255     switch (interrupt_no) {
0256     case PCH_CAN_DISABLE:
0257         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
0258         break;
0259 
0260     case PCH_CAN_ALL:
0261         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
0262         break;
0263 
0264     case PCH_CAN_NONE:
0265         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
0266         break;
0267 
0268     default:
0269         netdev_err(priv->ndev, "Invalid interrupt number.\n");
0270         break;
0271     }
0272 }
0273 
0274 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
0275                  int set, enum pch_ifreg dir)
0276 {
0277     u32 ie;
0278 
0279     if (dir)
0280         ie = PCH_IF_MCONT_TXIE;
0281     else
0282         ie = PCH_IF_MCONT_RXIE;
0283 
0284     /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
0285     iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
0286     pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
0287 
0288     /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
0289     iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
0290           &priv->regs->ifregs[dir].cmask);
0291 
0292     if (set) {
0293         /* Setting the MsgVal and RxIE/TxIE bits */
0294         pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
0295         pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
0296     } else {
0297         /* Clearing the MsgVal and RxIE/TxIE bits */
0298         pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
0299         pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
0300     }
0301 
0302     pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
0303 }
0304 
0305 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
0306 {
0307     int i;
0308 
0309     /* Traversing to obtain the object configured as receivers. */
0310     for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
0311         pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
0312 }
0313 
0314 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
0315 {
0316     int i;
0317 
0318     /* Traversing to obtain the object configured as transmit object. */
0319     for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
0320         pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
0321 }
0322 
0323 static u32 pch_can_int_pending(struct pch_can_priv *priv)
0324 {
0325     return ioread32(&priv->regs->intr) & 0xffff;
0326 }
0327 
0328 static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
0329 {
0330     int i; /* Msg Obj ID (1~32) */
0331 
0332     for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
0333         iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
0334         iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
0335         iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
0336         iowrite32(0x0, &priv->regs->ifregs[0].id1);
0337         iowrite32(0x0, &priv->regs->ifregs[0].id2);
0338         iowrite32(0x0, &priv->regs->ifregs[0].mcont);
0339         iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
0340         iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
0341         iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
0342         iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
0343         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
0344               PCH_CMASK_ARB | PCH_CMASK_CTRL,
0345               &priv->regs->ifregs[0].cmask);
0346         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
0347     }
0348 }
0349 
0350 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
0351 {
0352     int i;
0353 
0354     for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
0355         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
0356         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
0357 
0358         iowrite32(0x0, &priv->regs->ifregs[0].id1);
0359         iowrite32(0x0, &priv->regs->ifregs[0].id2);
0360 
0361         pch_can_bit_set(&priv->regs->ifregs[0].mcont,
0362                 PCH_IF_MCONT_UMASK);
0363 
0364         /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
0365         if (i == PCH_RX_OBJ_END)
0366             pch_can_bit_set(&priv->regs->ifregs[0].mcont,
0367                     PCH_IF_MCONT_EOB);
0368         else
0369             pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
0370                       PCH_IF_MCONT_EOB);
0371 
0372         iowrite32(0, &priv->regs->ifregs[0].mask1);
0373         pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
0374                   0x1fff | PCH_MASK2_MDIR_MXTD);
0375 
0376         /* Setting CMASK for writing */
0377         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
0378               PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
0379 
0380         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
0381     }
0382 
0383     for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
0384         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
0385         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
0386 
0387         /* Resetting DIR bit for reception */
0388         iowrite32(0x0, &priv->regs->ifregs[1].id1);
0389         iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
0390 
0391         /* Setting EOB bit for transmitter */
0392         iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
0393               &priv->regs->ifregs[1].mcont);
0394 
0395         iowrite32(0, &priv->regs->ifregs[1].mask1);
0396         pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
0397 
0398         /* Setting CMASK for writing */
0399         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
0400               PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
0401 
0402         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
0403     }
0404 }
0405 
0406 static void pch_can_init(struct pch_can_priv *priv)
0407 {
0408     /* Stopping the Can device. */
0409     pch_can_set_run_mode(priv, PCH_CAN_STOP);
0410 
0411     /* Clearing all the message object buffers. */
0412     pch_can_clear_if_buffers(priv);
0413 
0414     /* Configuring the respective message object as either rx/tx object. */
0415     pch_can_config_rx_tx_buffers(priv);
0416 
0417     /* Enabling the interrupts. */
0418     pch_can_set_int_enables(priv, PCH_CAN_ALL);
0419 }
0420 
0421 static void pch_can_release(struct pch_can_priv *priv)
0422 {
0423     /* Stooping the CAN device. */
0424     pch_can_set_run_mode(priv, PCH_CAN_STOP);
0425 
0426     /* Disabling the interrupts. */
0427     pch_can_set_int_enables(priv, PCH_CAN_NONE);
0428 
0429     /* Disabling all the receive object. */
0430     pch_can_set_rx_all(priv, 0);
0431 
0432     /* Disabling all the transmit object. */
0433     pch_can_set_tx_all(priv, 0);
0434 }
0435 
0436 /* This function clears interrupt(s) from the CAN device. */
0437 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
0438 {
0439     /* Clear interrupt for transmit object */
0440     if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
0441         /* Setting CMASK for clearing the reception interrupts. */
0442         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
0443               &priv->regs->ifregs[0].cmask);
0444 
0445         /* Clearing the Dir bit. */
0446         pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
0447 
0448         /* Clearing NewDat & IntPnd */
0449         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
0450                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
0451 
0452         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
0453     } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
0454         /*
0455          * Setting CMASK for clearing interrupts for frame transmission.
0456          */
0457         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
0458               &priv->regs->ifregs[1].cmask);
0459 
0460         /* Resetting the ID registers. */
0461         pch_can_bit_set(&priv->regs->ifregs[1].id2,
0462                    PCH_ID2_DIR | (0x7ff << 2));
0463         iowrite32(0x0, &priv->regs->ifregs[1].id1);
0464 
0465         /* Clearing NewDat, TxRqst & IntPnd */
0466         pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
0467                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
0468                   PCH_IF_MCONT_TXRQXT);
0469         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
0470     }
0471 }
0472 
0473 static void pch_can_reset(struct pch_can_priv *priv)
0474 {
0475     /* write to sw reset register */
0476     iowrite32(1, &priv->regs->srst);
0477     iowrite32(0, &priv->regs->srst);
0478 }
0479 
0480 static void pch_can_error(struct net_device *ndev, u32 status)
0481 {
0482     struct sk_buff *skb;
0483     struct pch_can_priv *priv = netdev_priv(ndev);
0484     struct can_frame *cf;
0485     u32 errc, lec;
0486     struct net_device_stats *stats = &(priv->ndev->stats);
0487     enum can_state state = priv->can.state;
0488 
0489     skb = alloc_can_err_skb(ndev, &cf);
0490     if (!skb)
0491         return;
0492 
0493     errc = ioread32(&priv->regs->errc);
0494     if (status & PCH_BUS_OFF) {
0495         pch_can_set_tx_all(priv, 0);
0496         pch_can_set_rx_all(priv, 0);
0497         state = CAN_STATE_BUS_OFF;
0498         cf->can_id |= CAN_ERR_BUSOFF;
0499         priv->can.can_stats.bus_off++;
0500         can_bus_off(ndev);
0501     } else {
0502         cf->can_id |= CAN_ERR_CNT;
0503         cf->data[6] = errc & PCH_TEC;
0504         cf->data[7] = (errc & PCH_REC) >> 8;
0505     }
0506 
0507     /* Warning interrupt. */
0508     if (status & PCH_EWARN) {
0509         state = CAN_STATE_ERROR_WARNING;
0510         priv->can.can_stats.error_warning++;
0511         cf->can_id |= CAN_ERR_CRTL;
0512         if (((errc & PCH_REC) >> 8) > 96)
0513             cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
0514         if ((errc & PCH_TEC) > 96)
0515             cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
0516         netdev_dbg(ndev,
0517             "%s -> Error Counter is more than 96.\n", __func__);
0518     }
0519     /* Error passive interrupt. */
0520     if (status & PCH_EPASSIV) {
0521         priv->can.can_stats.error_passive++;
0522         state = CAN_STATE_ERROR_PASSIVE;
0523         cf->can_id |= CAN_ERR_CRTL;
0524         if (errc & PCH_RP)
0525             cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
0526         if ((errc & PCH_TEC) > 127)
0527             cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
0528         netdev_dbg(ndev,
0529             "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
0530     }
0531 
0532     lec = status & PCH_LEC_ALL;
0533     switch (lec) {
0534     case PCH_STUF_ERR:
0535         cf->data[2] |= CAN_ERR_PROT_STUFF;
0536         priv->can.can_stats.bus_error++;
0537         stats->rx_errors++;
0538         break;
0539     case PCH_FORM_ERR:
0540         cf->data[2] |= CAN_ERR_PROT_FORM;
0541         priv->can.can_stats.bus_error++;
0542         stats->rx_errors++;
0543         break;
0544     case PCH_ACK_ERR:
0545         cf->can_id |= CAN_ERR_ACK;
0546         priv->can.can_stats.bus_error++;
0547         stats->rx_errors++;
0548         break;
0549     case PCH_BIT1_ERR:
0550     case PCH_BIT0_ERR:
0551         cf->data[2] |= CAN_ERR_PROT_BIT;
0552         priv->can.can_stats.bus_error++;
0553         stats->rx_errors++;
0554         break;
0555     case PCH_CRC_ERR:
0556         cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
0557         priv->can.can_stats.bus_error++;
0558         stats->rx_errors++;
0559         break;
0560     case PCH_LEC_ALL: /* Written by CPU. No error status */
0561         break;
0562     }
0563 
0564     priv->can.state = state;
0565     netif_receive_skb(skb);
0566 }
0567 
0568 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
0569 {
0570     struct net_device *ndev = (struct net_device *)dev_id;
0571     struct pch_can_priv *priv = netdev_priv(ndev);
0572 
0573     if (!pch_can_int_pending(priv))
0574         return IRQ_NONE;
0575 
0576     pch_can_set_int_enables(priv, PCH_CAN_NONE);
0577     napi_schedule(&priv->napi);
0578     return IRQ_HANDLED;
0579 }
0580 
0581 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
0582 {
0583     if (obj_id < PCH_FIFO_THRESH) {
0584         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
0585               PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
0586 
0587         /* Clearing the Dir bit. */
0588         pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
0589 
0590         /* Clearing NewDat & IntPnd */
0591         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
0592                   PCH_IF_MCONT_INTPND);
0593         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
0594     } else if (obj_id > PCH_FIFO_THRESH) {
0595         pch_can_int_clr(priv, obj_id);
0596     } else if (obj_id == PCH_FIFO_THRESH) {
0597         int cnt;
0598         for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
0599             pch_can_int_clr(priv, cnt + 1);
0600     }
0601 }
0602 
0603 static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
0604 {
0605     struct pch_can_priv *priv = netdev_priv(ndev);
0606     struct net_device_stats *stats = &(priv->ndev->stats);
0607     struct sk_buff *skb;
0608     struct can_frame *cf;
0609 
0610     netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
0611     pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
0612               PCH_IF_MCONT_MSGLOST);
0613     iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
0614           &priv->regs->ifregs[0].cmask);
0615     pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
0616 
0617     skb = alloc_can_err_skb(ndev, &cf);
0618     if (!skb)
0619         return;
0620 
0621     cf->can_id |= CAN_ERR_CRTL;
0622     cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
0623     stats->rx_over_errors++;
0624     stats->rx_errors++;
0625 
0626     netif_receive_skb(skb);
0627 }
0628 
0629 static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
0630 {
0631     u32 reg;
0632     canid_t id;
0633     int rcv_pkts = 0;
0634     struct sk_buff *skb;
0635     struct can_frame *cf;
0636     struct pch_can_priv *priv = netdev_priv(ndev);
0637     struct net_device_stats *stats = &(priv->ndev->stats);
0638     int i;
0639     u32 id2;
0640     u16 data_reg;
0641 
0642     do {
0643         /* Reading the message object from the Message RAM */
0644         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
0645         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
0646 
0647         /* Reading the MCONT register. */
0648         reg = ioread32(&priv->regs->ifregs[0].mcont);
0649 
0650         if (reg & PCH_IF_MCONT_EOB)
0651             break;
0652 
0653         /* If MsgLost bit set. */
0654         if (reg & PCH_IF_MCONT_MSGLOST) {
0655             pch_can_rx_msg_lost(ndev, obj_num);
0656             rcv_pkts++;
0657             quota--;
0658             obj_num++;
0659             continue;
0660         } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
0661             obj_num++;
0662             continue;
0663         }
0664 
0665         skb = alloc_can_skb(priv->ndev, &cf);
0666         if (!skb) {
0667             netdev_err(ndev, "alloc_can_skb Failed\n");
0668             return rcv_pkts;
0669         }
0670 
0671         /* Get Received data */
0672         id2 = ioread32(&priv->regs->ifregs[0].id2);
0673         if (id2 & PCH_ID2_XTD) {
0674             id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
0675             id |= (((id2) & 0x1fff) << 16);
0676             cf->can_id = id | CAN_EFF_FLAG;
0677         } else {
0678             id = (id2 >> 2) & CAN_SFF_MASK;
0679             cf->can_id = id;
0680         }
0681 
0682         cf->len = can_cc_dlc2len((ioread32(&priv->regs->
0683                             ifregs[0].mcont)) & 0xF);
0684 
0685         if (id2 & PCH_ID2_DIR) {
0686             cf->can_id |= CAN_RTR_FLAG;
0687         } else {
0688             for (i = 0; i < cf->len; i += 2) {
0689                 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
0690                 cf->data[i] = data_reg;
0691                 cf->data[i + 1] = data_reg >> 8;
0692             }
0693 
0694             stats->rx_bytes += cf->len;
0695         }
0696         stats->rx_packets++;
0697         rcv_pkts++;
0698         quota--;
0699         netif_receive_skb(skb);
0700 
0701         pch_fifo_thresh(priv, obj_num);
0702         obj_num++;
0703     } while (quota > 0);
0704 
0705     return rcv_pkts;
0706 }
0707 
0708 static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
0709 {
0710     struct pch_can_priv *priv = netdev_priv(ndev);
0711     struct net_device_stats *stats = &(priv->ndev->stats);
0712 
0713     stats->tx_bytes += can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1,
0714                         NULL);
0715     stats->tx_packets++;
0716     iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
0717           &priv->regs->ifregs[1].cmask);
0718     pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
0719     if (int_stat == PCH_TX_OBJ_END)
0720         netif_wake_queue(ndev);
0721 }
0722 
0723 static int pch_can_poll(struct napi_struct *napi, int quota)
0724 {
0725     struct net_device *ndev = napi->dev;
0726     struct pch_can_priv *priv = netdev_priv(ndev);
0727     u32 int_stat;
0728     u32 reg_stat;
0729     int quota_save = quota;
0730 
0731     int_stat = pch_can_int_pending(priv);
0732     if (!int_stat)
0733         goto end;
0734 
0735     if (int_stat == PCH_STATUS_INT) {
0736         reg_stat = ioread32(&priv->regs->stat);
0737 
0738         if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
0739            ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
0740             pch_can_error(ndev, reg_stat);
0741             quota--;
0742         }
0743 
0744         if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
0745             pch_can_bit_clear(&priv->regs->stat,
0746                       reg_stat & (PCH_TX_OK | PCH_RX_OK));
0747 
0748         int_stat = pch_can_int_pending(priv);
0749     }
0750 
0751     if (quota == 0)
0752         goto end;
0753 
0754     if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
0755         quota -= pch_can_rx_normal(ndev, int_stat, quota);
0756     } else if ((int_stat >= PCH_TX_OBJ_START) &&
0757            (int_stat <= PCH_TX_OBJ_END)) {
0758         /* Handle transmission interrupt */
0759         pch_can_tx_complete(ndev, int_stat);
0760     }
0761 
0762 end:
0763     napi_complete(napi);
0764     pch_can_set_int_enables(priv, PCH_CAN_ALL);
0765 
0766     return quota_save - quota;
0767 }
0768 
0769 static int pch_set_bittiming(struct net_device *ndev)
0770 {
0771     struct pch_can_priv *priv = netdev_priv(ndev);
0772     const struct can_bittiming *bt = &priv->can.bittiming;
0773     u32 canbit;
0774     u32 bepe;
0775 
0776     /* Setting the CCE bit for accessing the Can Timing register. */
0777     pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
0778 
0779     canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
0780     canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
0781     canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
0782     canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
0783     bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
0784     iowrite32(canbit, &priv->regs->bitt);
0785     iowrite32(bepe, &priv->regs->brpe);
0786     pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
0787 
0788     return 0;
0789 }
0790 
0791 static void pch_can_start(struct net_device *ndev)
0792 {
0793     struct pch_can_priv *priv = netdev_priv(ndev);
0794 
0795     if (priv->can.state != CAN_STATE_STOPPED)
0796         pch_can_reset(priv);
0797 
0798     pch_set_bittiming(ndev);
0799     pch_can_set_optmode(priv);
0800 
0801     pch_can_set_tx_all(priv, 1);
0802     pch_can_set_rx_all(priv, 1);
0803 
0804     /* Setting the CAN to run mode. */
0805     pch_can_set_run_mode(priv, PCH_CAN_RUN);
0806 
0807     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0808 
0809     return;
0810 }
0811 
0812 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
0813 {
0814     int ret = 0;
0815 
0816     switch (mode) {
0817     case CAN_MODE_START:
0818         pch_can_start(ndev);
0819         netif_wake_queue(ndev);
0820         break;
0821     default:
0822         ret = -EOPNOTSUPP;
0823         break;
0824     }
0825 
0826     return ret;
0827 }
0828 
0829 static int pch_can_open(struct net_device *ndev)
0830 {
0831     struct pch_can_priv *priv = netdev_priv(ndev);
0832     int retval;
0833 
0834     /* Registering the interrupt. */
0835     retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
0836                  ndev->name, ndev);
0837     if (retval) {
0838         netdev_err(ndev, "request_irq failed.\n");
0839         goto req_irq_err;
0840     }
0841 
0842     /* Open common can device */
0843     retval = open_candev(ndev);
0844     if (retval) {
0845         netdev_err(ndev, "open_candev() failed %d\n", retval);
0846         goto err_open_candev;
0847     }
0848 
0849     pch_can_init(priv);
0850     pch_can_start(ndev);
0851     napi_enable(&priv->napi);
0852     netif_start_queue(ndev);
0853 
0854     return 0;
0855 
0856 err_open_candev:
0857     free_irq(priv->dev->irq, ndev);
0858 req_irq_err:
0859     pch_can_release(priv);
0860 
0861     return retval;
0862 }
0863 
0864 static int pch_close(struct net_device *ndev)
0865 {
0866     struct pch_can_priv *priv = netdev_priv(ndev);
0867 
0868     netif_stop_queue(ndev);
0869     napi_disable(&priv->napi);
0870     pch_can_release(priv);
0871     free_irq(priv->dev->irq, ndev);
0872     close_candev(ndev);
0873     priv->can.state = CAN_STATE_STOPPED;
0874     return 0;
0875 }
0876 
0877 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
0878 {
0879     struct pch_can_priv *priv = netdev_priv(ndev);
0880     struct can_frame *cf = (struct can_frame *)skb->data;
0881     int tx_obj_no;
0882     int i;
0883     u32 id2;
0884 
0885     if (can_dropped_invalid_skb(ndev, skb))
0886         return NETDEV_TX_OK;
0887 
0888     tx_obj_no = priv->tx_obj;
0889     if (priv->tx_obj == PCH_TX_OBJ_END) {
0890         if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
0891             netif_stop_queue(ndev);
0892 
0893         priv->tx_obj = PCH_TX_OBJ_START;
0894     } else {
0895         priv->tx_obj++;
0896     }
0897 
0898     /* Setting the CMASK register. */
0899     pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
0900 
0901     /* If ID extended is set. */
0902     if (cf->can_id & CAN_EFF_FLAG) {
0903         iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
0904         id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
0905     } else {
0906         iowrite32(0, &priv->regs->ifregs[1].id1);
0907         id2 = (cf->can_id & CAN_SFF_MASK) << 2;
0908     }
0909 
0910     id2 |= PCH_ID_MSGVAL;
0911 
0912     /* If remote frame has to be transmitted.. */
0913     if (!(cf->can_id & CAN_RTR_FLAG))
0914         id2 |= PCH_ID2_DIR;
0915 
0916     iowrite32(id2, &priv->regs->ifregs[1].id2);
0917 
0918     /* Copy data to register */
0919     for (i = 0; i < cf->len; i += 2) {
0920         iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
0921               &priv->regs->ifregs[1].data[i / 2]);
0922     }
0923 
0924     can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1, 0);
0925 
0926     /* Set the size of the data. Update if2_mcont */
0927     iowrite32(cf->len | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
0928           PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
0929 
0930     pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
0931 
0932     return NETDEV_TX_OK;
0933 }
0934 
0935 static const struct net_device_ops pch_can_netdev_ops = {
0936     .ndo_open       = pch_can_open,
0937     .ndo_stop       = pch_close,
0938     .ndo_start_xmit     = pch_xmit,
0939     .ndo_change_mtu     = can_change_mtu,
0940 };
0941 
0942 static const struct ethtool_ops pch_can_ethtool_ops = {
0943     .get_ts_info = ethtool_op_get_ts_info,
0944 };
0945 
0946 static void pch_can_remove(struct pci_dev *pdev)
0947 {
0948     struct net_device *ndev = pci_get_drvdata(pdev);
0949     struct pch_can_priv *priv = netdev_priv(ndev);
0950 
0951     unregister_candev(priv->ndev);
0952     if (priv->use_msi)
0953         pci_disable_msi(priv->dev);
0954     pci_release_regions(pdev);
0955     pci_disable_device(pdev);
0956     pch_can_reset(priv);
0957     pci_iounmap(pdev, priv->regs);
0958     free_candev(priv->ndev);
0959 }
0960 
0961 static void __maybe_unused pch_can_set_int_custom(struct pch_can_priv *priv)
0962 {
0963     /* Clearing the IE, SIE and EIE bits of Can control register. */
0964     pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
0965 
0966     /* Appropriately setting them. */
0967     pch_can_bit_set(&priv->regs->cont,
0968             ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
0969 }
0970 
0971 /* This function retrieves interrupt enabled for the CAN device. */
0972 static u32 __maybe_unused pch_can_get_int_enables(struct pch_can_priv *priv)
0973 {
0974     /* Obtaining the status of IE, SIE and EIE interrupt bits. */
0975     return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
0976 }
0977 
0978 static u32 __maybe_unused pch_can_get_rxtx_ir(struct pch_can_priv *priv,
0979                           u32 buff_num, enum pch_ifreg dir)
0980 {
0981     u32 ie, enable;
0982 
0983     if (dir)
0984         ie = PCH_IF_MCONT_RXIE;
0985     else
0986         ie = PCH_IF_MCONT_TXIE;
0987 
0988     iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
0989     pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
0990 
0991     if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
0992             ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
0993         enable = 1;
0994     else
0995         enable = 0;
0996 
0997     return enable;
0998 }
0999 
1000 static void __maybe_unused pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1001                               u32 buffer_num, int set)
1002 {
1003     iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1004     pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1005     iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1006           &priv->regs->ifregs[0].cmask);
1007     if (set)
1008         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1009                   PCH_IF_MCONT_EOB);
1010     else
1011         pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1012 
1013     pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1014 }
1015 
1016 static u32 __maybe_unused pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
1017                              u32 buffer_num)
1018 {
1019     u32 link;
1020 
1021     iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1022     pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1023 
1024     if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1025         link = 0;
1026     else
1027         link = 1;
1028     return link;
1029 }
1030 
1031 static int __maybe_unused pch_can_get_buffer_status(struct pch_can_priv *priv)
1032 {
1033     return (ioread32(&priv->regs->treq1) & 0xffff) |
1034            (ioread32(&priv->regs->treq2) << 16);
1035 }
1036 
1037 static int __maybe_unused pch_can_suspend(struct device *dev_d)
1038 {
1039     int i;
1040     u32 buf_stat;   /* Variable for reading the transmit buffer status. */
1041     int counter = PCH_COUNTER_LIMIT;
1042 
1043     struct net_device *dev = dev_get_drvdata(dev_d);
1044     struct pch_can_priv *priv = netdev_priv(dev);
1045 
1046     /* Stop the CAN controller */
1047     pch_can_set_run_mode(priv, PCH_CAN_STOP);
1048 
1049     /* Indicate that we are aboutto/in suspend */
1050     priv->can.state = CAN_STATE_STOPPED;
1051 
1052     /* Waiting for all transmission to complete. */
1053     while (counter) {
1054         buf_stat = pch_can_get_buffer_status(priv);
1055         if (!buf_stat)
1056             break;
1057         counter--;
1058         udelay(1);
1059     }
1060     if (!counter)
1061         dev_err(dev_d, "%s -> Transmission time out.\n", __func__);
1062 
1063     /* Save interrupt configuration and then disable them */
1064     priv->int_enables = pch_can_get_int_enables(priv);
1065     pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1066 
1067     /* Save Tx buffer enable state */
1068     for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1069         priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1070                                  PCH_TX_IFREG);
1071 
1072     /* Disable all Transmit buffers */
1073     pch_can_set_tx_all(priv, 0);
1074 
1075     /* Save Rx buffer enable state */
1076     for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1077         priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1078                                  PCH_RX_IFREG);
1079         priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
1080     }
1081 
1082     /* Disable all Receive buffers */
1083     pch_can_set_rx_all(priv, 0);
1084 
1085     return 0;
1086 }
1087 
1088 static int __maybe_unused pch_can_resume(struct device *dev_d)
1089 {
1090     int i;
1091     struct net_device *dev = dev_get_drvdata(dev_d);
1092     struct pch_can_priv *priv = netdev_priv(dev);
1093 
1094     priv->can.state = CAN_STATE_ERROR_ACTIVE;
1095 
1096     /* Disabling all interrupts. */
1097     pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1098 
1099     /* Setting the CAN device in Stop Mode. */
1100     pch_can_set_run_mode(priv, PCH_CAN_STOP);
1101 
1102     /* Configuring the transmit and receive buffers. */
1103     pch_can_config_rx_tx_buffers(priv);
1104 
1105     /* Restore the CAN state */
1106     pch_set_bittiming(dev);
1107 
1108     /* Listen/Active */
1109     pch_can_set_optmode(priv);
1110 
1111     /* Enabling the transmit buffer. */
1112     for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1113         pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
1114 
1115     /* Configuring the receive buffer and enabling them. */
1116     for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1117         /* Restore buffer link */
1118         pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
1119 
1120         /* Restore buffer enables */
1121         pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
1122     }
1123 
1124     /* Enable CAN Interrupts */
1125     pch_can_set_int_custom(priv);
1126 
1127     /* Restore Run Mode */
1128     pch_can_set_run_mode(priv, PCH_CAN_RUN);
1129 
1130     return 0;
1131 }
1132 
1133 static int pch_can_get_berr_counter(const struct net_device *dev,
1134                     struct can_berr_counter *bec)
1135 {
1136     struct pch_can_priv *priv = netdev_priv(dev);
1137     u32 errc = ioread32(&priv->regs->errc);
1138 
1139     bec->txerr = errc & PCH_TEC;
1140     bec->rxerr = (errc & PCH_REC) >> 8;
1141 
1142     return 0;
1143 }
1144 
1145 static int pch_can_probe(struct pci_dev *pdev,
1146                    const struct pci_device_id *id)
1147 {
1148     struct net_device *ndev;
1149     struct pch_can_priv *priv;
1150     int rc;
1151     void __iomem *addr;
1152 
1153     rc = pci_enable_device(pdev);
1154     if (rc) {
1155         dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1156         goto probe_exit_endev;
1157     }
1158 
1159     rc = pci_request_regions(pdev, KBUILD_MODNAME);
1160     if (rc) {
1161         dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1162         goto probe_exit_pcireq;
1163     }
1164 
1165     addr = pci_iomap(pdev, 1, 0);
1166     if (!addr) {
1167         rc = -EIO;
1168         dev_err(&pdev->dev, "Failed pci_iomap\n");
1169         goto probe_exit_ipmap;
1170     }
1171 
1172     ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
1173     if (!ndev) {
1174         rc = -ENOMEM;
1175         dev_err(&pdev->dev, "Failed alloc_candev\n");
1176         goto probe_exit_alloc_candev;
1177     }
1178 
1179     priv = netdev_priv(ndev);
1180     priv->ndev = ndev;
1181     priv->regs = addr;
1182     priv->dev = pdev;
1183     priv->can.bittiming_const = &pch_can_bittiming_const;
1184     priv->can.do_set_mode = pch_can_do_set_mode;
1185     priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1186     priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1187                        CAN_CTRLMODE_LOOPBACK;
1188     priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
1189 
1190     ndev->irq = pdev->irq;
1191     ndev->flags |= IFF_ECHO;
1192 
1193     pci_set_drvdata(pdev, ndev);
1194     SET_NETDEV_DEV(ndev, &pdev->dev);
1195     ndev->netdev_ops = &pch_can_netdev_ops;
1196     ndev->ethtool_ops = &pch_can_ethtool_ops;
1197     priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1198 
1199     netif_napi_add_weight(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
1200 
1201     rc = pci_enable_msi(priv->dev);
1202     if (rc) {
1203         netdev_err(ndev, "PCH CAN opened without MSI\n");
1204         priv->use_msi = 0;
1205     } else {
1206         netdev_err(ndev, "PCH CAN opened with MSI\n");
1207         pci_set_master(pdev);
1208         priv->use_msi = 1;
1209     }
1210 
1211     rc = register_candev(ndev);
1212     if (rc) {
1213         dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1214         goto probe_exit_reg_candev;
1215     }
1216 
1217     return 0;
1218 
1219 probe_exit_reg_candev:
1220     if (priv->use_msi)
1221         pci_disable_msi(priv->dev);
1222     free_candev(ndev);
1223 probe_exit_alloc_candev:
1224     pci_iounmap(pdev, addr);
1225 probe_exit_ipmap:
1226     pci_release_regions(pdev);
1227 probe_exit_pcireq:
1228     pci_disable_device(pdev);
1229 probe_exit_endev:
1230     return rc;
1231 }
1232 
1233 static SIMPLE_DEV_PM_OPS(pch_can_pm_ops,
1234              pch_can_suspend,
1235              pch_can_resume);
1236 
1237 static struct pci_driver pch_can_pci_driver = {
1238     .name = "pch_can",
1239     .id_table = pch_pci_tbl,
1240     .probe = pch_can_probe,
1241     .remove = pch_can_remove,
1242     .driver.pm = &pch_can_pm_ops,
1243 };
1244 
1245 module_pci_driver(pch_can_pci_driver);
1246 
1247 MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
1248 MODULE_LICENSE("GPL v2");
1249 MODULE_VERSION("0.94");
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