can/mscan/mscan.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Definitions of consts/structs to drive the Freescale MSCAN.
0004  *
0005  * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
0006  *                         Varma Electronics Oy
0007  */
0008
0009 #ifndef __MSCAN_H__
0010 #define __MSCAN_H__
0011
0012 #include <linux/clk.h>
0013 #include <linux/types.h>
0014
0015 /* MSCAN control register 0 (CANCTL0) bits */
0016 #define MSCAN_RXFRM     0x80
0017 #define MSCAN_RXACT     0x40
0018 #define MSCAN_CSWAI     0x20
0019 #define MSCAN_SYNCH     0x10
0020 #define MSCAN_TIME      0x08
0021 #define MSCAN_WUPE      0x04
0022 #define MSCAN_SLPRQ     0x02
0023 #define MSCAN_INITRQ        0x01
0024
0025 /* MSCAN control register 1 (CANCTL1) bits */
0026 #define MSCAN_CANE      0x80
0027 #define MSCAN_CLKSRC        0x40
0028 #define MSCAN_LOOPB     0x20
0029 #define MSCAN_LISTEN        0x10
0030 #define MSCAN_BORM      0x08
0031 #define MSCAN_WUPM      0x04
0032 #define MSCAN_SLPAK     0x02
0033 #define MSCAN_INITAK        0x01
0034
0035 /* Use the MPC5XXX MSCAN variant? */
0036 #ifdef CONFIG_PPC
0037 #define MSCAN_FOR_MPC5XXX
0038 #endif
0039
0040 #ifdef MSCAN_FOR_MPC5XXX
0041 #define MSCAN_CLKSRC_BUS    0
0042 #define MSCAN_CLKSRC_XTAL   MSCAN_CLKSRC
0043 #define MSCAN_CLKSRC_IPS    MSCAN_CLKSRC
0044 #else
0045 #define MSCAN_CLKSRC_BUS    MSCAN_CLKSRC
0046 #define MSCAN_CLKSRC_XTAL   0
0047 #endif
0048
0049 /* MSCAN receiver flag register (CANRFLG) bits */
0050 #define MSCAN_WUPIF     0x80
0051 #define MSCAN_CSCIF     0x40
0052 #define MSCAN_RSTAT1        0x20
0053 #define MSCAN_RSTAT0        0x10
0054 #define MSCAN_TSTAT1        0x08
0055 #define MSCAN_TSTAT0        0x04
0056 #define MSCAN_OVRIF     0x02
0057 #define MSCAN_RXF       0x01
0058 #define MSCAN_ERR_IF        (MSCAN_OVRIF | MSCAN_CSCIF)
0059 #define MSCAN_RSTAT_MSK     (MSCAN_RSTAT1 | MSCAN_RSTAT0)
0060 #define MSCAN_TSTAT_MSK     (MSCAN_TSTAT1 | MSCAN_TSTAT0)
0061 #define MSCAN_STAT_MSK      (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
0062
0063 #define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
0064                  MSCAN_TSTAT1 | MSCAN_TSTAT0)
0065 #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
0066 #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
0067 #define MSCAN_STATE_ACTIVE  0
0068 #define MSCAN_STATE_WARNING 1
0069 #define MSCAN_STATE_PASSIVE 2
0070 #define MSCAN_STATE_BUSOFF  3
0071
0072 /* MSCAN receiver interrupt enable register (CANRIER) bits */
0073 #define MSCAN_WUPIE     0x80
0074 #define MSCAN_CSCIE     0x40
0075 #define MSCAN_RSTATE1       0x20
0076 #define MSCAN_RSTATE0       0x10
0077 #define MSCAN_TSTATE1       0x08
0078 #define MSCAN_TSTATE0       0x04
0079 #define MSCAN_OVRIE     0x02
0080 #define MSCAN_RXFIE     0x01
0081
0082 /* MSCAN transmitter flag register (CANTFLG) bits */
0083 #define MSCAN_TXE2      0x04
0084 #define MSCAN_TXE1      0x02
0085 #define MSCAN_TXE0      0x01
0086 #define MSCAN_TXE       (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
0087
0088 /* MSCAN transmitter interrupt enable register (CANTIER) bits */
0089 #define MSCAN_TXIE2     0x04
0090 #define MSCAN_TXIE1     0x02
0091 #define MSCAN_TXIE0     0x01
0092 #define MSCAN_TXIE      (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
0093
0094 /* MSCAN transmitter message abort request (CANTARQ) bits */
0095 #define MSCAN_ABTRQ2        0x04
0096 #define MSCAN_ABTRQ1        0x02
0097 #define MSCAN_ABTRQ0        0x01
0098
0099 /* MSCAN transmitter message abort ack (CANTAAK) bits */
0100 #define MSCAN_ABTAK2        0x04
0101 #define MSCAN_ABTAK1        0x02
0102 #define MSCAN_ABTAK0        0x01
0103
0104 /* MSCAN transmit buffer selection (CANTBSEL) bits */
0105 #define MSCAN_TX2       0x04
0106 #define MSCAN_TX1       0x02
0107 #define MSCAN_TX0       0x01
0108
0109 /* MSCAN ID acceptance control register (CANIDAC) bits */
0110 #define MSCAN_IDAM1     0x20
0111 #define MSCAN_IDAM0     0x10
0112 #define MSCAN_IDHIT2        0x04
0113 #define MSCAN_IDHIT1        0x02
0114 #define MSCAN_IDHIT0        0x01
0115
0116 #define MSCAN_AF_32BIT      0x00
0117 #define MSCAN_AF_16BIT      MSCAN_IDAM0
0118 #define MSCAN_AF_8BIT       MSCAN_IDAM1
0119 #define MSCAN_AF_CLOSED     (MSCAN_IDAM0|MSCAN_IDAM1)
0120 #define MSCAN_AF_MASK       (~(MSCAN_IDAM0|MSCAN_IDAM1))
0121
0122 /* MSCAN Miscellaneous Register (CANMISC) bits */
0123 #define MSCAN_BOHOLD        0x01
0124
0125 /* MSCAN Identifier Register (IDR) bits */
0126 #define MSCAN_SFF_RTR_SHIFT 4
0127 #define MSCAN_EFF_RTR_SHIFT 0
0128 #define MSCAN_EFF_FLAGS     0x18    /* IDE + SRR */
0129
0130 #ifdef MSCAN_FOR_MPC5XXX
0131 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
0132 #define _MSCAN_RESERVED_DSR_SIZE    2
0133 #else
0134 #define _MSCAN_RESERVED_(n, num)
0135 #define _MSCAN_RESERVED_DSR_SIZE    0
0136 #endif
0137
0138 /* Structure of the hardware registers */
0139 struct mscan_regs {
0140     /* (see doc S12MSCANV3/D)         MPC5200    MSCAN */
0141     u8 canctl0;             /* + 0x00     0x00 */
0142     u8 canctl1;             /* + 0x01     0x01 */
0143     _MSCAN_RESERVED_(1, 2);         /* + 0x02          */
0144     u8 canbtr0;             /* + 0x04     0x02 */
0145     u8 canbtr1;             /* + 0x05     0x03 */
0146     _MSCAN_RESERVED_(2, 2);         /* + 0x06          */
0147     u8 canrflg;             /* + 0x08     0x04 */
0148     u8 canrier;             /* + 0x09     0x05 */
0149     _MSCAN_RESERVED_(3, 2);         /* + 0x0a          */
0150     u8 cantflg;             /* + 0x0c     0x06 */
0151     u8 cantier;             /* + 0x0d     0x07 */
0152     _MSCAN_RESERVED_(4, 2);         /* + 0x0e          */
0153     u8 cantarq;             /* + 0x10     0x08 */
0154     u8 cantaak;             /* + 0x11     0x09 */
0155     _MSCAN_RESERVED_(5, 2);         /* + 0x12          */
0156     u8 cantbsel;                /* + 0x14     0x0a */
0157     u8 canidac;             /* + 0x15     0x0b */
0158     u8 reserved;                /* + 0x16     0x0c */
0159     _MSCAN_RESERVED_(6, 2);         /* + 0x17          */
0160     u8 canmisc;             /* + 0x19     0x0d */
0161     _MSCAN_RESERVED_(7, 2);         /* + 0x1a          */
0162     u8 canrxerr;                /* + 0x1c     0x0e */
0163     u8 cantxerr;                /* + 0x1d     0x0f */
0164     _MSCAN_RESERVED_(8, 2);         /* + 0x1e          */
0165     u16 canidar1_0;             /* + 0x20     0x10 */
0166     _MSCAN_RESERVED_(9, 2);         /* + 0x22          */
0167     u16 canidar3_2;             /* + 0x24     0x12 */
0168     _MSCAN_RESERVED_(10, 2);        /* + 0x26          */
0169     u16 canidmr1_0;             /* + 0x28     0x14 */
0170     _MSCAN_RESERVED_(11, 2);        /* + 0x2a          */
0171     u16 canidmr3_2;             /* + 0x2c     0x16 */
0172     _MSCAN_RESERVED_(12, 2);        /* + 0x2e          */
0173     u16 canidar5_4;             /* + 0x30     0x18 */
0174     _MSCAN_RESERVED_(13, 2);        /* + 0x32          */
0175     u16 canidar7_6;             /* + 0x34     0x1a */
0176     _MSCAN_RESERVED_(14, 2);        /* + 0x36          */
0177     u16 canidmr5_4;             /* + 0x38     0x1c */
0178     _MSCAN_RESERVED_(15, 2);        /* + 0x3a          */
0179     u16 canidmr7_6;             /* + 0x3c     0x1e */
0180     _MSCAN_RESERVED_(16, 2);        /* + 0x3e          */
0181     struct {
0182         u16 idr1_0;         /* + 0x40     0x20 */
0183         _MSCAN_RESERVED_(17, 2);    /* + 0x42          */
0184         u16 idr3_2;         /* + 0x44     0x22 */
0185         _MSCAN_RESERVED_(18, 2);    /* + 0x46          */
0186         u16 dsr1_0;         /* + 0x48     0x24 */
0187         _MSCAN_RESERVED_(19, 2);    /* + 0x4a          */
0188         u16 dsr3_2;         /* + 0x4c     0x26 */
0189         _MSCAN_RESERVED_(20, 2);    /* + 0x4e          */
0190         u16 dsr5_4;         /* + 0x50     0x28 */
0191         _MSCAN_RESERVED_(21, 2);    /* + 0x52          */
0192         u16 dsr7_6;         /* + 0x54     0x2a */
0193         _MSCAN_RESERVED_(22, 2);    /* + 0x56          */
0194         u8 dlr;             /* + 0x58     0x2c */
0195         u8 reserved;            /* + 0x59     0x2d */
0196         _MSCAN_RESERVED_(23, 2);    /* + 0x5a          */
0197         u16 time;           /* + 0x5c     0x2e */
0198     } rx;
0199     _MSCAN_RESERVED_(24, 2);        /* + 0x5e          */
0200     struct {
0201         u16 idr1_0;         /* + 0x60     0x30 */
0202         _MSCAN_RESERVED_(25, 2);    /* + 0x62          */
0203         u16 idr3_2;         /* + 0x64     0x32 */
0204         _MSCAN_RESERVED_(26, 2);    /* + 0x66          */
0205         u16 dsr1_0;         /* + 0x68     0x34 */
0206         _MSCAN_RESERVED_(27, 2);    /* + 0x6a          */
0207         u16 dsr3_2;         /* + 0x6c     0x36 */
0208         _MSCAN_RESERVED_(28, 2);    /* + 0x6e          */
0209         u16 dsr5_4;         /* + 0x70     0x38 */
0210         _MSCAN_RESERVED_(29, 2);    /* + 0x72          */
0211         u16 dsr7_6;         /* + 0x74     0x3a */
0212         _MSCAN_RESERVED_(30, 2);    /* + 0x76          */
0213         u8 dlr;             /* + 0x78     0x3c */
0214         u8 tbpr;            /* + 0x79     0x3d */
0215         _MSCAN_RESERVED_(31, 2);    /* + 0x7a          */
0216         u16 time;           /* + 0x7c     0x3e */
0217     } tx;
0218     _MSCAN_RESERVED_(32, 2);        /* + 0x7e          */
0219 } __packed;
0220
0221 #undef _MSCAN_RESERVED_
0222 #define MSCAN_REGION    sizeof(struct mscan)
0223
0224 #define MSCAN_NORMAL_MODE   0
0225 #define MSCAN_SLEEP_MODE    MSCAN_SLPRQ
0226 #define MSCAN_INIT_MODE     (MSCAN_INITRQ | MSCAN_SLPRQ)
0227 #define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ)
0228 #define MSCAN_SET_MODE_RETRIES  255
0229 #define MSCAN_ECHO_SKB_MAX  3
0230 #define MSCAN_RX_INTS_ENABLE    (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
0231                  MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
0232                  MSCAN_TSTATE1 | MSCAN_TSTATE0)
0233
0234 /* MSCAN type variants */
0235 enum {
0236     MSCAN_TYPE_MPC5200,
0237     MSCAN_TYPE_MPC5121
0238 };
0239
0240 #define BTR0_BRP_MASK       0x3f
0241 #define BTR0_SJW_SHIFT      6
0242 #define BTR0_SJW_MASK       (0x3 << BTR0_SJW_SHIFT)
0243
0244 #define BTR1_TSEG1_MASK     0xf
0245 #define BTR1_TSEG2_SHIFT    4
0246 #define BTR1_TSEG2_MASK     (0x7 << BTR1_TSEG2_SHIFT)
0247 #define BTR1_SAM_SHIFT      7
0248
0249 #define BTR0_SET_BRP(brp)   (((brp) - 1) & BTR0_BRP_MASK)
0250 #define BTR0_SET_SJW(sjw)   ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
0251                  BTR0_SJW_MASK)
0252
0253 #define BTR1_SET_TSEG1(tseg1)   (((tseg1) - 1) &  BTR1_TSEG1_MASK)
0254 #define BTR1_SET_TSEG2(tseg2)   ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
0255                  BTR1_TSEG2_MASK)
0256 #define BTR1_SET_SAM(sam)   ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
0257
0258 #define F_RX_PROGRESS   0
0259 #define F_TX_PROGRESS   1
0260 #define F_TX_WAIT_ALL   2
0261
0262 #define TX_QUEUE_SIZE   3
0263
0264 struct tx_queue_entry {
0265     struct list_head list;
0266     u8 mask;
0267     u8 id;
0268 };
0269
0270 struct mscan_priv {
0271     struct can_priv can;    /* must be the first member */
0272     unsigned int type;  /* MSCAN type variants */
0273     unsigned long flags;
0274     void __iomem *reg_base; /* ioremap'ed address to registers */
0275     struct clk *clk_ipg;    /* clock for registers */
0276     struct clk *clk_can;    /* clock for bitrates */
0277     u8 shadow_statflg;
0278     u8 shadow_canrier;
0279     u8 cur_pri;
0280     u8 prev_buf_id;
0281     u8 tx_active;
0282
0283     struct list_head tx_head;
0284     struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
0285     struct napi_struct napi;
0286 };
0287
0288 struct net_device *alloc_mscandev(void);
0289 int register_mscandev(struct net_device *dev, int mscan_clksrc);
0290 void unregister_mscandev(struct net_device *dev);
0291
0292 #endif /* __MSCAN_H__ */