can/mscan/mpc5xxx_can.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * CAN bus driver for the Freescale MPC5xxx embedded CPU.
0004  *
0005  * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
0006  *                         Varma Electronics Oy
0007  * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
0008  * Copyright (C) 2009 Wolfram Sang, Pengutronix <kernel@pengutronix.de>
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/netdevice.h>
0016 #include <linux/can/dev.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020 #include <sysdev/fsl_soc.h>
0021 #include <linux/clk.h>
0022 #include <linux/io.h>
0023 #include <asm/mpc52xx.h>
0024
0025 #include "mscan.h"
0026
0027 #define DRV_NAME "mpc5xxx_can"
0028
0029 struct mpc5xxx_can_data {
0030     unsigned int type;
0031     u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
0032              int *mscan_clksrc);
0033     void (*put_clock)(struct platform_device *ofdev);
0034 };
0035
0036 #ifdef CONFIG_PPC_MPC52xx
0037 static const struct of_device_id mpc52xx_cdm_ids[] = {
0038     { .compatible = "fsl,mpc5200-cdm", },
0039     {}
0040 };
0041
0042 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
0043                  const char *clock_name, int *mscan_clksrc)
0044 {
0045     unsigned int pvr;
0046     struct mpc52xx_cdm  __iomem *cdm;
0047     struct device_node *np_cdm;
0048     unsigned int freq;
0049     u32 val;
0050
0051     pvr = mfspr(SPRN_PVR);
0052
0053     /*
0054      * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
0055      * (IP_CLK) can be selected as MSCAN clock source. According to
0056      * the MPC5200 user's manual, the oscillator clock is the better
0057      * choice as it has less jitter. For this reason, it is selected
0058      * by default. Unfortunately, it can not be selected for the old
0059      * MPC5200 Rev. A chips due to a hardware bug (check errata).
0060      */
0061     if (clock_name && strcmp(clock_name, "ip") == 0)
0062         *mscan_clksrc = MSCAN_CLKSRC_BUS;
0063     else
0064         *mscan_clksrc = MSCAN_CLKSRC_XTAL;
0065
0066     freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
0067     if (!freq)
0068         return 0;
0069
0070     if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
0071         return freq;
0072
0073     /* Determine SYS_XTAL_IN frequency from the clock domain settings */
0074     np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
0075     if (!np_cdm) {
0076         dev_err(&ofdev->dev, "can't get clock node!\n");
0077         return 0;
0078     }
0079     cdm = of_iomap(np_cdm, 0);
0080     if (!cdm) {
0081         of_node_put(np_cdm);
0082         dev_err(&ofdev->dev, "can't map clock node!\n");
0083         return 0;
0084     }
0085
0086     if (in_8(&cdm->ipb_clk_sel) & 0x1)
0087         freq *= 2;
0088     val = in_be32(&cdm->rstcfg);
0089
0090     freq *= (val & (1 << 5)) ? 8 : 4;
0091     freq /= (val & (1 << 6)) ? 12 : 16;
0092
0093     of_node_put(np_cdm);
0094     iounmap(cdm);
0095
0096     return freq;
0097 }
0098 #else /* !CONFIG_PPC_MPC52xx */
0099 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
0100                  const char *clock_name, int *mscan_clksrc)
0101 {
0102     return 0;
0103 }
0104 #endif /* CONFIG_PPC_MPC52xx */
0105
0106 #ifdef CONFIG_PPC_MPC512x
0107 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
0108                  const char *clock_source, int *mscan_clksrc)
0109 {
0110     struct device_node *np;
0111     u32 clockdiv;
0112     enum {
0113         CLK_FROM_AUTO,
0114         CLK_FROM_IPS,
0115         CLK_FROM_SYS,
0116         CLK_FROM_REF,
0117     } clk_from;
0118     struct clk *clk_in, *clk_can;
0119     unsigned long freq_calc;
0120     struct mscan_priv *priv;
0121     struct clk *clk_ipg;
0122
0123     /* the caller passed in the clock source spec that was read from
0124      * the device tree, get the optional clock divider as well
0125      */
0126     np = ofdev->dev.of_node;
0127     clockdiv = 1;
0128     of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
0129     dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
0130         clock_source ? clock_source : "<NULL>", clockdiv);
0131
0132     /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
0133      * get set, and the 'ips' clock is the input to the MSCAN
0134      * component
0135      *
0136      * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
0137      * bit needs to get cleared, an optional clock-divider may have
0138      * been specified (the default value is 1), the appropriate
0139      * MSCAN related MCLK is the input to the MSCAN component
0140      *
0141      * in the absence of a clock-source spec, first an optimal clock
0142      * gets determined based on the 'sys' clock, if that fails the
0143      * 'ref' clock is used
0144      */
0145     clk_from = CLK_FROM_AUTO;
0146     if (clock_source) {
0147         /* interpret the device tree's spec for the clock source */
0148         if (!strcmp(clock_source, "ip"))
0149             clk_from = CLK_FROM_IPS;
0150         else if (!strcmp(clock_source, "sys"))
0151             clk_from = CLK_FROM_SYS;
0152         else if (!strcmp(clock_source, "ref"))
0153             clk_from = CLK_FROM_REF;
0154         else
0155             goto err_invalid;
0156         dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
0157     }
0158     if (clk_from == CLK_FROM_AUTO) {
0159         /* no spec so far, try the 'sys' clock; round to the
0160          * next MHz and see if we can get a multiple of 16MHz
0161          */
0162         dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
0163         clk_in = devm_clk_get(&ofdev->dev, "sys");
0164         if (IS_ERR(clk_in))
0165             goto err_notavail;
0166         freq_calc = clk_get_rate(clk_in);
0167         freq_calc +=  499999;
0168         freq_calc /= 1000000;
0169         freq_calc *= 1000000;
0170         if ((freq_calc % 16000000) == 0) {
0171             clk_from = CLK_FROM_SYS;
0172             clockdiv = freq_calc / 16000000;
0173             dev_dbg(&ofdev->dev,
0174                 "clk fit, sys[%lu] div[%d] freq[%lu]\n",
0175                 freq_calc, clockdiv, freq_calc / clockdiv);
0176         }
0177     }
0178     if (clk_from == CLK_FROM_AUTO) {
0179         /* no spec so far, use the 'ref' clock */
0180         dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
0181         clk_in = devm_clk_get(&ofdev->dev, "ref");
0182         if (IS_ERR(clk_in))
0183             goto err_notavail;
0184         clk_from = CLK_FROM_REF;
0185         freq_calc = clk_get_rate(clk_in);
0186         dev_dbg(&ofdev->dev,
0187             "clk fit, ref[%lu] (no div) freq[%lu]\n",
0188             freq_calc, freq_calc);
0189     }
0190
0191     /* select IPS or MCLK as the MSCAN input (returned to the caller),
0192      * setup the MCLK mux source and rate if applicable, apply the
0193      * optionally specified or derived above divider, and determine
0194      * the actual resulting clock rate to return to the caller
0195      */
0196     switch (clk_from) {
0197     case CLK_FROM_IPS:
0198         clk_can = devm_clk_get(&ofdev->dev, "ips");
0199         if (IS_ERR(clk_can))
0200             goto err_notavail;
0201         priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
0202         priv->clk_can = clk_can;
0203         freq_calc = clk_get_rate(clk_can);
0204         *mscan_clksrc = MSCAN_CLKSRC_IPS;
0205         dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
0206             *mscan_clksrc, freq_calc);
0207         break;
0208     case CLK_FROM_SYS:
0209     case CLK_FROM_REF:
0210         clk_can = devm_clk_get(&ofdev->dev, "mclk");
0211         if (IS_ERR(clk_can))
0212             goto err_notavail;
0213         priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
0214         priv->clk_can = clk_can;
0215         if (clk_from == CLK_FROM_SYS)
0216             clk_in = devm_clk_get(&ofdev->dev, "sys");
0217         if (clk_from == CLK_FROM_REF)
0218             clk_in = devm_clk_get(&ofdev->dev, "ref");
0219         if (IS_ERR(clk_in))
0220             goto err_notavail;
0221         clk_set_parent(clk_can, clk_in);
0222         freq_calc = clk_get_rate(clk_in);
0223         freq_calc /= clockdiv;
0224         clk_set_rate(clk_can, freq_calc);
0225         freq_calc = clk_get_rate(clk_can);
0226         *mscan_clksrc = MSCAN_CLKSRC_BUS;
0227         dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
0228             *mscan_clksrc, freq_calc);
0229         break;
0230     default:
0231         goto err_invalid;
0232     }
0233
0234     /* the above clk_can item is used for the bitrate, access to
0235      * the peripheral's register set needs the clk_ipg item
0236      */
0237     clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
0238     if (IS_ERR(clk_ipg))
0239         goto err_notavail_ipg;
0240     if (clk_prepare_enable(clk_ipg))
0241         goto err_notavail_ipg;
0242     priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
0243     priv->clk_ipg = clk_ipg;
0244
0245     /* return the determined clock source rate */
0246     return freq_calc;
0247
0248 err_invalid:
0249     dev_err(&ofdev->dev, "invalid clock source specification\n");
0250     /* clock source rate could not get determined */
0251     return 0;
0252
0253 err_notavail:
0254     dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
0255     /* clock source rate could not get determined */
0256     return 0;
0257
0258 err_notavail_ipg:
0259     dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
0260     /* clock source rate could not get determined */
0261     return 0;
0262 }
0263
0264 static void mpc512x_can_put_clock(struct platform_device *ofdev)
0265 {
0266     struct mscan_priv *priv;
0267
0268     priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
0269     if (priv->clk_ipg)
0270         clk_disable_unprepare(priv->clk_ipg);
0271 }
0272 #else /* !CONFIG_PPC_MPC512x */
0273 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
0274                  const char *clock_name, int *mscan_clksrc)
0275 {
0276     return 0;
0277 }
0278 #define mpc512x_can_put_clock NULL
0279 #endif /* CONFIG_PPC_MPC512x */
0280
0281 static const struct of_device_id mpc5xxx_can_table[];
0282 static int mpc5xxx_can_probe(struct platform_device *ofdev)
0283 {
0284     const struct mpc5xxx_can_data *data;
0285     struct device_node *np = ofdev->dev.of_node;
0286     struct net_device *dev;
0287     struct mscan_priv *priv;
0288     void __iomem *base;
0289     const char *clock_name = NULL;
0290     int irq, mscan_clksrc = 0;
0291     int err = -ENOMEM;
0292
0293     data = of_device_get_match_data(&ofdev->dev);
0294     if (!data)
0295         return -EINVAL;
0296
0297     base = of_iomap(np, 0);
0298     if (!base)
0299         return dev_err_probe(&ofdev->dev, err, "couldn't ioremap\n");
0300
0301     irq = irq_of_parse_and_map(np, 0);
0302     if (!irq) {
0303         dev_err(&ofdev->dev, "no irq found\n");
0304         err = -ENODEV;
0305         goto exit_unmap_mem;
0306     }
0307
0308     dev = alloc_mscandev();
0309     if (!dev)
0310         goto exit_dispose_irq;
0311     platform_set_drvdata(ofdev, dev);
0312     SET_NETDEV_DEV(dev, &ofdev->dev);
0313
0314     priv = netdev_priv(dev);
0315     priv->reg_base = base;
0316     dev->irq = irq;
0317
0318     clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
0319
0320     priv->type = data->type;
0321     priv->can.clock.freq = data->get_clock(ofdev, clock_name,
0322                            &mscan_clksrc);
0323     if (!priv->can.clock.freq) {
0324         dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
0325         goto exit_free_mscan;
0326     }
0327
0328     err = register_mscandev(dev, mscan_clksrc);
0329     if (err) {
0330         dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
0331             DRV_NAME, err);
0332         goto exit_free_mscan;
0333     }
0334
0335     dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
0336          priv->reg_base, dev->irq, priv->can.clock.freq);
0337
0338     return 0;
0339
0340 exit_free_mscan:
0341     free_candev(dev);
0342 exit_dispose_irq:
0343     irq_dispose_mapping(irq);
0344 exit_unmap_mem:
0345     iounmap(base);
0346
0347     return err;
0348 }
0349
0350 static int mpc5xxx_can_remove(struct platform_device *ofdev)
0351 {
0352     const struct of_device_id *match;
0353     const struct mpc5xxx_can_data *data;
0354     struct net_device *dev = platform_get_drvdata(ofdev);
0355     struct mscan_priv *priv = netdev_priv(dev);
0356
0357     match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
0358     data = match ? match->data : NULL;
0359
0360     unregister_mscandev(dev);
0361     if (data && data->put_clock)
0362         data->put_clock(ofdev);
0363     iounmap(priv->reg_base);
0364     irq_dispose_mapping(dev->irq);
0365     free_candev(dev);
0366
0367     return 0;
0368 }
0369
0370 #ifdef CONFIG_PM
0371 static struct mscan_regs saved_regs;
0372 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
0373 {
0374     struct net_device *dev = platform_get_drvdata(ofdev);
0375     struct mscan_priv *priv = netdev_priv(dev);
0376     struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
0377
0378     _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
0379
0380     return 0;
0381 }
0382
0383 static int mpc5xxx_can_resume(struct platform_device *ofdev)
0384 {
0385     struct net_device *dev = platform_get_drvdata(ofdev);
0386     struct mscan_priv *priv = netdev_priv(dev);
0387     struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
0388
0389     regs->canctl0 |= MSCAN_INITRQ;
0390     while (!(regs->canctl1 & MSCAN_INITAK))
0391         udelay(10);
0392
0393     regs->canctl1 = saved_regs.canctl1;
0394     regs->canbtr0 = saved_regs.canbtr0;
0395     regs->canbtr1 = saved_regs.canbtr1;
0396     regs->canidac = saved_regs.canidac;
0397
0398     /* restore masks, buffers etc. */
0399     _memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
0400              sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
0401
0402     regs->canctl0 &= ~MSCAN_INITRQ;
0403     regs->cantbsel = saved_regs.cantbsel;
0404     regs->canrier = saved_regs.canrier;
0405     regs->cantier = saved_regs.cantier;
0406     regs->canctl0 = saved_regs.canctl0;
0407
0408     return 0;
0409 }
0410 #endif
0411
0412 static const struct mpc5xxx_can_data mpc5200_can_data = {
0413     .type = MSCAN_TYPE_MPC5200,
0414     .get_clock = mpc52xx_can_get_clock,
0415     /* .put_clock not applicable */
0416 };
0417
0418 static const struct mpc5xxx_can_data mpc5121_can_data = {
0419     .type = MSCAN_TYPE_MPC5121,
0420     .get_clock = mpc512x_can_get_clock,
0421     .put_clock = mpc512x_can_put_clock,
0422 };
0423
0424 static const struct of_device_id mpc5xxx_can_table[] = {
0425     { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
0426     /* Note that only MPC5121 Rev. 2 (and later) is supported */
0427     { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
0428     {},
0429 };
0430 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
0431
0432 static struct platform_driver mpc5xxx_can_driver = {
0433     .driver = {
0434         .name = "mpc5xxx_can",
0435         .of_match_table = mpc5xxx_can_table,
0436     },
0437     .probe = mpc5xxx_can_probe,
0438     .remove = mpc5xxx_can_remove,
0439 #ifdef CONFIG_PM
0440     .suspend = mpc5xxx_can_suspend,
0441     .resume = mpc5xxx_can_resume,
0442 #endif
0443 };
0444
0445 module_platform_driver(mpc5xxx_can_driver);
0446
0447 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
0448 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
0449 MODULE_LICENSE("GPL v2");