can/m_can/m_can.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* CAN bus driver for Bosch M_CAN controller
0003  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
0004  */
0005
0006 #ifndef _CAN_M_CAN_H_
0007 #define _CAN_M_CAN_H_
0008
0009 #include <linux/can/core.h>
0010 #include <linux/can/rx-offload.h>
0011 #include <linux/completion.h>
0012 #include <linux/device.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/freezer.h>
0015 #include <linux/slab.h>
0016 #include <linux/uaccess.h>
0017 #include <linux/clk.h>
0018 #include <linux/delay.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/io.h>
0021 #include <linux/kernel.h>
0022 #include <linux/module.h>
0023 #include <linux/netdevice.h>
0024 #include <linux/of.h>
0025 #include <linux/of_device.h>
0026 #include <linux/pm_runtime.h>
0027 #include <linux/iopoll.h>
0028 #include <linux/can/dev.h>
0029 #include <linux/pinctrl/consumer.h>
0030 #include <linux/phy/phy.h>
0031
0032 /* m_can lec values */
0033 enum m_can_lec_type {
0034     LEC_NO_ERROR = 0,
0035     LEC_STUFF_ERROR,
0036     LEC_FORM_ERROR,
0037     LEC_ACK_ERROR,
0038     LEC_BIT1_ERROR,
0039     LEC_BIT0_ERROR,
0040     LEC_CRC_ERROR,
0041     LEC_UNUSED,
0042 };
0043
0044 enum m_can_mram_cfg {
0045     MRAM_SIDF = 0,
0046     MRAM_XIDF,
0047     MRAM_RXF0,
0048     MRAM_RXF1,
0049     MRAM_RXB,
0050     MRAM_TXE,
0051     MRAM_TXB,
0052     MRAM_CFG_NUM,
0053 };
0054
0055 /* address offset and element number for each FIFO/Buffer in the Message RAM */
0056 struct mram_cfg {
0057     u16 off;
0058     u8  num;
0059 };
0060
0061 struct m_can_classdev;
0062 struct m_can_ops {
0063     /* Device specific call backs */
0064     int (*clear_interrupts)(struct m_can_classdev *cdev);
0065     u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
0066     int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
0067     int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
0068     int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
0069               const void *val, size_t val_count);
0070     int (*init)(struct m_can_classdev *cdev);
0071 };
0072
0073 struct m_can_classdev {
0074     struct can_priv can;
0075     struct can_rx_offload offload;
0076     struct napi_struct napi;
0077     struct net_device *net;
0078     struct device *dev;
0079     struct clk *hclk;
0080     struct clk *cclk;
0081
0082     struct workqueue_struct *tx_wq;
0083     struct work_struct tx_work;
0084     struct sk_buff *tx_skb;
0085     struct phy *transceiver;
0086
0087     struct m_can_ops *ops;
0088
0089     int version;
0090     u32 irqstatus;
0091
0092     int pm_clock_support;
0093     int is_peripheral;
0094
0095     struct mram_cfg mcfg[MRAM_CFG_NUM];
0096 };
0097
0098 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
0099 void m_can_class_free_dev(struct net_device *net);
0100 int m_can_class_register(struct m_can_classdev *cdev);
0101 void m_can_class_unregister(struct m_can_classdev *cdev);
0102 int m_can_class_get_clocks(struct m_can_classdev *cdev);
0103 int m_can_init_ram(struct m_can_classdev *priv);
0104
0105 int m_can_class_suspend(struct device *dev);
0106 int m_can_class_resume(struct device *dev);
0107 #endif  /* _CAN_M_H_ */