can/flexcan/flexcan.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  * flexcan.c - FLEXCAN CAN controller driver
0003  *
0004  * Copyright (c) 2005-2006 Varma Electronics Oy
0005  * Copyright (c) 2009 Sascha Hauer, Pengutronix
0006  * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
0007  * Copyright (c) 2014 David Jander, Protonic Holland
0008  * Copyright (C) 2022 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
0009  *
0010  * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
0011  *
0012  */
0013
0014 #ifndef _FLEXCAN_H
0015 #define _FLEXCAN_H
0016
0017 #include <linux/can/rx-offload.h>
0018
0019 /* FLEXCAN hardware feature flags
0020  *
0021  * Below is some version info we got:
0022  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
0023  *                                Filter? connected?  Passive detection  ption in MB Supported?
0024  * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
0025  *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
0026  *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
0027  *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
0028  *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
0029  *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
0030  *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
0031  *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
0032  *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
0033  *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
0034  *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
0035  *
0036  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
0037  */
0038
0039 /* [TR]WRN_INT not connected */
0040 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
0041  /* Disable RX FIFO Global mask */
0042 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
0043 /* Enable EACEN and RRS bit in ctrl2 */
0044 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3)
0045 /* Disable non-correctable errors interrupt and freeze mode */
0046 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
0047 /* Use mailboxes (not FIFO) for RX path */
0048 #define FLEXCAN_QUIRK_USE_RX_MAILBOX BIT(5)
0049 /* No interrupt for error passive */
0050 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
0051 /* default to BE register access */
0052 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
0053 /* Setup stop mode with GPR to support wakeup */
0054 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
0055 /* Support CAN-FD mode */
0056 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
0057 /* support memory detection and correction */
0058 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
0059 /* Setup stop mode with SCU firmware to support wakeup */
0060 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
0061 /* Setup 3 separate interrupts, main, boff and err */
0062 #define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
0063 /* Setup 16 mailboxes */
0064 #define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
0065 /* Device supports RX via mailboxes */
0066 #define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX BIT(14)
0067 /* Device supports RTR reception via mailboxes */
0068 #define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR BIT(15)
0069 /* Device supports RX via FIFO */
0070 #define FLEXCAN_QUIRK_SUPPPORT_RX_FIFO BIT(16)
0071
0072 struct flexcan_devtype_data {
0073     u32 quirks;     /* quirks needed for different IP cores */
0074 };
0075
0076 struct flexcan_stop_mode {
0077     struct regmap *gpr;
0078     u8 req_gpr;
0079     u8 req_bit;
0080 };
0081
0082 struct flexcan_priv {
0083     struct can_priv can;
0084     struct can_rx_offload offload;
0085     struct device *dev;
0086
0087     struct flexcan_regs __iomem *regs;
0088     struct flexcan_mb __iomem *tx_mb;
0089     struct flexcan_mb __iomem *tx_mb_reserved;
0090     u8 tx_mb_idx;
0091     u8 mb_count;
0092     u8 mb_size;
0093     u8 clk_src; /* clock source of CAN Protocol Engine */
0094     u8 scu_idx;
0095
0096     u64 rx_mask;
0097     u64 tx_mask;
0098     u32 reg_ctrl_default;
0099
0100     struct clk *clk_ipg;
0101     struct clk *clk_per;
0102     struct flexcan_devtype_data devtype_data;
0103     struct regulator *reg_xceiver;
0104     struct flexcan_stop_mode stm;
0105
0106     int irq_boff;
0107     int irq_err;
0108
0109     /* IPC handle when setup stop mode by System Controller firmware(scfw) */
0110     struct imx_sc_ipc *sc_ipc_handle;
0111
0112     /* Read and Write APIs */
0113     u32 (*read)(void __iomem *addr);
0114     void (*write)(u32 val, void __iomem *addr);
0115 };
0116
0117 extern const struct ethtool_ops flexcan_ethtool_ops;
0118
0119 static inline bool
0120 flexcan_supports_rx_mailbox(const struct flexcan_priv *priv)
0121 {
0122     const u32 quirks = priv->devtype_data.quirks;
0123
0124     return quirks & FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX;
0125 }
0126
0127 static inline bool
0128 flexcan_supports_rx_mailbox_rtr(const struct flexcan_priv *priv)
0129 {
0130     const u32 quirks = priv->devtype_data.quirks;
0131
0132     return (quirks & (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
0133               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
0134         (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
0135          FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR);
0136 }
0137
0138 static inline bool
0139 flexcan_supports_rx_fifo(const struct flexcan_priv *priv)
0140 {
0141     const u32 quirks = priv->devtype_data.quirks;
0142
0143     return quirks & FLEXCAN_QUIRK_SUPPPORT_RX_FIFO;
0144 }
0145
0146 static inline bool
0147 flexcan_active_rx_rtr(const struct flexcan_priv *priv)
0148 {
0149     const u32 quirks = priv->devtype_data.quirks;
0150
0151     if (quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
0152         if (quirks & FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)
0153             return true;
0154     } else {
0155         /*  RX-FIFO is always RTR capable */
0156         return true;
0157     }
0158
0159     return false;
0160 }
0161
0162
0163 #endif /* _FLEXCAN_H */