can/ctucanfd/ctucanfd_kregs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*******************************************************************************
0003  *
0004  * CTU CAN FD IP Core
0005  *
0006  * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
0007  * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
0008  * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
0009  * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
0010  *
0011  * Project advisors:
0012  *     Jiri Novak <jnovak@fel.cvut.cz>
0013  *     Pavel Pisa <pisa@cmp.felk.cvut.cz>
0014  *
0015  * Department of Measurement         (http://meas.fel.cvut.cz/)
0016  * Faculty of Electrical Engineering (http://www.fel.cvut.cz)
0017  * Czech Technical University        (http://www.cvut.cz/)
0018  ******************************************************************************/
0019
0020 /* This file is autogenerated, DO NOT EDIT! */
0021
0022 #ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
0023 #define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
0024
0025 #include <linux/bits.h>
0026
0027 /* CAN_Registers memory map */
0028 enum ctu_can_fd_can_registers {
0029     CTUCANFD_DEVICE_ID             = 0x0,
0030     CTUCANFD_VERSION               = 0x2,
0031     CTUCANFD_MODE                  = 0x4,
0032     CTUCANFD_SETTINGS              = 0x6,
0033     CTUCANFD_STATUS                = 0x8,
0034     CTUCANFD_COMMAND               = 0xc,
0035     CTUCANFD_INT_STAT             = 0x10,
0036     CTUCANFD_INT_ENA_SET          = 0x14,
0037     CTUCANFD_INT_ENA_CLR          = 0x18,
0038     CTUCANFD_INT_MASK_SET         = 0x1c,
0039     CTUCANFD_INT_MASK_CLR         = 0x20,
0040     CTUCANFD_BTR                  = 0x24,
0041     CTUCANFD_BTR_FD               = 0x28,
0042     CTUCANFD_EWL                  = 0x2c,
0043     CTUCANFD_ERP                  = 0x2d,
0044     CTUCANFD_FAULT_STATE          = 0x2e,
0045     CTUCANFD_REC                  = 0x30,
0046     CTUCANFD_TEC                  = 0x32,
0047     CTUCANFD_ERR_NORM             = 0x34,
0048     CTUCANFD_ERR_FD               = 0x36,
0049     CTUCANFD_CTR_PRES             = 0x38,
0050     CTUCANFD_FILTER_A_MASK        = 0x3c,
0051     CTUCANFD_FILTER_A_VAL         = 0x40,
0052     CTUCANFD_FILTER_B_MASK        = 0x44,
0053     CTUCANFD_FILTER_B_VAL         = 0x48,
0054     CTUCANFD_FILTER_C_MASK        = 0x4c,
0055     CTUCANFD_FILTER_C_VAL         = 0x50,
0056     CTUCANFD_FILTER_RAN_LOW       = 0x54,
0057     CTUCANFD_FILTER_RAN_HIGH      = 0x58,
0058     CTUCANFD_FILTER_CONTROL       = 0x5c,
0059     CTUCANFD_FILTER_STATUS        = 0x5e,
0060     CTUCANFD_RX_MEM_INFO          = 0x60,
0061     CTUCANFD_RX_POINTERS          = 0x64,
0062     CTUCANFD_RX_STATUS            = 0x68,
0063     CTUCANFD_RX_SETTINGS          = 0x6a,
0064     CTUCANFD_RX_DATA              = 0x6c,
0065     CTUCANFD_TX_STATUS            = 0x70,
0066     CTUCANFD_TX_COMMAND           = 0x74,
0067     CTUCANFD_TXTB_INFO            = 0x76,
0068     CTUCANFD_TX_PRIORITY          = 0x78,
0069     CTUCANFD_ERR_CAPT             = 0x7c,
0070     CTUCANFD_RETR_CTR             = 0x7d,
0071     CTUCANFD_ALC                  = 0x7e,
0072     CTUCANFD_TS_INFO              = 0x7f,
0073     CTUCANFD_TRV_DELAY            = 0x80,
0074     CTUCANFD_SSP_CFG              = 0x82,
0075     CTUCANFD_RX_FR_CTR            = 0x84,
0076     CTUCANFD_TX_FR_CTR            = 0x88,
0077     CTUCANFD_DEBUG_REGISTER       = 0x8c,
0078     CTUCANFD_YOLO_REG             = 0x90,
0079     CTUCANFD_TIMESTAMP_LOW        = 0x94,
0080     CTUCANFD_TIMESTAMP_HIGH       = 0x98,
0081     CTUCANFD_TXTB1_DATA_1        = 0x100,
0082     CTUCANFD_TXTB1_DATA_2        = 0x104,
0083     CTUCANFD_TXTB1_DATA_20       = 0x14c,
0084     CTUCANFD_TXTB2_DATA_1        = 0x200,
0085     CTUCANFD_TXTB2_DATA_2        = 0x204,
0086     CTUCANFD_TXTB2_DATA_20       = 0x24c,
0087     CTUCANFD_TXTB3_DATA_1        = 0x300,
0088     CTUCANFD_TXTB3_DATA_2        = 0x304,
0089     CTUCANFD_TXTB3_DATA_20       = 0x34c,
0090     CTUCANFD_TXTB4_DATA_1        = 0x400,
0091     CTUCANFD_TXTB4_DATA_2        = 0x404,
0092     CTUCANFD_TXTB4_DATA_20       = 0x44c,
0093 };
0094
0095 /* Control_registers memory region */
0096
0097 /*  DEVICE_ID VERSION registers */
0098 #define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
0099 #define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
0100 #define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
0101
0102 /*  MODE SETTINGS registers */
0103 #define REG_MODE_RST BIT(0)
0104 #define REG_MODE_BMM BIT(1)
0105 #define REG_MODE_STM BIT(2)
0106 #define REG_MODE_AFM BIT(3)
0107 #define REG_MODE_FDE BIT(4)
0108 #define REG_MODE_TTTM BIT(5)
0109 #define REG_MODE_ROM BIT(6)
0110 #define REG_MODE_ACF BIT(7)
0111 #define REG_MODE_TSTM BIT(8)
0112 #define REG_MODE_RXBAM BIT(9)
0113 #define REG_MODE_SAM BIT(11)
0114 #define REG_MODE_RTRLE BIT(16)
0115 #define REG_MODE_RTRTH GENMASK(20, 17)
0116 #define REG_MODE_ILBP BIT(21)
0117 #define REG_MODE_ENA BIT(22)
0118 #define REG_MODE_NISOFD BIT(23)
0119 #define REG_MODE_PEX BIT(24)
0120 #define REG_MODE_TBFBO BIT(25)
0121 #define REG_MODE_FDRF BIT(26)
0122
0123 /*  STATUS registers */
0124 #define REG_STATUS_RXNE BIT(0)
0125 #define REG_STATUS_DOR BIT(1)
0126 #define REG_STATUS_TXNF BIT(2)
0127 #define REG_STATUS_EFT BIT(3)
0128 #define REG_STATUS_RXS BIT(4)
0129 #define REG_STATUS_TXS BIT(5)
0130 #define REG_STATUS_EWL BIT(6)
0131 #define REG_STATUS_IDLE BIT(7)
0132 #define REG_STATUS_PEXS BIT(8)
0133 #define REG_STATUS_STCNT BIT(16)
0134
0135 /*  COMMAND registers */
0136 #define REG_COMMAND_RXRPMV BIT(1)
0137 #define REG_COMMAND_RRB BIT(2)
0138 #define REG_COMMAND_CDO BIT(3)
0139 #define REG_COMMAND_ERCRST BIT(4)
0140 #define REG_COMMAND_RXFCRST BIT(5)
0141 #define REG_COMMAND_TXFCRST BIT(6)
0142 #define REG_COMMAND_CPEXS BIT(7)
0143
0144 /*  INT_STAT registers */
0145 #define REG_INT_STAT_RXI BIT(0)
0146 #define REG_INT_STAT_TXI BIT(1)
0147 #define REG_INT_STAT_EWLI BIT(2)
0148 #define REG_INT_STAT_DOI BIT(3)
0149 #define REG_INT_STAT_FCSI BIT(4)
0150 #define REG_INT_STAT_ALI BIT(5)
0151 #define REG_INT_STAT_BEI BIT(6)
0152 #define REG_INT_STAT_OFI BIT(7)
0153 #define REG_INT_STAT_RXFI BIT(8)
0154 #define REG_INT_STAT_BSI BIT(9)
0155 #define REG_INT_STAT_RBNEI BIT(10)
0156 #define REG_INT_STAT_TXBHCI BIT(11)
0157
0158 /*  INT_ENA_SET registers */
0159 #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
0160
0161 /*  INT_ENA_CLR registers */
0162 #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
0163
0164 /*  INT_MASK_SET registers */
0165 #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
0166
0167 /*  INT_MASK_CLR registers */
0168 #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
0169
0170 /*  BTR registers */
0171 #define REG_BTR_PROP GENMASK(6, 0)
0172 #define REG_BTR_PH1 GENMASK(12, 7)
0173 #define REG_BTR_PH2 GENMASK(18, 13)
0174 #define REG_BTR_BRP GENMASK(26, 19)
0175 #define REG_BTR_SJW GENMASK(31, 27)
0176
0177 /*  BTR_FD registers */
0178 #define REG_BTR_FD_PROP_FD GENMASK(5, 0)
0179 #define REG_BTR_FD_PH1_FD GENMASK(11, 7)
0180 #define REG_BTR_FD_PH2_FD GENMASK(17, 13)
0181 #define REG_BTR_FD_BRP_FD GENMASK(26, 19)
0182 #define REG_BTR_FD_SJW_FD GENMASK(31, 27)
0183
0184 /*  EWL ERP FAULT_STATE registers */
0185 #define REG_EWL_EW_LIMIT GENMASK(7, 0)
0186 #define REG_EWL_ERP_LIMIT GENMASK(15, 8)
0187 #define REG_EWL_ERA BIT(16)
0188 #define REG_EWL_ERP BIT(17)
0189 #define REG_EWL_BOF BIT(18)
0190
0191 /*  REC TEC registers */
0192 #define REG_REC_REC_VAL GENMASK(8, 0)
0193 #define REG_REC_TEC_VAL GENMASK(24, 16)
0194
0195 /*  ERR_NORM ERR_FD registers */
0196 #define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
0197 #define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
0198
0199 /*  CTR_PRES registers */
0200 #define REG_CTR_PRES_CTPV GENMASK(8, 0)
0201 #define REG_CTR_PRES_PTX BIT(9)
0202 #define REG_CTR_PRES_PRX BIT(10)
0203 #define REG_CTR_PRES_ENORM BIT(11)
0204 #define REG_CTR_PRES_EFD BIT(12)
0205
0206 /*  FILTER_A_MASK registers */
0207 #define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
0208
0209 /*  FILTER_A_VAL registers */
0210 #define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
0211
0212 /*  FILTER_B_MASK registers */
0213 #define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
0214
0215 /*  FILTER_B_VAL registers */
0216 #define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
0217
0218 /*  FILTER_C_MASK registers */
0219 #define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
0220
0221 /*  FILTER_C_VAL registers */
0222 #define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
0223
0224 /*  FILTER_RAN_LOW registers */
0225 #define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
0226
0227 /*  FILTER_RAN_HIGH registers */
0228 #define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
0229
0230 /*  FILTER_CONTROL FILTER_STATUS registers */
0231 #define REG_FILTER_CONTROL_FANB BIT(0)
0232 #define REG_FILTER_CONTROL_FANE BIT(1)
0233 #define REG_FILTER_CONTROL_FAFB BIT(2)
0234 #define REG_FILTER_CONTROL_FAFE BIT(3)
0235 #define REG_FILTER_CONTROL_FBNB BIT(4)
0236 #define REG_FILTER_CONTROL_FBNE BIT(5)
0237 #define REG_FILTER_CONTROL_FBFB BIT(6)
0238 #define REG_FILTER_CONTROL_FBFE BIT(7)
0239 #define REG_FILTER_CONTROL_FCNB BIT(8)
0240 #define REG_FILTER_CONTROL_FCNE BIT(9)
0241 #define REG_FILTER_CONTROL_FCFB BIT(10)
0242 #define REG_FILTER_CONTROL_FCFE BIT(11)
0243 #define REG_FILTER_CONTROL_FRNB BIT(12)
0244 #define REG_FILTER_CONTROL_FRNE BIT(13)
0245 #define REG_FILTER_CONTROL_FRFB BIT(14)
0246 #define REG_FILTER_CONTROL_FRFE BIT(15)
0247 #define REG_FILTER_CONTROL_SFA BIT(16)
0248 #define REG_FILTER_CONTROL_SFB BIT(17)
0249 #define REG_FILTER_CONTROL_SFC BIT(18)
0250 #define REG_FILTER_CONTROL_SFR BIT(19)
0251
0252 /*  RX_MEM_INFO registers */
0253 #define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
0254 #define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
0255
0256 /*  RX_POINTERS registers */
0257 #define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
0258 #define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
0259
0260 /*  RX_STATUS RX_SETTINGS registers */
0261 #define REG_RX_STATUS_RXE BIT(0)
0262 #define REG_RX_STATUS_RXF BIT(1)
0263 #define REG_RX_STATUS_RXMOF BIT(2)
0264 #define REG_RX_STATUS_RXFRC GENMASK(14, 4)
0265 #define REG_RX_STATUS_RTSOP BIT(16)
0266
0267 /*  RX_DATA registers */
0268 #define REG_RX_DATA_RX_DATA GENMASK(31, 0)
0269
0270 /*  TX_STATUS registers */
0271 #define REG_TX_STATUS_TX1S GENMASK(3, 0)
0272 #define REG_TX_STATUS_TX2S GENMASK(7, 4)
0273 #define REG_TX_STATUS_TX3S GENMASK(11, 8)
0274 #define REG_TX_STATUS_TX4S GENMASK(15, 12)
0275 #define REG_TX_STATUS_TX5S GENMASK(19, 16)
0276 #define REG_TX_STATUS_TX6S GENMASK(23, 20)
0277 #define REG_TX_STATUS_TX7S GENMASK(27, 24)
0278 #define REG_TX_STATUS_TX8S GENMASK(31, 28)
0279
0280 /*  TX_COMMAND TXTB_INFO registers */
0281 #define REG_TX_COMMAND_TXCE BIT(0)
0282 #define REG_TX_COMMAND_TXCR BIT(1)
0283 #define REG_TX_COMMAND_TXCA BIT(2)
0284 #define REG_TX_COMMAND_TXB1 BIT(8)
0285 #define REG_TX_COMMAND_TXB2 BIT(9)
0286 #define REG_TX_COMMAND_TXB3 BIT(10)
0287 #define REG_TX_COMMAND_TXB4 BIT(11)
0288 #define REG_TX_COMMAND_TXB5 BIT(12)
0289 #define REG_TX_COMMAND_TXB6 BIT(13)
0290 #define REG_TX_COMMAND_TXB7 BIT(14)
0291 #define REG_TX_COMMAND_TXB8 BIT(15)
0292 #define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)
0293
0294 /*  TX_PRIORITY registers */
0295 #define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
0296 #define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
0297 #define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
0298 #define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
0299 #define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)
0300 #define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)
0301 #define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)
0302 #define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)
0303
0304 /*  ERR_CAPT RETR_CTR ALC TS_INFO registers */
0305 #define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
0306 #define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
0307 #define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
0308 #define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
0309 #define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
0310 #define REG_ERR_CAPT_TS_BITS GENMASK(29, 24)
0311
0312 /*  TRV_DELAY SSP_CFG registers */
0313 #define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
0314 #define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
0315 #define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
0316
0317 /*  RX_FR_CTR registers */
0318 #define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
0319
0320 /*  TX_FR_CTR registers */
0321 #define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
0322
0323 /*  DEBUG_REGISTER registers */
0324 #define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
0325 #define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
0326 #define REG_DEBUG_REGISTER_PC_ARB BIT(6)
0327 #define REG_DEBUG_REGISTER_PC_CON BIT(7)
0328 #define REG_DEBUG_REGISTER_PC_DAT BIT(8)
0329 #define REG_DEBUG_REGISTER_PC_STC BIT(9)
0330 #define REG_DEBUG_REGISTER_PC_CRC BIT(10)
0331 #define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
0332 #define REG_DEBUG_REGISTER_PC_ACK BIT(12)
0333 #define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
0334 #define REG_DEBUG_REGISTER_PC_EOF BIT(14)
0335 #define REG_DEBUG_REGISTER_PC_INT BIT(15)
0336 #define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
0337 #define REG_DEBUG_REGISTER_PC_OVR BIT(17)
0338 #define REG_DEBUG_REGISTER_PC_SOF BIT(18)
0339
0340 /*  YOLO_REG registers */
0341 #define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
0342
0343 /*  TIMESTAMP_LOW registers */
0344 #define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
0345
0346 /*  TIMESTAMP_HIGH registers */
0347 #define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
0348
0349 #endif