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0001 /*
0002  * Platform CAN bus driver for Bosch C_CAN controller
0003  *
0004  * Copyright (C) 2010 ST Microelectronics
0005  * Bhupesh Sharma <bhupesh.sharma@st.com>
0006  *
0007  * Borrowed heavily from the C_CAN driver originally written by:
0008  * Copyright (C) 2007
0009  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
0010  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
0011  *
0012  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
0013  * Bosch C_CAN user manual can be obtained from:
0014  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
0015  * users_manual_c_can.pdf
0016  *
0017  * This file is licensed under the terms of the GNU General Public
0018  * License version 2. This program is licensed "as is" without any
0019  * warranty of any kind, whether express or implied.
0020  */
0021 
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/delay.h>
0026 #include <linux/netdevice.h>
0027 #include <linux/if_arp.h>
0028 #include <linux/if_ether.h>
0029 #include <linux/list.h>
0030 #include <linux/io.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/pm_runtime.h>
0033 #include <linux/clk.h>
0034 #include <linux/of.h>
0035 #include <linux/of_device.h>
0036 #include <linux/mfd/syscon.h>
0037 #include <linux/regmap.h>
0038 
0039 #include <linux/can/dev.h>
0040 
0041 #include "c_can.h"
0042 
0043 #define DCAN_RAM_INIT_BIT BIT(3)
0044 
0045 static DEFINE_SPINLOCK(raminit_lock);
0046 
0047 /* 16-bit c_can registers can be arranged differently in the memory
0048  * architecture of different implementations. For example: 16-bit
0049  * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
0050  * Handle the same by providing a common read/write interface.
0051  */
0052 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
0053                         enum reg index)
0054 {
0055     return readw(priv->base + priv->regs[index]);
0056 }
0057 
0058 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
0059                           enum reg index, u16 val)
0060 {
0061     writew(val, priv->base + priv->regs[index]);
0062 }
0063 
0064 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
0065                         enum reg index)
0066 {
0067     return readw(priv->base + 2 * priv->regs[index]);
0068 }
0069 
0070 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
0071                           enum reg index, u16 val)
0072 {
0073     writew(val, priv->base + 2 * priv->regs[index]);
0074 }
0075 
0076 static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
0077                      u32 mask, u32 val)
0078 {
0079     const struct c_can_raminit *raminit = &priv->raminit_sys;
0080     int timeout = 0;
0081     u32 ctrl = 0;
0082 
0083     /* We look only at the bits of our instance. */
0084     val &= mask;
0085     do {
0086         udelay(1);
0087         timeout++;
0088 
0089         regmap_read(raminit->syscon, raminit->reg, &ctrl);
0090         if (timeout == 1000) {
0091             dev_err(&priv->dev->dev, "%s: time out\n", __func__);
0092             break;
0093         }
0094     } while ((ctrl & mask) != val);
0095 }
0096 
0097 static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
0098 {
0099     const struct c_can_raminit *raminit = &priv->raminit_sys;
0100     u32 ctrl = 0;
0101     u32 mask;
0102 
0103     spin_lock(&raminit_lock);
0104 
0105     mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
0106     regmap_read(raminit->syscon, raminit->reg, &ctrl);
0107 
0108     /* We clear the start bit first. The start bit is
0109      * looking at the 0 -> transition, but is not self clearing;
0110      * NOTE: DONE must be written with 1 to clear it.
0111      * We can't clear the DONE bit here using regmap_update_bits()
0112      * as it will bypass the write if initial condition is START:0 DONE:1
0113      * e.g. on DRA7 which needs START pulse.
0114      */
0115     ctrl &= ~mask;  /* START = 0, DONE = 0 */
0116     regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
0117 
0118     /* check if START bit is 0. Ignore DONE bit for now
0119      * as it can be either 0 or 1.
0120      */
0121     c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl);
0122 
0123     if (enable) {
0124         /* Clear DONE bit & set START bit. */
0125         ctrl |= 1 << raminit->bits.start;
0126         /* DONE must be written with 1 to clear it */
0127         ctrl |= 1 << raminit->bits.done;
0128         regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
0129         /* prevent further clearing of DONE bit */
0130         ctrl &= ~(1 << raminit->bits.done);
0131         /* clear START bit if start pulse is needed */
0132         if (raminit->needs_pulse) {
0133             ctrl &= ~(1 << raminit->bits.start);
0134             regmap_update_bits(raminit->syscon, raminit->reg,
0135                        mask, ctrl);
0136         }
0137 
0138         ctrl |= 1 << raminit->bits.done;
0139         c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
0140     }
0141     spin_unlock(&raminit_lock);
0142 }
0143 
0144 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
0145 {
0146     u32 val;
0147 
0148     val = priv->read_reg(priv, index);
0149     val |= ((u32)priv->read_reg(priv, index + 1)) << 16;
0150 
0151     return val;
0152 }
0153 
0154 static void c_can_plat_write_reg32(const struct c_can_priv *priv,
0155                    enum reg index, u32 val)
0156 {
0157     priv->write_reg(priv, index + 1, val >> 16);
0158     priv->write_reg(priv, index, val);
0159 }
0160 
0161 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
0162 {
0163     return readl(priv->base + priv->regs[index]);
0164 }
0165 
0166 static void d_can_plat_write_reg32(const struct c_can_priv *priv,
0167                    enum reg index, u32 val)
0168 {
0169     writel(val, priv->base + priv->regs[index]);
0170 }
0171 
0172 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
0173 {
0174     while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
0175         udelay(1);
0176 }
0177 
0178 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
0179 {
0180     u32 ctrl;
0181 
0182     ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
0183     ctrl &= ~DCAN_RAM_INIT_BIT;
0184     priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
0185     c_can_hw_raminit_wait(priv, ctrl);
0186 
0187     if (enable) {
0188         ctrl |= DCAN_RAM_INIT_BIT;
0189         priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
0190         c_can_hw_raminit_wait(priv, ctrl);
0191     }
0192 }
0193 
0194 static const struct c_can_driver_data c_can_drvdata = {
0195     .id = BOSCH_C_CAN,
0196     .msg_obj_num = 32,
0197 };
0198 
0199 static const struct c_can_driver_data d_can_drvdata = {
0200     .id = BOSCH_D_CAN,
0201     .msg_obj_num = 32,
0202 };
0203 
0204 static const struct raminit_bits dra7_raminit_bits[] = {
0205     [0] = { .start = 3, .done = 1, },
0206     [1] = { .start = 5, .done = 2, },
0207 };
0208 
0209 static const struct c_can_driver_data dra7_dcan_drvdata = {
0210     .id = BOSCH_D_CAN,
0211     .msg_obj_num = 64,
0212     .raminit_num = ARRAY_SIZE(dra7_raminit_bits),
0213     .raminit_bits = dra7_raminit_bits,
0214     .raminit_pulse = true,
0215 };
0216 
0217 static const struct raminit_bits am3352_raminit_bits[] = {
0218     [0] = { .start = 0, .done = 8, },
0219     [1] = { .start = 1, .done = 9, },
0220 };
0221 
0222 static const struct c_can_driver_data am3352_dcan_drvdata = {
0223     .id = BOSCH_D_CAN,
0224     .msg_obj_num = 64,
0225     .raminit_num = ARRAY_SIZE(am3352_raminit_bits),
0226     .raminit_bits = am3352_raminit_bits,
0227 };
0228 
0229 static const struct platform_device_id c_can_id_table[] = {
0230     {
0231         .name = KBUILD_MODNAME,
0232         .driver_data = (kernel_ulong_t)&c_can_drvdata,
0233     },
0234     {
0235         .name = "c_can",
0236         .driver_data = (kernel_ulong_t)&c_can_drvdata,
0237     },
0238     {
0239         .name = "d_can",
0240         .driver_data = (kernel_ulong_t)&d_can_drvdata,
0241     },
0242     { /* sentinel */ },
0243 };
0244 MODULE_DEVICE_TABLE(platform, c_can_id_table);
0245 
0246 static const struct of_device_id c_can_of_table[] = {
0247     { .compatible = "bosch,c_can", .data = &c_can_drvdata },
0248     { .compatible = "bosch,d_can", .data = &d_can_drvdata },
0249     { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
0250     { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
0251     { .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
0252     { /* sentinel */ },
0253 };
0254 MODULE_DEVICE_TABLE(of, c_can_of_table);
0255 
0256 static int c_can_plat_probe(struct platform_device *pdev)
0257 {
0258     int ret;
0259     void __iomem *addr;
0260     struct net_device *dev;
0261     struct c_can_priv *priv;
0262     const struct of_device_id *match;
0263     struct resource *mem;
0264     int irq;
0265     struct clk *clk;
0266     const struct c_can_driver_data *drvdata;
0267     struct device_node *np = pdev->dev.of_node;
0268 
0269     match = of_match_device(c_can_of_table, &pdev->dev);
0270     if (match) {
0271         drvdata = match->data;
0272     } else if (pdev->id_entry->driver_data) {
0273         drvdata = (struct c_can_driver_data *)
0274             platform_get_device_id(pdev)->driver_data;
0275     } else {
0276         return -ENODEV;
0277     }
0278 
0279     /* get the appropriate clk */
0280     clk = devm_clk_get(&pdev->dev, NULL);
0281     if (IS_ERR(clk)) {
0282         ret = PTR_ERR(clk);
0283         goto exit;
0284     }
0285 
0286     /* get the platform data */
0287     irq = platform_get_irq(pdev, 0);
0288     if (irq <= 0) {
0289         ret = -ENODEV;
0290         goto exit;
0291     }
0292 
0293     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0294     addr = devm_ioremap_resource(&pdev->dev, mem);
0295     if (IS_ERR(addr)) {
0296         ret =  PTR_ERR(addr);
0297         goto exit;
0298     }
0299 
0300     /* allocate the c_can device */
0301     dev = alloc_c_can_dev(drvdata->msg_obj_num);
0302     if (!dev) {
0303         ret = -ENOMEM;
0304         goto exit;
0305     }
0306 
0307     priv = netdev_priv(dev);
0308     switch (drvdata->id) {
0309     case BOSCH_C_CAN:
0310         priv->regs = reg_map_c_can;
0311         switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
0312         case IORESOURCE_MEM_32BIT:
0313             priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
0314             priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
0315             priv->read_reg32 = c_can_plat_read_reg32;
0316             priv->write_reg32 = c_can_plat_write_reg32;
0317             break;
0318         case IORESOURCE_MEM_16BIT:
0319         default:
0320             priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
0321             priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
0322             priv->read_reg32 = c_can_plat_read_reg32;
0323             priv->write_reg32 = c_can_plat_write_reg32;
0324             break;
0325         }
0326         break;
0327     case BOSCH_D_CAN:
0328         priv->regs = reg_map_d_can;
0329         priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
0330         priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
0331         priv->read_reg32 = d_can_plat_read_reg32;
0332         priv->write_reg32 = d_can_plat_write_reg32;
0333 
0334         /* Check if we need custom RAMINIT via syscon. Mostly for TI
0335          * platforms. Only supported with DT boot.
0336          */
0337         if (np && of_property_read_bool(np, "syscon-raminit")) {
0338             u32 id;
0339             struct c_can_raminit *raminit = &priv->raminit_sys;
0340 
0341             ret = -EINVAL;
0342             raminit->syscon = syscon_regmap_lookup_by_phandle(np,
0343                                       "syscon-raminit");
0344             if (IS_ERR(raminit->syscon)) {
0345                 /* can fail with -EPROBE_DEFER */
0346                 ret = PTR_ERR(raminit->syscon);
0347                 free_c_can_dev(dev);
0348                 return ret;
0349             }
0350 
0351             if (of_property_read_u32_index(np, "syscon-raminit", 1,
0352                                &raminit->reg)) {
0353                 dev_err(&pdev->dev,
0354                     "couldn't get the RAMINIT reg. offset!\n");
0355                 goto exit_free_device;
0356             }
0357 
0358             if (of_property_read_u32_index(np, "syscon-raminit", 2,
0359                                &id)) {
0360                 dev_err(&pdev->dev,
0361                     "couldn't get the CAN instance ID\n");
0362                 goto exit_free_device;
0363             }
0364 
0365             if (id >= drvdata->raminit_num) {
0366                 dev_err(&pdev->dev,
0367                     "Invalid CAN instance ID\n");
0368                 goto exit_free_device;
0369             }
0370 
0371             raminit->bits = drvdata->raminit_bits[id];
0372             raminit->needs_pulse = drvdata->raminit_pulse;
0373 
0374             priv->raminit = c_can_hw_raminit_syscon;
0375         } else {
0376             priv->raminit = c_can_hw_raminit;
0377         }
0378         break;
0379     default:
0380         ret = -EINVAL;
0381         goto exit_free_device;
0382     }
0383 
0384     dev->irq = irq;
0385     priv->base = addr;
0386     priv->device = &pdev->dev;
0387     priv->can.clock.freq = clk_get_rate(clk);
0388     priv->type = drvdata->id;
0389 
0390     platform_set_drvdata(pdev, dev);
0391     SET_NETDEV_DEV(dev, &pdev->dev);
0392 
0393     pm_runtime_enable(priv->device);
0394     ret = register_c_can_dev(dev);
0395     if (ret) {
0396         dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
0397             KBUILD_MODNAME, ret);
0398         goto exit_free_device;
0399     }
0400 
0401     dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
0402          KBUILD_MODNAME, priv->base, dev->irq);
0403     return 0;
0404 
0405 exit_free_device:
0406     pm_runtime_disable(priv->device);
0407     free_c_can_dev(dev);
0408 exit:
0409     dev_err(&pdev->dev, "probe failed\n");
0410 
0411     return ret;
0412 }
0413 
0414 static int c_can_plat_remove(struct platform_device *pdev)
0415 {
0416     struct net_device *dev = platform_get_drvdata(pdev);
0417     struct c_can_priv *priv = netdev_priv(dev);
0418 
0419     unregister_c_can_dev(dev);
0420     pm_runtime_disable(priv->device);
0421     free_c_can_dev(dev);
0422 
0423     return 0;
0424 }
0425 
0426 #ifdef CONFIG_PM
0427 static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
0428 {
0429     int ret;
0430     struct net_device *ndev = platform_get_drvdata(pdev);
0431     struct c_can_priv *priv = netdev_priv(ndev);
0432 
0433     if (priv->type != BOSCH_D_CAN) {
0434         dev_warn(&pdev->dev, "Not supported\n");
0435         return 0;
0436     }
0437 
0438     if (netif_running(ndev)) {
0439         netif_stop_queue(ndev);
0440         netif_device_detach(ndev);
0441     }
0442 
0443     ret = c_can_power_down(ndev);
0444     if (ret) {
0445         netdev_err(ndev, "failed to enter power down mode\n");
0446         return ret;
0447     }
0448 
0449     priv->can.state = CAN_STATE_SLEEPING;
0450 
0451     return 0;
0452 }
0453 
0454 static int c_can_resume(struct platform_device *pdev)
0455 {
0456     int ret;
0457     struct net_device *ndev = platform_get_drvdata(pdev);
0458     struct c_can_priv *priv = netdev_priv(ndev);
0459 
0460     if (priv->type != BOSCH_D_CAN) {
0461         dev_warn(&pdev->dev, "Not supported\n");
0462         return 0;
0463     }
0464 
0465     ret = c_can_power_up(ndev);
0466     if (ret) {
0467         netdev_err(ndev, "Still in power down mode\n");
0468         return ret;
0469     }
0470 
0471     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0472 
0473     if (netif_running(ndev)) {
0474         netif_device_attach(ndev);
0475         netif_start_queue(ndev);
0476     }
0477 
0478     return 0;
0479 }
0480 #else
0481 #define c_can_suspend NULL
0482 #define c_can_resume NULL
0483 #endif
0484 
0485 static struct platform_driver c_can_plat_driver = {
0486     .driver = {
0487         .name = KBUILD_MODNAME,
0488         .of_match_table = c_can_of_table,
0489     },
0490     .probe = c_can_plat_probe,
0491     .remove = c_can_plat_remove,
0492     .suspend = c_can_suspend,
0493     .resume = c_can_resume,
0494     .id_table = c_can_id_table,
0495 };
0496 
0497 module_platform_driver(c_can_plat_driver);
0498 
0499 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
0500 MODULE_LICENSE("GPL v2");
0501 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
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