can/c_can/c_can_pci.c

0001 /*
0002  * PCI bus driver for Bosch C_CAN/D_CAN controller
0003  *
0004  * Copyright (C) 2012 Federico Vaga <federico.vaga@gmail.com>
0005  *
0006  * Borrowed from c_can_platform.c
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2. This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/netdevice.h>
0016 #include <linux/pci.h>
0017
0018 #include <linux/can/dev.h>
0019
0020 #include "c_can.h"
0021
0022 #define PCI_DEVICE_ID_PCH_CAN   0x8818
0023 #define PCH_PCI_SOFT_RESET  0x01fc
0024
0025 enum c_can_pci_reg_align {
0026     C_CAN_REG_ALIGN_16,
0027     C_CAN_REG_ALIGN_32,
0028     C_CAN_REG_32,
0029 };
0030
0031 struct c_can_pci_data {
0032     /* Specify if is C_CAN or D_CAN */
0033     enum c_can_dev_id type;
0034     /* Number of message objects */
0035     unsigned int msg_obj_num;
0036     /* Set the register alignment in the memory */
0037     enum c_can_pci_reg_align reg_align;
0038     /* Set the frequency */
0039     unsigned int freq;
0040     /* PCI bar number */
0041     int bar;
0042     /* Callback for reset */
0043     void (*init)(const struct c_can_priv *priv, bool enable);
0044 };
0045
0046 /* 16-bit c_can registers can be arranged differently in the memory
0047  * architecture of different implementations. For example: 16-bit
0048  * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
0049  * Handle the same by providing a common read/write interface.
0050  */
0051 static u16 c_can_pci_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
0052                            enum reg index)
0053 {
0054     return readw(priv->base + priv->regs[index]);
0055 }
0056
0057 static void c_can_pci_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
0058                          enum reg index, u16 val)
0059 {
0060     writew(val, priv->base + priv->regs[index]);
0061 }
0062
0063 static u16 c_can_pci_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
0064                            enum reg index)
0065 {
0066     return readw(priv->base + 2 * priv->regs[index]);
0067 }
0068
0069 static void c_can_pci_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
0070                          enum reg index, u16 val)
0071 {
0072     writew(val, priv->base + 2 * priv->regs[index]);
0073 }
0074
0075 static u16 c_can_pci_read_reg_32bit(const struct c_can_priv *priv,
0076                     enum reg index)
0077 {
0078     return (u16)ioread32(priv->base + 2 * priv->regs[index]);
0079 }
0080
0081 static void c_can_pci_write_reg_32bit(const struct c_can_priv *priv,
0082                       enum reg index, u16 val)
0083 {
0084     iowrite32((u32)val, priv->base + 2 * priv->regs[index]);
0085 }
0086
0087 static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index)
0088 {
0089     u32 val;
0090
0091     val = priv->read_reg(priv, index);
0092     val |= ((u32)priv->read_reg(priv, index + 1)) << 16;
0093
0094     return val;
0095 }
0096
0097 static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index,
0098                   u32 val)
0099 {
0100     priv->write_reg(priv, index + 1, val >> 16);
0101     priv->write_reg(priv, index, val);
0102 }
0103
0104 static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
0105 {
0106     if (enable) {
0107         u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
0108
0109         /* write to sw reset register */
0110         iowrite32(1, addr);
0111         iowrite32(0, addr);
0112     }
0113 }
0114
0115 static int c_can_pci_probe(struct pci_dev *pdev,
0116                const struct pci_device_id *ent)
0117 {
0118     struct c_can_pci_data *c_can_pci_data = (void *)ent->driver_data;
0119     struct c_can_priv *priv;
0120     struct net_device *dev;
0121     void __iomem *addr;
0122     int ret;
0123
0124     ret = pci_enable_device(pdev);
0125     if (ret) {
0126         dev_err(&pdev->dev, "pci_enable_device FAILED\n");
0127         goto out;
0128     }
0129
0130     ret = pci_request_regions(pdev, KBUILD_MODNAME);
0131     if (ret) {
0132         dev_err(&pdev->dev, "pci_request_regions FAILED\n");
0133         goto out_disable_device;
0134     }
0135
0136     ret = pci_enable_msi(pdev);
0137     if (!ret) {
0138         dev_info(&pdev->dev, "MSI enabled\n");
0139         pci_set_master(pdev);
0140     }
0141
0142     addr = pci_iomap(pdev, c_can_pci_data->bar,
0143              pci_resource_len(pdev, c_can_pci_data->bar));
0144     if (!addr) {
0145         dev_err(&pdev->dev,
0146             "device has no PCI memory resources, failing adapter\n");
0147         ret = -ENOMEM;
0148         goto out_release_regions;
0149     }
0150
0151     /* allocate the c_can device */
0152     dev = alloc_c_can_dev(c_can_pci_data->msg_obj_num);
0153     if (!dev) {
0154         ret = -ENOMEM;
0155         goto out_iounmap;
0156     }
0157
0158     priv = netdev_priv(dev);
0159     pci_set_drvdata(pdev, dev);
0160     SET_NETDEV_DEV(dev, &pdev->dev);
0161
0162     dev->irq = pdev->irq;
0163     priv->base = addr;
0164     priv->device = &pdev->dev;
0165
0166     if (!c_can_pci_data->freq) {
0167         dev_err(&pdev->dev, "no clock frequency defined\n");
0168         ret = -ENODEV;
0169         goto out_free_c_can;
0170     } else {
0171         priv->can.clock.freq = c_can_pci_data->freq;
0172     }
0173
0174     /* Configure CAN type */
0175     switch (c_can_pci_data->type) {
0176     case BOSCH_C_CAN:
0177         priv->regs = reg_map_c_can;
0178         break;
0179     case BOSCH_D_CAN:
0180         priv->regs = reg_map_d_can;
0181         break;
0182     default:
0183         ret = -EINVAL;
0184         goto out_free_c_can;
0185     }
0186
0187     priv->type = c_can_pci_data->type;
0188
0189     /* Configure access to registers */
0190     switch (c_can_pci_data->reg_align) {
0191     case C_CAN_REG_ALIGN_32:
0192         priv->read_reg = c_can_pci_read_reg_aligned_to_32bit;
0193         priv->write_reg = c_can_pci_write_reg_aligned_to_32bit;
0194         break;
0195     case C_CAN_REG_ALIGN_16:
0196         priv->read_reg = c_can_pci_read_reg_aligned_to_16bit;
0197         priv->write_reg = c_can_pci_write_reg_aligned_to_16bit;
0198         break;
0199     case C_CAN_REG_32:
0200         priv->read_reg = c_can_pci_read_reg_32bit;
0201         priv->write_reg = c_can_pci_write_reg_32bit;
0202         break;
0203     default:
0204         ret = -EINVAL;
0205         goto out_free_c_can;
0206     }
0207     priv->read_reg32 = c_can_pci_read_reg32;
0208     priv->write_reg32 = c_can_pci_write_reg32;
0209
0210     priv->raminit = c_can_pci_data->init;
0211
0212     ret = register_c_can_dev(dev);
0213     if (ret) {
0214         dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
0215             KBUILD_MODNAME, ret);
0216         goto out_free_c_can;
0217     }
0218
0219     dev_dbg(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
0220         KBUILD_MODNAME, priv->regs, dev->irq);
0221
0222     return 0;
0223
0224 out_free_c_can:
0225     free_c_can_dev(dev);
0226 out_iounmap:
0227     pci_iounmap(pdev, addr);
0228 out_release_regions:
0229     pci_disable_msi(pdev);
0230     pci_clear_master(pdev);
0231     pci_release_regions(pdev);
0232 out_disable_device:
0233     pci_disable_device(pdev);
0234 out:
0235     return ret;
0236 }
0237
0238 static void c_can_pci_remove(struct pci_dev *pdev)
0239 {
0240     struct net_device *dev = pci_get_drvdata(pdev);
0241     struct c_can_priv *priv = netdev_priv(dev);
0242     void __iomem *addr = priv->base;
0243
0244     unregister_c_can_dev(dev);
0245
0246     free_c_can_dev(dev);
0247
0248     pci_iounmap(pdev, addr);
0249     pci_disable_msi(pdev);
0250     pci_clear_master(pdev);
0251     pci_release_regions(pdev);
0252     pci_disable_device(pdev);
0253 }
0254
0255 static const struct c_can_pci_data c_can_sta2x11 = {
0256     .type = BOSCH_C_CAN,
0257     .msg_obj_num = 32,
0258     .reg_align = C_CAN_REG_ALIGN_32,
0259     .freq = 52000000, /* 52 Mhz */
0260     .bar = 0,
0261 };
0262
0263 static const struct c_can_pci_data c_can_pch = {
0264     .type = BOSCH_C_CAN,
0265     .msg_obj_num = 32,
0266     .reg_align = C_CAN_REG_32,
0267     .freq = 50000000, /* 50 MHz */
0268     .init = c_can_pci_reset_pch,
0269     .bar = 1,
0270 };
0271
0272 #define C_CAN_ID(_vend, _dev, _driverdata) {        \
0273     PCI_DEVICE(_vend, _dev),            \
0274     .driver_data = (unsigned long)&(_driverdata),   \
0275 }
0276
0277 static const struct pci_device_id c_can_pci_tbl[] = {
0278     C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN,
0279          c_can_sta2x11),
0280     C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN,
0281          c_can_pch),
0282     {},
0283 };
0284
0285 static struct pci_driver c_can_pci_driver = {
0286     .name = KBUILD_MODNAME,
0287     .id_table = c_can_pci_tbl,
0288     .probe = c_can_pci_probe,
0289     .remove = c_can_pci_remove,
0290 };
0291
0292 module_pci_driver(c_can_pci_driver);
0293
0294 MODULE_AUTHOR("Federico Vaga <federico.vaga@gmail.com>");
0295 MODULE_LICENSE("GPL v2");
0296 MODULE_DESCRIPTION("PCI CAN bus driver for Bosch C_CAN/D_CAN controller");
0297 MODULE_DEVICE_TABLE(pci, c_can_pci_tbl);