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0001 /*
0002  * CAN bus driver for Bosch C_CAN controller
0003  *
0004  * Copyright (C) 2010 ST Microelectronics
0005  * Bhupesh Sharma <bhupesh.sharma@st.com>
0006  *
0007  * Borrowed heavily from the C_CAN driver originally written by:
0008  * Copyright (C) 2007
0009  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
0010  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
0011  *
0012  * TX and RX NAPI implementation has been borrowed from at91 CAN driver
0013  * written by:
0014  * Copyright
0015  * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
0016  * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
0017  *
0018  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
0019  * Bosch C_CAN user manual can be obtained from:
0020  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
0021  * users_manual_c_can.pdf
0022  *
0023  * This file is licensed under the terms of the GNU General Public
0024  * License version 2. This program is licensed "as is" without any
0025  * warranty of any kind, whether express or implied.
0026  */
0027 
0028 #include <linux/kernel.h>
0029 #include <linux/module.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/delay.h>
0032 #include <linux/netdevice.h>
0033 #include <linux/if_arp.h>
0034 #include <linux/if_ether.h>
0035 #include <linux/list.h>
0036 #include <linux/io.h>
0037 #include <linux/pm_runtime.h>
0038 #include <linux/pinctrl/consumer.h>
0039 
0040 #include <linux/can.h>
0041 #include <linux/can/dev.h>
0042 #include <linux/can/error.h>
0043 
0044 #include "c_can.h"
0045 
0046 /* Number of interface registers */
0047 #define IF_ENUM_REG_LEN     11
0048 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
0049 
0050 /* control extension register D_CAN specific */
0051 #define CONTROL_EX_PDR      BIT(8)
0052 
0053 /* control register */
0054 #define CONTROL_SWR     BIT(15)
0055 #define CONTROL_TEST        BIT(7)
0056 #define CONTROL_CCE     BIT(6)
0057 #define CONTROL_DISABLE_AR  BIT(5)
0058 #define CONTROL_ENABLE_AR   (0 << 5)
0059 #define CONTROL_EIE     BIT(3)
0060 #define CONTROL_SIE     BIT(2)
0061 #define CONTROL_IE      BIT(1)
0062 #define CONTROL_INIT        BIT(0)
0063 
0064 #define CONTROL_IRQMSK      (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
0065 
0066 /* test register */
0067 #define TEST_RX         BIT(7)
0068 #define TEST_TX1        BIT(6)
0069 #define TEST_TX2        BIT(5)
0070 #define TEST_LBACK      BIT(4)
0071 #define TEST_SILENT     BIT(3)
0072 #define TEST_BASIC      BIT(2)
0073 
0074 /* status register */
0075 #define STATUS_PDA      BIT(10)
0076 #define STATUS_BOFF     BIT(7)
0077 #define STATUS_EWARN        BIT(6)
0078 #define STATUS_EPASS        BIT(5)
0079 #define STATUS_RXOK     BIT(4)
0080 #define STATUS_TXOK     BIT(3)
0081 
0082 /* error counter register */
0083 #define ERR_CNT_TEC_MASK    0xff
0084 #define ERR_CNT_TEC_SHIFT   0
0085 #define ERR_CNT_REC_SHIFT   8
0086 #define ERR_CNT_REC_MASK    (0x7f << ERR_CNT_REC_SHIFT)
0087 #define ERR_CNT_RP_SHIFT    15
0088 #define ERR_CNT_RP_MASK     (0x1 << ERR_CNT_RP_SHIFT)
0089 
0090 /* bit-timing register */
0091 #define BTR_BRP_MASK        0x3f
0092 #define BTR_BRP_SHIFT       0
0093 #define BTR_SJW_SHIFT       6
0094 #define BTR_SJW_MASK        (0x3 << BTR_SJW_SHIFT)
0095 #define BTR_TSEG1_SHIFT     8
0096 #define BTR_TSEG1_MASK      (0xf << BTR_TSEG1_SHIFT)
0097 #define BTR_TSEG2_SHIFT     12
0098 #define BTR_TSEG2_MASK      (0x7 << BTR_TSEG2_SHIFT)
0099 
0100 /* interrupt register */
0101 #define INT_STS_PENDING     0x8000
0102 
0103 /* brp extension register */
0104 #define BRP_EXT_BRPE_MASK   0x0f
0105 #define BRP_EXT_BRPE_SHIFT  0
0106 
0107 /* IFx command request */
0108 #define IF_COMR_BUSY        BIT(15)
0109 
0110 /* IFx command mask */
0111 #define IF_COMM_WR      BIT(7)
0112 #define IF_COMM_MASK        BIT(6)
0113 #define IF_COMM_ARB     BIT(5)
0114 #define IF_COMM_CONTROL     BIT(4)
0115 #define IF_COMM_CLR_INT_PND BIT(3)
0116 #define IF_COMM_TXRQST      BIT(2)
0117 #define IF_COMM_CLR_NEWDAT  IF_COMM_TXRQST
0118 #define IF_COMM_DATAA       BIT(1)
0119 #define IF_COMM_DATAB       BIT(0)
0120 
0121 /* TX buffer setup */
0122 #define IF_COMM_TX      (IF_COMM_ARB | IF_COMM_CONTROL | \
0123                  IF_COMM_TXRQST |        \
0124                  IF_COMM_DATAA | IF_COMM_DATAB)
0125 
0126 /* For the low buffers we clear the interrupt bit, but keep newdat */
0127 #define IF_COMM_RCV_LOW     (IF_COMM_MASK | IF_COMM_ARB | \
0128                  IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
0129                  IF_COMM_DATAA | IF_COMM_DATAB)
0130 
0131 /* For the high buffers we clear the interrupt bit and newdat */
0132 #define IF_COMM_RCV_HIGH    (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
0133 
0134 /* Receive setup of message objects */
0135 #define IF_COMM_RCV_SETUP   (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
0136 
0137 /* Invalidation of message objects */
0138 #define IF_COMM_INVAL       (IF_COMM_ARB | IF_COMM_CONTROL)
0139 
0140 /* IFx arbitration */
0141 #define IF_ARB_MSGVAL       BIT(31)
0142 #define IF_ARB_MSGXTD       BIT(30)
0143 #define IF_ARB_TRANSMIT     BIT(29)
0144 
0145 /* IFx message control */
0146 #define IF_MCONT_NEWDAT     BIT(15)
0147 #define IF_MCONT_MSGLST     BIT(14)
0148 #define IF_MCONT_INTPND     BIT(13)
0149 #define IF_MCONT_UMASK      BIT(12)
0150 #define IF_MCONT_TXIE       BIT(11)
0151 #define IF_MCONT_RXIE       BIT(10)
0152 #define IF_MCONT_RMTEN      BIT(9)
0153 #define IF_MCONT_TXRQST     BIT(8)
0154 #define IF_MCONT_EOB        BIT(7)
0155 #define IF_MCONT_DLC_MASK   0xf
0156 
0157 #define IF_MCONT_RCV        (IF_MCONT_RXIE | IF_MCONT_UMASK)
0158 #define IF_MCONT_RCV_EOB    (IF_MCONT_RCV | IF_MCONT_EOB)
0159 
0160 #define IF_MCONT_TX     (IF_MCONT_TXIE | IF_MCONT_EOB)
0161 
0162 /* Use IF1 in NAPI path and IF2 in TX path */
0163 #define IF_NAPI         0
0164 #define IF_TX           1
0165 
0166 /* minimum timeout for checking BUSY status */
0167 #define MIN_TIMEOUT_VALUE   6
0168 
0169 /* Wait for ~1 sec for INIT bit */
0170 #define INIT_WAIT_MS        1000
0171 
0172 /* c_can lec values */
0173 enum c_can_lec_type {
0174     LEC_NO_ERROR = 0,
0175     LEC_STUFF_ERROR,
0176     LEC_FORM_ERROR,
0177     LEC_ACK_ERROR,
0178     LEC_BIT1_ERROR,
0179     LEC_BIT0_ERROR,
0180     LEC_CRC_ERROR,
0181     LEC_UNUSED,
0182     LEC_MASK = LEC_UNUSED,
0183 };
0184 
0185 /* c_can error types:
0186  * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
0187  */
0188 enum c_can_bus_error_types {
0189     C_CAN_NO_ERROR = 0,
0190     C_CAN_BUS_OFF,
0191     C_CAN_ERROR_WARNING,
0192     C_CAN_ERROR_PASSIVE,
0193 };
0194 
0195 static const struct can_bittiming_const c_can_bittiming_const = {
0196     .name = KBUILD_MODNAME,
0197     .tseg1_min = 2,     /* Time segment 1 = prop_seg + phase_seg1 */
0198     .tseg1_max = 16,
0199     .tseg2_min = 1,     /* Time segment 2 = phase_seg2 */
0200     .tseg2_max = 8,
0201     .sjw_max = 4,
0202     .brp_min = 1,
0203     .brp_max = 1024,    /* 6-bit BRP field + 4-bit BRPE field*/
0204     .brp_inc = 1,
0205 };
0206 
0207 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
0208 {
0209     if (priv->device)
0210         pm_runtime_get_sync(priv->device);
0211 }
0212 
0213 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
0214 {
0215     if (priv->device)
0216         pm_runtime_put_sync(priv->device);
0217 }
0218 
0219 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
0220 {
0221     if (priv->raminit)
0222         priv->raminit(priv, enable);
0223 }
0224 
0225 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
0226 {
0227     u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
0228 
0229     if (enable)
0230         ctrl |= CONTROL_IRQMSK;
0231 
0232     priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
0233 }
0234 
0235 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
0236 {
0237     struct c_can_priv *priv = netdev_priv(dev);
0238     int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
0239 
0240     priv->write_reg32(priv, reg, (cmd << 16) | obj);
0241 
0242     for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
0243         if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
0244             return;
0245         udelay(1);
0246     }
0247     netdev_err(dev, "Updating object timed out\n");
0248 }
0249 
0250 static inline void c_can_object_get(struct net_device *dev, int iface,
0251                     u32 obj, u32 cmd)
0252 {
0253     c_can_obj_update(dev, iface, cmd, obj);
0254 }
0255 
0256 static inline void c_can_object_put(struct net_device *dev, int iface,
0257                     u32 obj, u32 cmd)
0258 {
0259     c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
0260 }
0261 
0262 /* Note: According to documentation clearing TXIE while MSGVAL is set
0263  * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
0264  * load significantly.
0265  */
0266 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
0267 {
0268     struct c_can_priv *priv = netdev_priv(dev);
0269 
0270     priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
0271     c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
0272 }
0273 
0274 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
0275 {
0276     struct c_can_priv *priv = netdev_priv(dev);
0277 
0278     priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
0279     c_can_inval_tx_object(dev, iface, obj);
0280 }
0281 
0282 static void c_can_setup_tx_object(struct net_device *dev, int iface,
0283                   struct can_frame *frame, int idx)
0284 {
0285     struct c_can_priv *priv = netdev_priv(dev);
0286     u16 ctrl = IF_MCONT_TX | frame->len;
0287     bool rtr = frame->can_id & CAN_RTR_FLAG;
0288     u32 arb = IF_ARB_MSGVAL;
0289     int i;
0290 
0291     if (frame->can_id & CAN_EFF_FLAG) {
0292         arb |= frame->can_id & CAN_EFF_MASK;
0293         arb |= IF_ARB_MSGXTD;
0294     } else {
0295         arb |= (frame->can_id & CAN_SFF_MASK) << 18;
0296     }
0297 
0298     if (!rtr)
0299         arb |= IF_ARB_TRANSMIT;
0300 
0301     /* If we change the DIR bit, we need to invalidate the buffer
0302      * first, i.e. clear the MSGVAL flag in the arbiter.
0303      */
0304     if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
0305         u32 obj = idx + priv->msg_obj_tx_first;
0306 
0307         c_can_inval_msg_object(dev, iface, obj);
0308         change_bit(idx, &priv->tx_dir);
0309     }
0310 
0311     priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
0312 
0313     priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
0314 
0315     if (priv->type == BOSCH_D_CAN) {
0316         u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
0317 
0318         for (i = 0; i < frame->len; i += 4, dreg += 2) {
0319             data = (u32)frame->data[i];
0320             data |= (u32)frame->data[i + 1] << 8;
0321             data |= (u32)frame->data[i + 2] << 16;
0322             data |= (u32)frame->data[i + 3] << 24;
0323             priv->write_reg32(priv, dreg, data);
0324         }
0325     } else {
0326         for (i = 0; i < frame->len; i += 2) {
0327             priv->write_reg(priv,
0328                     C_CAN_IFACE(DATA1_REG, iface) + i / 2,
0329                     frame->data[i] |
0330                     (frame->data[i + 1] << 8));
0331         }
0332     }
0333 }
0334 
0335 static int c_can_handle_lost_msg_obj(struct net_device *dev,
0336                      int iface, int objno, u32 ctrl)
0337 {
0338     struct net_device_stats *stats = &dev->stats;
0339     struct c_can_priv *priv = netdev_priv(dev);
0340     struct can_frame *frame;
0341     struct sk_buff *skb;
0342 
0343     ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
0344     priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
0345     c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
0346 
0347     stats->rx_errors++;
0348     stats->rx_over_errors++;
0349 
0350     /* create an error msg */
0351     skb = alloc_can_err_skb(dev, &frame);
0352     if (unlikely(!skb))
0353         return 0;
0354 
0355     frame->can_id |= CAN_ERR_CRTL;
0356     frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
0357 
0358     netif_receive_skb(skb);
0359     return 1;
0360 }
0361 
0362 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
0363 {
0364     struct net_device_stats *stats = &dev->stats;
0365     struct c_can_priv *priv = netdev_priv(dev);
0366     struct can_frame *frame;
0367     struct sk_buff *skb;
0368     u32 arb, data;
0369 
0370     skb = alloc_can_skb(dev, &frame);
0371     if (!skb) {
0372         stats->rx_dropped++;
0373         return -ENOMEM;
0374     }
0375 
0376     frame->len = can_cc_dlc2len(ctrl & 0x0F);
0377 
0378     arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
0379 
0380     if (arb & IF_ARB_MSGXTD)
0381         frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
0382     else
0383         frame->can_id = (arb >> 18) & CAN_SFF_MASK;
0384 
0385     if (arb & IF_ARB_TRANSMIT) {
0386         frame->can_id |= CAN_RTR_FLAG;
0387     } else {
0388         int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
0389 
0390         if (priv->type == BOSCH_D_CAN) {
0391             for (i = 0; i < frame->len; i += 4, dreg += 2) {
0392                 data = priv->read_reg32(priv, dreg);
0393                 frame->data[i] = data;
0394                 frame->data[i + 1] = data >> 8;
0395                 frame->data[i + 2] = data >> 16;
0396                 frame->data[i + 3] = data >> 24;
0397             }
0398         } else {
0399             for (i = 0; i < frame->len; i += 2, dreg++) {
0400                 data = priv->read_reg(priv, dreg);
0401                 frame->data[i] = data;
0402                 frame->data[i + 1] = data >> 8;
0403             }
0404         }
0405 
0406         stats->rx_bytes += frame->len;
0407     }
0408     stats->rx_packets++;
0409 
0410     netif_receive_skb(skb);
0411     return 0;
0412 }
0413 
0414 static void c_can_setup_receive_object(struct net_device *dev, int iface,
0415                        u32 obj, u32 mask, u32 id, u32 mcont)
0416 {
0417     struct c_can_priv *priv = netdev_priv(dev);
0418 
0419     mask |= BIT(29);
0420     priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
0421 
0422     id |= IF_ARB_MSGVAL;
0423     priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
0424 
0425     priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
0426     c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
0427 }
0428 
0429 static bool c_can_tx_busy(const struct c_can_priv *priv,
0430               const struct c_can_tx_ring *tx_ring)
0431 {
0432     if (c_can_get_tx_free(priv, tx_ring) > 0)
0433         return false;
0434 
0435     netif_stop_queue(priv->dev);
0436 
0437     /* Memory barrier before checking tx_free (head and tail) */
0438     smp_mb();
0439 
0440     if (c_can_get_tx_free(priv, tx_ring) == 0) {
0441         netdev_dbg(priv->dev,
0442                "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n",
0443                tx_ring->head, tx_ring->tail,
0444                tx_ring->head - tx_ring->tail);
0445         return true;
0446     }
0447 
0448     netif_start_queue(priv->dev);
0449     return false;
0450 }
0451 
0452 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
0453                     struct net_device *dev)
0454 {
0455     struct can_frame *frame = (struct can_frame *)skb->data;
0456     struct c_can_priv *priv = netdev_priv(dev);
0457     struct c_can_tx_ring *tx_ring = &priv->tx;
0458     u32 idx, obj, cmd = IF_COMM_TX;
0459 
0460     if (can_dropped_invalid_skb(dev, skb))
0461         return NETDEV_TX_OK;
0462 
0463     if (c_can_tx_busy(priv, tx_ring))
0464         return NETDEV_TX_BUSY;
0465 
0466     idx = c_can_get_tx_head(tx_ring);
0467     tx_ring->head++;
0468     if (c_can_get_tx_free(priv, tx_ring) == 0)
0469         netif_stop_queue(dev);
0470 
0471     if (idx < c_can_get_tx_tail(tx_ring))
0472         cmd &= ~IF_COMM_TXRQST; /* Cache the message */
0473 
0474     /* Store the message in the interface so we can call
0475      * can_put_echo_skb(). We must do this before we enable
0476      * transmit as we might race against do_tx().
0477      */
0478     c_can_setup_tx_object(dev, IF_TX, frame, idx);
0479     can_put_echo_skb(skb, dev, idx, 0);
0480     obj = idx + priv->msg_obj_tx_first;
0481     c_can_object_put(dev, IF_TX, obj, cmd);
0482 
0483     return NETDEV_TX_OK;
0484 }
0485 
0486 static int c_can_wait_for_ctrl_init(struct net_device *dev,
0487                     struct c_can_priv *priv, u32 init)
0488 {
0489     int retry = 0;
0490 
0491     while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
0492         udelay(10);
0493         if (retry++ > 1000) {
0494             netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
0495             return -EIO;
0496         }
0497     }
0498     return 0;
0499 }
0500 
0501 static int c_can_set_bittiming(struct net_device *dev)
0502 {
0503     unsigned int reg_btr, reg_brpe, ctrl_save;
0504     u8 brp, brpe, sjw, tseg1, tseg2;
0505     u32 ten_bit_brp;
0506     struct c_can_priv *priv = netdev_priv(dev);
0507     const struct can_bittiming *bt = &priv->can.bittiming;
0508     int res;
0509 
0510     /* c_can provides a 6-bit brp and 4-bit brpe fields */
0511     ten_bit_brp = bt->brp - 1;
0512     brp = ten_bit_brp & BTR_BRP_MASK;
0513     brpe = ten_bit_brp >> 6;
0514 
0515     sjw = bt->sjw - 1;
0516     tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
0517     tseg2 = bt->phase_seg2 - 1;
0518     reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
0519             (tseg2 << BTR_TSEG2_SHIFT);
0520     reg_brpe = brpe & BRP_EXT_BRPE_MASK;
0521 
0522     netdev_info(dev,
0523             "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
0524 
0525     ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
0526     ctrl_save &= ~CONTROL_INIT;
0527     priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
0528     res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
0529     if (res)
0530         return res;
0531 
0532     priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
0533     priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
0534     priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
0535 
0536     return c_can_wait_for_ctrl_init(dev, priv, 0);
0537 }
0538 
0539 /* Configure C_CAN message objects for Tx and Rx purposes:
0540  * C_CAN provides a total of 32 message objects that can be configured
0541  * either for Tx or Rx purposes. Here the first 16 message objects are used as
0542  * a reception FIFO. The end of reception FIFO is signified by the EoB bit
0543  * being SET. The remaining 16 message objects are kept aside for Tx purposes.
0544  * See user guide document for further details on configuring message
0545  * objects.
0546  */
0547 static void c_can_configure_msg_objects(struct net_device *dev)
0548 {
0549     struct c_can_priv *priv = netdev_priv(dev);
0550     int i;
0551 
0552     /* first invalidate all message objects */
0553     for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++)
0554         c_can_inval_msg_object(dev, IF_NAPI, i);
0555 
0556     /* setup receive message objects */
0557     for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++)
0558         c_can_setup_receive_object(dev, IF_NAPI, i, 0, 0, IF_MCONT_RCV);
0559 
0560     c_can_setup_receive_object(dev, IF_NAPI, priv->msg_obj_rx_last, 0, 0,
0561                    IF_MCONT_RCV_EOB);
0562 }
0563 
0564 static int c_can_software_reset(struct net_device *dev)
0565 {
0566     struct c_can_priv *priv = netdev_priv(dev);
0567     int retry = 0;
0568 
0569     if (priv->type != BOSCH_D_CAN)
0570         return 0;
0571 
0572     priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
0573     while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
0574         msleep(20);
0575         if (retry++ > 100) {
0576             netdev_err(dev, "CCTRL: software reset failed\n");
0577             return -EIO;
0578         }
0579     }
0580 
0581     return 0;
0582 }
0583 
0584 /* Configure C_CAN chip:
0585  * - enable/disable auto-retransmission
0586  * - set operating mode
0587  * - configure message objects
0588  */
0589 static int c_can_chip_config(struct net_device *dev)
0590 {
0591     struct c_can_priv *priv = netdev_priv(dev);
0592     struct c_can_tx_ring *tx_ring = &priv->tx;
0593     int err;
0594 
0595     err = c_can_software_reset(dev);
0596     if (err)
0597         return err;
0598 
0599     /* enable automatic retransmission */
0600     priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
0601 
0602     if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
0603         (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
0604         /* loopback + silent mode : useful for hot self-test */
0605         priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
0606         priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
0607     } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
0608         /* loopback mode : useful for self-test function */
0609         priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
0610         priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
0611     } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
0612         /* silent mode : bus-monitoring mode */
0613         priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
0614         priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
0615     }
0616 
0617     /* configure message objects */
0618     c_can_configure_msg_objects(dev);
0619 
0620     /* set a `lec` value so that we can check for updates later */
0621     priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
0622 
0623     /* Clear all internal status */
0624     tx_ring->head = 0;
0625     tx_ring->tail = 0;
0626     priv->tx_dir = 0;
0627 
0628     /* set bittiming params */
0629     return c_can_set_bittiming(dev);
0630 }
0631 
0632 static int c_can_start(struct net_device *dev)
0633 {
0634     struct c_can_priv *priv = netdev_priv(dev);
0635     int err;
0636     struct pinctrl *p;
0637 
0638     /* basic c_can configuration */
0639     err = c_can_chip_config(dev);
0640     if (err)
0641         return err;
0642 
0643     /* Setup the command for new messages */
0644     priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
0645         IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
0646 
0647     priv->can.state = CAN_STATE_ERROR_ACTIVE;
0648 
0649     /* Attempt to use "active" if available else use "default" */
0650     p = pinctrl_get_select(priv->device, "active");
0651     if (!IS_ERR(p))
0652         pinctrl_put(p);
0653     else
0654         pinctrl_pm_select_default_state(priv->device);
0655 
0656     return 0;
0657 }
0658 
0659 static void c_can_stop(struct net_device *dev)
0660 {
0661     struct c_can_priv *priv = netdev_priv(dev);
0662 
0663     c_can_irq_control(priv, false);
0664 
0665     /* put ctrl to init on stop to end ongoing transmission */
0666     priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
0667 
0668     /* deactivate pins */
0669     pinctrl_pm_select_sleep_state(dev->dev.parent);
0670     priv->can.state = CAN_STATE_STOPPED;
0671 }
0672 
0673 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
0674 {
0675     struct c_can_priv *priv = netdev_priv(dev);
0676     int err;
0677 
0678     switch (mode) {
0679     case CAN_MODE_START:
0680         err = c_can_start(dev);
0681         if (err)
0682             return err;
0683         netif_wake_queue(dev);
0684         c_can_irq_control(priv, true);
0685         break;
0686     default:
0687         return -EOPNOTSUPP;
0688     }
0689 
0690     return 0;
0691 }
0692 
0693 static int __c_can_get_berr_counter(const struct net_device *dev,
0694                     struct can_berr_counter *bec)
0695 {
0696     unsigned int reg_err_counter;
0697     struct c_can_priv *priv = netdev_priv(dev);
0698 
0699     reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
0700     bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
0701                 ERR_CNT_REC_SHIFT;
0702     bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
0703 
0704     return 0;
0705 }
0706 
0707 static int c_can_get_berr_counter(const struct net_device *dev,
0708                   struct can_berr_counter *bec)
0709 {
0710     struct c_can_priv *priv = netdev_priv(dev);
0711     int err;
0712 
0713     c_can_pm_runtime_get_sync(priv);
0714     err = __c_can_get_berr_counter(dev, bec);
0715     c_can_pm_runtime_put_sync(priv);
0716 
0717     return err;
0718 }
0719 
0720 static void c_can_do_tx(struct net_device *dev)
0721 {
0722     struct c_can_priv *priv = netdev_priv(dev);
0723     struct c_can_tx_ring *tx_ring = &priv->tx;
0724     struct net_device_stats *stats = &dev->stats;
0725     u32 idx, obj, pkts = 0, bytes = 0, pend;
0726     u8 tail;
0727 
0728     if (priv->msg_obj_tx_last > 32)
0729         pend = priv->read_reg32(priv, C_CAN_INTPND3_REG);
0730     else
0731         pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
0732 
0733     while ((idx = ffs(pend))) {
0734         idx--;
0735         pend &= ~BIT(idx);
0736         obj = idx + priv->msg_obj_tx_first;
0737 
0738         /* We use IF_NAPI interface instead of IF_TX because we
0739          * are called from c_can_poll(), which runs inside
0740          * NAPI. We are not transmitting.
0741          */
0742         c_can_inval_tx_object(dev, IF_NAPI, obj);
0743         bytes += can_get_echo_skb(dev, idx, NULL);
0744         pkts++;
0745     }
0746 
0747     if (!pkts)
0748         return;
0749 
0750     tx_ring->tail += pkts;
0751     if (c_can_get_tx_free(priv, tx_ring)) {
0752         /* Make sure that anybody stopping the queue after
0753          * this sees the new tx_ring->tail.
0754          */
0755         smp_mb();
0756         netif_wake_queue(priv->dev);
0757     }
0758 
0759     stats->tx_bytes += bytes;
0760     stats->tx_packets += pkts;
0761 
0762     tail = c_can_get_tx_tail(tx_ring);
0763     if (priv->type == BOSCH_D_CAN && tail == 0) {
0764         u8 head = c_can_get_tx_head(tx_ring);
0765 
0766         /* Start transmission for all cached messages */
0767         for (idx = tail; idx < head; idx++) {
0768             obj = idx + priv->msg_obj_tx_first;
0769             c_can_object_put(dev, IF_NAPI, obj, IF_COMM_TXRQST);
0770         }
0771     }
0772 }
0773 
0774 /* If we have a gap in the pending bits, that means we either
0775  * raced with the hardware or failed to readout all upper
0776  * objects in the last run due to quota limit.
0777  */
0778 static u32 c_can_adjust_pending(u32 pend, u32 rx_mask)
0779 {
0780     u32 weight, lasts;
0781 
0782     if (pend == rx_mask)
0783         return pend;
0784 
0785     /* If the last set bit is larger than the number of pending
0786      * bits we have a gap.
0787      */
0788     weight = hweight32(pend);
0789     lasts = fls(pend);
0790 
0791     /* If the bits are linear, nothing to do */
0792     if (lasts == weight)
0793         return pend;
0794 
0795     /* Find the first set bit after the gap. We walk backwards
0796      * from the last set bit.
0797      */
0798     for (lasts--; pend & BIT(lasts - 1); lasts--)
0799         ;
0800 
0801     return pend & ~GENMASK(lasts - 1, 0);
0802 }
0803 
0804 static inline void c_can_rx_object_get(struct net_device *dev,
0805                        struct c_can_priv *priv, u32 obj)
0806 {
0807     c_can_object_get(dev, IF_NAPI, obj, priv->comm_rcv_high);
0808 }
0809 
0810 static inline void c_can_rx_finalize(struct net_device *dev,
0811                      struct c_can_priv *priv, u32 obj)
0812 {
0813     if (priv->type != BOSCH_D_CAN)
0814         c_can_object_get(dev, IF_NAPI, obj, IF_COMM_CLR_NEWDAT);
0815 }
0816 
0817 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
0818                   u32 pend, int quota)
0819 {
0820     u32 pkts = 0, ctrl, obj;
0821 
0822     while ((obj = ffs(pend)) && quota > 0) {
0823         pend &= ~BIT(obj - 1);
0824 
0825         c_can_rx_object_get(dev, priv, obj);
0826         ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI));
0827 
0828         if (ctrl & IF_MCONT_MSGLST) {
0829             int n;
0830 
0831             n = c_can_handle_lost_msg_obj(dev, IF_NAPI, obj, ctrl);
0832 
0833             pkts += n;
0834             quota -= n;
0835             continue;
0836         }
0837 
0838         /* This really should not happen, but this covers some
0839          * odd HW behaviour. Do not remove that unless you
0840          * want to brick your machine.
0841          */
0842         if (!(ctrl & IF_MCONT_NEWDAT))
0843             continue;
0844 
0845         /* read the data from the message object */
0846         c_can_read_msg_object(dev, IF_NAPI, ctrl);
0847 
0848         c_can_rx_finalize(dev, priv, obj);
0849 
0850         pkts++;
0851         quota--;
0852     }
0853 
0854     return pkts;
0855 }
0856 
0857 static inline u32 c_can_get_pending(struct c_can_priv *priv)
0858 {
0859     u32 pend;
0860 
0861     if (priv->msg_obj_rx_last > 16)
0862         pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG);
0863     else
0864         pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
0865 
0866     return pend;
0867 }
0868 
0869 /* theory of operation:
0870  *
0871  * c_can core saves a received CAN message into the first free message
0872  * object it finds free (starting with the lowest). Bits NEWDAT and
0873  * INTPND are set for this message object indicating that a new message
0874  * has arrived.
0875  *
0876  * We clear the newdat bit right away.
0877  *
0878  * This can result in packet reordering when the readout is slow.
0879  */
0880 static int c_can_do_rx_poll(struct net_device *dev, int quota)
0881 {
0882     struct c_can_priv *priv = netdev_priv(dev);
0883     u32 pkts = 0, pend = 0, toread, n;
0884 
0885     while (quota > 0) {
0886         if (!pend) {
0887             pend = c_can_get_pending(priv);
0888             if (!pend)
0889                 break;
0890             /* If the pending field has a gap, handle the
0891              * bits above the gap first.
0892              */
0893             toread = c_can_adjust_pending(pend,
0894                               priv->msg_obj_rx_mask);
0895         } else {
0896             toread = pend;
0897         }
0898         /* Remove the bits from pend */
0899         pend &= ~toread;
0900         /* Read the objects */
0901         n = c_can_read_objects(dev, priv, toread, quota);
0902         pkts += n;
0903         quota -= n;
0904     }
0905 
0906     return pkts;
0907 }
0908 
0909 static int c_can_handle_state_change(struct net_device *dev,
0910                      enum c_can_bus_error_types error_type)
0911 {
0912     unsigned int reg_err_counter;
0913     unsigned int rx_err_passive;
0914     struct c_can_priv *priv = netdev_priv(dev);
0915     struct can_frame *cf;
0916     struct sk_buff *skb;
0917     struct can_berr_counter bec;
0918 
0919     switch (error_type) {
0920     case C_CAN_NO_ERROR:
0921         priv->can.state = CAN_STATE_ERROR_ACTIVE;
0922         break;
0923     case C_CAN_ERROR_WARNING:
0924         /* error warning state */
0925         priv->can.can_stats.error_warning++;
0926         priv->can.state = CAN_STATE_ERROR_WARNING;
0927         break;
0928     case C_CAN_ERROR_PASSIVE:
0929         /* error passive state */
0930         priv->can.can_stats.error_passive++;
0931         priv->can.state = CAN_STATE_ERROR_PASSIVE;
0932         break;
0933     case C_CAN_BUS_OFF:
0934         /* bus-off state */
0935         priv->can.state = CAN_STATE_BUS_OFF;
0936         priv->can.can_stats.bus_off++;
0937         break;
0938     default:
0939         break;
0940     }
0941 
0942     /* propagate the error condition to the CAN stack */
0943     skb = alloc_can_err_skb(dev, &cf);
0944     if (unlikely(!skb))
0945         return 0;
0946 
0947     __c_can_get_berr_counter(dev, &bec);
0948     reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
0949     rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
0950                 ERR_CNT_RP_SHIFT;
0951 
0952     switch (error_type) {
0953     case C_CAN_NO_ERROR:
0954         cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
0955         cf->data[1] = CAN_ERR_CRTL_ACTIVE;
0956         cf->data[6] = bec.txerr;
0957         cf->data[7] = bec.rxerr;
0958         break;
0959     case C_CAN_ERROR_WARNING:
0960         /* error warning state */
0961         cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
0962         cf->data[1] = (bec.txerr > bec.rxerr) ?
0963             CAN_ERR_CRTL_TX_WARNING :
0964             CAN_ERR_CRTL_RX_WARNING;
0965         cf->data[6] = bec.txerr;
0966         cf->data[7] = bec.rxerr;
0967 
0968         break;
0969     case C_CAN_ERROR_PASSIVE:
0970         /* error passive state */
0971         cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
0972         if (rx_err_passive)
0973             cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
0974         if (bec.txerr > 127)
0975             cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
0976 
0977         cf->data[6] = bec.txerr;
0978         cf->data[7] = bec.rxerr;
0979         break;
0980     case C_CAN_BUS_OFF:
0981         /* bus-off state */
0982         cf->can_id |= CAN_ERR_BUSOFF;
0983         can_bus_off(dev);
0984         break;
0985     default:
0986         break;
0987     }
0988 
0989     netif_receive_skb(skb);
0990 
0991     return 1;
0992 }
0993 
0994 static int c_can_handle_bus_err(struct net_device *dev,
0995                 enum c_can_lec_type lec_type)
0996 {
0997     struct c_can_priv *priv = netdev_priv(dev);
0998     struct net_device_stats *stats = &dev->stats;
0999     struct can_frame *cf;
1000     struct sk_buff *skb;
1001 
1002     /* early exit if no lec update or no error.
1003      * no lec update means that no CAN bus event has been detected
1004      * since CPU wrote 0x7 value to status reg.
1005      */
1006     if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1007         return 0;
1008 
1009     if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1010         return 0;
1011 
1012     /* common for all type of bus errors */
1013     priv->can.can_stats.bus_error++;
1014     stats->rx_errors++;
1015 
1016     /* propagate the error condition to the CAN stack */
1017     skb = alloc_can_err_skb(dev, &cf);
1018     if (unlikely(!skb))
1019         return 0;
1020 
1021     /* check for 'last error code' which tells us the
1022      * type of the last error to occur on the CAN bus
1023      */
1024     cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1025 
1026     switch (lec_type) {
1027     case LEC_STUFF_ERROR:
1028         netdev_dbg(dev, "stuff error\n");
1029         cf->data[2] |= CAN_ERR_PROT_STUFF;
1030         break;
1031     case LEC_FORM_ERROR:
1032         netdev_dbg(dev, "form error\n");
1033         cf->data[2] |= CAN_ERR_PROT_FORM;
1034         break;
1035     case LEC_ACK_ERROR:
1036         netdev_dbg(dev, "ack error\n");
1037         cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1038         break;
1039     case LEC_BIT1_ERROR:
1040         netdev_dbg(dev, "bit1 error\n");
1041         cf->data[2] |= CAN_ERR_PROT_BIT1;
1042         break;
1043     case LEC_BIT0_ERROR:
1044         netdev_dbg(dev, "bit0 error\n");
1045         cf->data[2] |= CAN_ERR_PROT_BIT0;
1046         break;
1047     case LEC_CRC_ERROR:
1048         netdev_dbg(dev, "CRC error\n");
1049         cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1050         break;
1051     default:
1052         break;
1053     }
1054 
1055     netif_receive_skb(skb);
1056     return 1;
1057 }
1058 
1059 static int c_can_poll(struct napi_struct *napi, int quota)
1060 {
1061     struct net_device *dev = napi->dev;
1062     struct c_can_priv *priv = netdev_priv(dev);
1063     u16 curr, last = priv->last_status;
1064     int work_done = 0;
1065 
1066     /* Only read the status register if a status interrupt was pending */
1067     if (atomic_xchg(&priv->sie_pending, 0)) {
1068         priv->last_status = priv->read_reg(priv, C_CAN_STS_REG);
1069         curr = priv->last_status;
1070         /* Ack status on C_CAN. D_CAN is self clearing */
1071         if (priv->type != BOSCH_D_CAN)
1072             priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1073     } else {
1074         /* no change detected ... */
1075         curr = last;
1076     }
1077 
1078     /* handle state changes */
1079     if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1080         netdev_dbg(dev, "entered error warning state\n");
1081         work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1082     }
1083 
1084     if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1085         netdev_dbg(dev, "entered error passive state\n");
1086         work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1087     }
1088 
1089     if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1090         netdev_dbg(dev, "entered bus off state\n");
1091         work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1092         goto end;
1093     }
1094 
1095     /* handle bus recovery events */
1096     if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1097         netdev_dbg(dev, "left bus off state\n");
1098         work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1099     }
1100 
1101     if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1102         netdev_dbg(dev, "left error passive state\n");
1103         work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1104     }
1105 
1106     if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1107         netdev_dbg(dev, "left error warning state\n");
1108         work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1109     }
1110 
1111     /* handle lec errors on the bus */
1112     work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1113 
1114     /* Handle Tx/Rx events. We do this unconditionally */
1115     work_done += c_can_do_rx_poll(dev, (quota - work_done));
1116     c_can_do_tx(dev);
1117 
1118 end:
1119     if (work_done < quota) {
1120         napi_complete_done(napi, work_done);
1121         /* enable all IRQs if we are not in bus off state */
1122         if (priv->can.state != CAN_STATE_BUS_OFF)
1123             c_can_irq_control(priv, true);
1124     }
1125 
1126     return work_done;
1127 }
1128 
1129 static irqreturn_t c_can_isr(int irq, void *dev_id)
1130 {
1131     struct net_device *dev = (struct net_device *)dev_id;
1132     struct c_can_priv *priv = netdev_priv(dev);
1133     int reg_int;
1134 
1135     reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1136     if (!reg_int)
1137         return IRQ_NONE;
1138 
1139     /* save for later use */
1140     if (reg_int & INT_STS_PENDING)
1141         atomic_set(&priv->sie_pending, 1);
1142 
1143     /* disable all interrupts and schedule the NAPI */
1144     c_can_irq_control(priv, false);
1145     napi_schedule(&priv->napi);
1146 
1147     return IRQ_HANDLED;
1148 }
1149 
1150 static int c_can_open(struct net_device *dev)
1151 {
1152     int err;
1153     struct c_can_priv *priv = netdev_priv(dev);
1154 
1155     c_can_pm_runtime_get_sync(priv);
1156     c_can_reset_ram(priv, true);
1157 
1158     /* open the can device */
1159     err = open_candev(dev);
1160     if (err) {
1161         netdev_err(dev, "failed to open can device\n");
1162         goto exit_open_fail;
1163     }
1164 
1165     /* register interrupt handler */
1166     err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1167               dev);
1168     if (err < 0) {
1169         netdev_err(dev, "failed to request interrupt\n");
1170         goto exit_irq_fail;
1171     }
1172 
1173     /* start the c_can controller */
1174     err = c_can_start(dev);
1175     if (err)
1176         goto exit_start_fail;
1177 
1178     napi_enable(&priv->napi);
1179     /* enable status change, error and module interrupts */
1180     c_can_irq_control(priv, true);
1181     netif_start_queue(dev);
1182 
1183     return 0;
1184 
1185 exit_start_fail:
1186     free_irq(dev->irq, dev);
1187 exit_irq_fail:
1188     close_candev(dev);
1189 exit_open_fail:
1190     c_can_reset_ram(priv, false);
1191     c_can_pm_runtime_put_sync(priv);
1192     return err;
1193 }
1194 
1195 static int c_can_close(struct net_device *dev)
1196 {
1197     struct c_can_priv *priv = netdev_priv(dev);
1198 
1199     netif_stop_queue(dev);
1200     napi_disable(&priv->napi);
1201     c_can_stop(dev);
1202     free_irq(dev->irq, dev);
1203     close_candev(dev);
1204 
1205     c_can_reset_ram(priv, false);
1206     c_can_pm_runtime_put_sync(priv);
1207 
1208     return 0;
1209 }
1210 
1211 struct net_device *alloc_c_can_dev(int msg_obj_num)
1212 {
1213     struct net_device *dev;
1214     struct c_can_priv *priv;
1215     int msg_obj_tx_num = msg_obj_num / 2;
1216 
1217     dev = alloc_candev(sizeof(*priv), msg_obj_tx_num);
1218     if (!dev)
1219         return NULL;
1220 
1221     priv = netdev_priv(dev);
1222     priv->msg_obj_num = msg_obj_num;
1223     priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num;
1224     priv->msg_obj_rx_first = 1;
1225     priv->msg_obj_rx_last =
1226         priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1;
1227     priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0);
1228 
1229     priv->msg_obj_tx_num = msg_obj_tx_num;
1230     priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1;
1231     priv->msg_obj_tx_last =
1232         priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1;
1233 
1234     priv->tx.head = 0;
1235     priv->tx.tail = 0;
1236     priv->tx.obj_num = msg_obj_tx_num;
1237 
1238     netif_napi_add_weight(dev, &priv->napi, c_can_poll,
1239                   priv->msg_obj_rx_num);
1240 
1241     priv->dev = dev;
1242     priv->can.bittiming_const = &c_can_bittiming_const;
1243     priv->can.do_set_mode = c_can_set_mode;
1244     priv->can.do_get_berr_counter = c_can_get_berr_counter;
1245     priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1246                     CAN_CTRLMODE_LISTENONLY |
1247                     CAN_CTRLMODE_BERR_REPORTING;
1248 
1249     return dev;
1250 }
1251 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1252 
1253 #ifdef CONFIG_PM
1254 int c_can_power_down(struct net_device *dev)
1255 {
1256     u32 val;
1257     unsigned long time_out;
1258     struct c_can_priv *priv = netdev_priv(dev);
1259 
1260     if (!(dev->flags & IFF_UP))
1261         return 0;
1262 
1263     WARN_ON(priv->type != BOSCH_D_CAN);
1264 
1265     /* set PDR value so the device goes to power down mode */
1266     val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1267     val |= CONTROL_EX_PDR;
1268     priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1269 
1270     /* Wait for the PDA bit to get set */
1271     time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1272     while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1273            time_after(time_out, jiffies))
1274         cpu_relax();
1275 
1276     if (time_after(jiffies, time_out))
1277         return -ETIMEDOUT;
1278 
1279     c_can_stop(dev);
1280 
1281     c_can_reset_ram(priv, false);
1282     c_can_pm_runtime_put_sync(priv);
1283 
1284     return 0;
1285 }
1286 EXPORT_SYMBOL_GPL(c_can_power_down);
1287 
1288 int c_can_power_up(struct net_device *dev)
1289 {
1290     u32 val;
1291     unsigned long time_out;
1292     struct c_can_priv *priv = netdev_priv(dev);
1293     int ret;
1294 
1295     if (!(dev->flags & IFF_UP))
1296         return 0;
1297 
1298     WARN_ON(priv->type != BOSCH_D_CAN);
1299 
1300     c_can_pm_runtime_get_sync(priv);
1301     c_can_reset_ram(priv, true);
1302 
1303     /* Clear PDR and INIT bits */
1304     val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1305     val &= ~CONTROL_EX_PDR;
1306     priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1307     val = priv->read_reg(priv, C_CAN_CTRL_REG);
1308     val &= ~CONTROL_INIT;
1309     priv->write_reg(priv, C_CAN_CTRL_REG, val);
1310 
1311     /* Wait for the PDA bit to get clear */
1312     time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1313     while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1314            time_after(time_out, jiffies))
1315         cpu_relax();
1316 
1317     if (time_after(jiffies, time_out)) {
1318         ret = -ETIMEDOUT;
1319         goto err_out;
1320     }
1321 
1322     ret = c_can_start(dev);
1323     if (ret)
1324         goto err_out;
1325 
1326     c_can_irq_control(priv, true);
1327 
1328     return 0;
1329 
1330 err_out:
1331     c_can_reset_ram(priv, false);
1332     c_can_pm_runtime_put_sync(priv);
1333 
1334     return ret;
1335 }
1336 EXPORT_SYMBOL_GPL(c_can_power_up);
1337 #endif
1338 
1339 void free_c_can_dev(struct net_device *dev)
1340 {
1341     struct c_can_priv *priv = netdev_priv(dev);
1342 
1343     netif_napi_del(&priv->napi);
1344     free_candev(dev);
1345 }
1346 EXPORT_SYMBOL_GPL(free_c_can_dev);
1347 
1348 static const struct net_device_ops c_can_netdev_ops = {
1349     .ndo_open = c_can_open,
1350     .ndo_stop = c_can_close,
1351     .ndo_start_xmit = c_can_start_xmit,
1352     .ndo_change_mtu = can_change_mtu,
1353 };
1354 
1355 int register_c_can_dev(struct net_device *dev)
1356 {
1357     /* Deactivate pins to prevent DRA7 DCAN IP from being
1358      * stuck in transition when module is disabled.
1359      * Pins are activated in c_can_start() and deactivated
1360      * in c_can_stop()
1361      */
1362     pinctrl_pm_select_sleep_state(dev->dev.parent);
1363 
1364     dev->flags |= IFF_ECHO; /* we support local echo */
1365     dev->netdev_ops = &c_can_netdev_ops;
1366     dev->ethtool_ops = &c_can_ethtool_ops;
1367 
1368     return register_candev(dev);
1369 }
1370 EXPORT_SYMBOL_GPL(register_c_can_dev);
1371 
1372 void unregister_c_can_dev(struct net_device *dev)
1373 {
1374     unregister_candev(dev);
1375 }
1376 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1377 
1378 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1379 MODULE_LICENSE("GPL v2");
1380 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
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