can/c_can/c_can.h

0001 /*
0002  * CAN bus driver for Bosch C_CAN controller
0003  *
0004  * Copyright (C) 2010 ST Microelectronics
0005  * Bhupesh Sharma <bhupesh.sharma@st.com>
0006  *
0007  * Borrowed heavily from the C_CAN driver originally written by:
0008  * Copyright (C) 2007
0009  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
0010  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
0011  *
0012  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
0013  * Bosch C_CAN user manual can be obtained from:
0014  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
0015  * users_manual_c_can.pdf
0016  *
0017  * This file is licensed under the terms of the GNU General Public
0018  * License version 2. This program is licensed "as is" without any
0019  * warranty of any kind, whether express or implied.
0020  */
0021
0022 #ifndef C_CAN_H
0023 #define C_CAN_H
0024
0025 enum reg {
0026     C_CAN_CTRL_REG = 0,
0027     C_CAN_CTRL_EX_REG,
0028     C_CAN_STS_REG,
0029     C_CAN_ERR_CNT_REG,
0030     C_CAN_BTR_REG,
0031     C_CAN_INT_REG,
0032     C_CAN_TEST_REG,
0033     C_CAN_BRPEXT_REG,
0034     C_CAN_IF1_COMREQ_REG,
0035     C_CAN_IF1_COMMSK_REG,
0036     C_CAN_IF1_MASK1_REG,
0037     C_CAN_IF1_MASK2_REG,
0038     C_CAN_IF1_ARB1_REG,
0039     C_CAN_IF1_ARB2_REG,
0040     C_CAN_IF1_MSGCTRL_REG,
0041     C_CAN_IF1_DATA1_REG,
0042     C_CAN_IF1_DATA2_REG,
0043     C_CAN_IF1_DATA3_REG,
0044     C_CAN_IF1_DATA4_REG,
0045     C_CAN_IF2_COMREQ_REG,
0046     C_CAN_IF2_COMMSK_REG,
0047     C_CAN_IF2_MASK1_REG,
0048     C_CAN_IF2_MASK2_REG,
0049     C_CAN_IF2_ARB1_REG,
0050     C_CAN_IF2_ARB2_REG,
0051     C_CAN_IF2_MSGCTRL_REG,
0052     C_CAN_IF2_DATA1_REG,
0053     C_CAN_IF2_DATA2_REG,
0054     C_CAN_IF2_DATA3_REG,
0055     C_CAN_IF2_DATA4_REG,
0056     C_CAN_TXRQST1_REG,
0057     C_CAN_TXRQST2_REG,
0058     C_CAN_NEWDAT1_REG,
0059     C_CAN_NEWDAT2_REG,
0060     C_CAN_INTPND1_REG,
0061     C_CAN_INTPND2_REG,
0062     C_CAN_INTPND3_REG,
0063     C_CAN_MSGVAL1_REG,
0064     C_CAN_MSGVAL2_REG,
0065     C_CAN_FUNCTION_REG,
0066 };
0067
0068 static const u16 __maybe_unused reg_map_c_can[] = {
0069     [C_CAN_CTRL_REG]    = 0x00,
0070     [C_CAN_STS_REG]     = 0x02,
0071     [C_CAN_ERR_CNT_REG] = 0x04,
0072     [C_CAN_BTR_REG]     = 0x06,
0073     [C_CAN_INT_REG]     = 0x08,
0074     [C_CAN_TEST_REG]    = 0x0A,
0075     [C_CAN_BRPEXT_REG]  = 0x0C,
0076     [C_CAN_IF1_COMREQ_REG]  = 0x10,
0077     [C_CAN_IF1_COMMSK_REG]  = 0x12,
0078     [C_CAN_IF1_MASK1_REG]   = 0x14,
0079     [C_CAN_IF1_MASK2_REG]   = 0x16,
0080     [C_CAN_IF1_ARB1_REG]    = 0x18,
0081     [C_CAN_IF1_ARB2_REG]    = 0x1A,
0082     [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
0083     [C_CAN_IF1_DATA1_REG]   = 0x1E,
0084     [C_CAN_IF1_DATA2_REG]   = 0x20,
0085     [C_CAN_IF1_DATA3_REG]   = 0x22,
0086     [C_CAN_IF1_DATA4_REG]   = 0x24,
0087     [C_CAN_IF2_COMREQ_REG]  = 0x40,
0088     [C_CAN_IF2_COMMSK_REG]  = 0x42,
0089     [C_CAN_IF2_MASK1_REG]   = 0x44,
0090     [C_CAN_IF2_MASK2_REG]   = 0x46,
0091     [C_CAN_IF2_ARB1_REG]    = 0x48,
0092     [C_CAN_IF2_ARB2_REG]    = 0x4A,
0093     [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
0094     [C_CAN_IF2_DATA1_REG]   = 0x4E,
0095     [C_CAN_IF2_DATA2_REG]   = 0x50,
0096     [C_CAN_IF2_DATA3_REG]   = 0x52,
0097     [C_CAN_IF2_DATA4_REG]   = 0x54,
0098     [C_CAN_TXRQST1_REG] = 0x80,
0099     [C_CAN_TXRQST2_REG] = 0x82,
0100     [C_CAN_NEWDAT1_REG] = 0x90,
0101     [C_CAN_NEWDAT2_REG] = 0x92,
0102     [C_CAN_INTPND1_REG] = 0xA0,
0103     [C_CAN_INTPND2_REG] = 0xA2,
0104     [C_CAN_MSGVAL1_REG] = 0xB0,
0105     [C_CAN_MSGVAL2_REG] = 0xB2,
0106 };
0107
0108 static const u16 __maybe_unused reg_map_d_can[] = {
0109     [C_CAN_CTRL_REG]    = 0x00,
0110     [C_CAN_CTRL_EX_REG] = 0x02,
0111     [C_CAN_STS_REG]     = 0x04,
0112     [C_CAN_ERR_CNT_REG] = 0x08,
0113     [C_CAN_BTR_REG]     = 0x0C,
0114     [C_CAN_BRPEXT_REG]  = 0x0E,
0115     [C_CAN_INT_REG]     = 0x10,
0116     [C_CAN_TEST_REG]    = 0x14,
0117     [C_CAN_FUNCTION_REG]    = 0x18,
0118     [C_CAN_TXRQST1_REG] = 0x88,
0119     [C_CAN_TXRQST2_REG] = 0x8A,
0120     [C_CAN_NEWDAT1_REG] = 0x9C,
0121     [C_CAN_NEWDAT2_REG] = 0x9E,
0122     [C_CAN_INTPND1_REG] = 0xB0,
0123     [C_CAN_INTPND2_REG] = 0xB2,
0124     [C_CAN_INTPND3_REG] = 0xB4,
0125     [C_CAN_MSGVAL1_REG] = 0xC4,
0126     [C_CAN_MSGVAL2_REG] = 0xC6,
0127     [C_CAN_IF1_COMREQ_REG]  = 0x100,
0128     [C_CAN_IF1_COMMSK_REG]  = 0x102,
0129     [C_CAN_IF1_MASK1_REG]   = 0x104,
0130     [C_CAN_IF1_MASK2_REG]   = 0x106,
0131     [C_CAN_IF1_ARB1_REG]    = 0x108,
0132     [C_CAN_IF1_ARB2_REG]    = 0x10A,
0133     [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
0134     [C_CAN_IF1_DATA1_REG]   = 0x110,
0135     [C_CAN_IF1_DATA2_REG]   = 0x112,
0136     [C_CAN_IF1_DATA3_REG]   = 0x114,
0137     [C_CAN_IF1_DATA4_REG]   = 0x116,
0138     [C_CAN_IF2_COMREQ_REG]  = 0x120,
0139     [C_CAN_IF2_COMMSK_REG]  = 0x122,
0140     [C_CAN_IF2_MASK1_REG]   = 0x124,
0141     [C_CAN_IF2_MASK2_REG]   = 0x126,
0142     [C_CAN_IF2_ARB1_REG]    = 0x128,
0143     [C_CAN_IF2_ARB2_REG]    = 0x12A,
0144     [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
0145     [C_CAN_IF2_DATA1_REG]   = 0x130,
0146     [C_CAN_IF2_DATA2_REG]   = 0x132,
0147     [C_CAN_IF2_DATA3_REG]   = 0x134,
0148     [C_CAN_IF2_DATA4_REG]   = 0x136,
0149 };
0150
0151 enum c_can_dev_id {
0152     BOSCH_C_CAN,
0153     BOSCH_D_CAN,
0154 };
0155
0156 struct raminit_bits {
0157     u8 start;
0158     u8 done;
0159 };
0160
0161 struct c_can_driver_data {
0162     enum c_can_dev_id id;
0163     unsigned int msg_obj_num;
0164
0165     /* RAMINIT register description. Optional. */
0166     const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */
0167     u8 raminit_num;     /* Number of CAN instances on the SoC */
0168     bool raminit_pulse; /* If set, sets and clears START bit (pulse) */
0169 };
0170
0171 /* Out of band RAMINIT register access via syscon regmap */
0172 struct c_can_raminit {
0173     struct regmap *syscon;  /* for raminit ctrl. reg. access */
0174     unsigned int reg;   /* register index within syscon */
0175     struct raminit_bits bits;
0176     bool needs_pulse;
0177 };
0178
0179 /* c_can tx ring structure */
0180 struct c_can_tx_ring {
0181     unsigned int head;
0182     unsigned int tail;
0183     unsigned int obj_num;
0184 };
0185
0186 /* c_can private data structure */
0187 struct c_can_priv {
0188     struct can_priv can;    /* must be the first member */
0189     struct napi_struct napi;
0190     struct net_device *dev;
0191     struct device *device;
0192     unsigned int msg_obj_num;
0193     unsigned int msg_obj_rx_num;
0194     unsigned int msg_obj_tx_num;
0195     unsigned int msg_obj_rx_first;
0196     unsigned int msg_obj_rx_last;
0197     unsigned int msg_obj_tx_first;
0198     unsigned int msg_obj_tx_last;
0199     u32 msg_obj_rx_mask;
0200     atomic_t sie_pending;
0201     unsigned long tx_dir;
0202     int last_status;
0203     struct c_can_tx_ring tx;
0204     u16 (*read_reg)(const struct c_can_priv *priv, enum reg index);
0205     void (*write_reg)(const struct c_can_priv *priv, enum reg index, u16 val);
0206     u32 (*read_reg32)(const struct c_can_priv *priv, enum reg index);
0207     void (*write_reg32)(const struct c_can_priv *priv, enum reg index, u32 val);
0208     void __iomem *base;
0209     const u16 *regs;
0210     enum c_can_dev_id type;
0211     struct c_can_raminit raminit_sys;   /* RAMINIT via syscon regmap */
0212     void (*raminit)(const struct c_can_priv *priv, bool enable);
0213     u32 comm_rcv_high;
0214 };
0215
0216 struct net_device *alloc_c_can_dev(int msg_obj_num);
0217 void free_c_can_dev(struct net_device *dev);
0218 int register_c_can_dev(struct net_device *dev);
0219 void unregister_c_can_dev(struct net_device *dev);
0220
0221 #ifdef CONFIG_PM
0222 int c_can_power_up(struct net_device *dev);
0223 int c_can_power_down(struct net_device *dev);
0224 #endif
0225
0226 extern const struct ethtool_ops c_can_ethtool_ops;
0227
0228 static inline u8 c_can_get_tx_head(const struct c_can_tx_ring *ring)
0229 {
0230     return ring->head & (ring->obj_num - 1);
0231 }
0232
0233 static inline u8 c_can_get_tx_tail(const struct c_can_tx_ring *ring)
0234 {
0235     return ring->tail & (ring->obj_num - 1);
0236 }
0237
0238 static inline u8 c_can_get_tx_free(const struct c_can_priv *priv,
0239                    const struct c_can_tx_ring *ring)
0240 {
0241     u8 head = c_can_get_tx_head(ring);
0242     u8 tail = c_can_get_tx_tail(ring);
0243
0244     if (priv->type == BOSCH_D_CAN)
0245         return ring->obj_num - (ring->head - ring->tail);
0246
0247     /* This is not a FIFO. C/D_CAN sends out the buffers
0248      * prioritized. The lowest buffer number wins.
0249      */
0250     if (head < tail)
0251         return 0;
0252
0253     return ring->obj_num - head;
0254 }
0255
0256 #endif /* C_CAN_H */