mtd/spi-nor/sfdp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2005, Intec Automation Inc.
0004  * Copyright (C) 2014, Freescale Semiconductor, Inc.
0005  */
0006
0007 #ifndef __LINUX_MTD_SFDP_H
0008 #define __LINUX_MTD_SFDP_H
0009
0010 /* SFDP revisions */
0011 #define SFDP_JESD216_MAJOR  1
0012 #define SFDP_JESD216_MINOR  0
0013 #define SFDP_JESD216A_MINOR 5
0014 #define SFDP_JESD216B_MINOR 6
0015
0016 /* Basic Flash Parameter Table */
0017
0018 /*
0019  * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
0020  * They are indexed from 1 but C arrays are indexed from 0.
0021  */
0022 #define BFPT_DWORD(i)       ((i) - 1)
0023 #define BFPT_DWORD_MAX      20
0024
0025 struct sfdp_bfpt {
0026     u32 dwords[BFPT_DWORD_MAX];
0027 };
0028
0029 /* The first version of JESD216 defined only 9 DWORDs. */
0030 #define BFPT_DWORD_MAX_JESD216          9
0031 #define BFPT_DWORD_MAX_JESD216B         16
0032
0033 /* 1st DWORD. */
0034 #define BFPT_DWORD1_FAST_READ_1_1_2     BIT(16)
0035 #define BFPT_DWORD1_ADDRESS_BYTES_MASK      GENMASK(18, 17)
0036 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY    (0x0UL << 17)
0037 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4    (0x1UL << 17)
0038 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY    (0x2UL << 17)
0039 #define BFPT_DWORD1_DTR             BIT(19)
0040 #define BFPT_DWORD1_FAST_READ_1_2_2     BIT(20)
0041 #define BFPT_DWORD1_FAST_READ_1_4_4     BIT(21)
0042 #define BFPT_DWORD1_FAST_READ_1_1_4     BIT(22)
0043
0044 /* 5th DWORD. */
0045 #define BFPT_DWORD5_FAST_READ_2_2_2     BIT(0)
0046 #define BFPT_DWORD5_FAST_READ_4_4_4     BIT(4)
0047
0048 /* 11th DWORD. */
0049 #define BFPT_DWORD11_PAGE_SIZE_SHIFT        4
0050 #define BFPT_DWORD11_PAGE_SIZE_MASK     GENMASK(7, 4)
0051
0052 /* 15th DWORD. */
0053
0054 /*
0055  * (from JESD216 rev B)
0056  * Quad Enable Requirements (QER):
0057  * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
0058  *         reads based on instruction. DQ3/HOLD# functions are hold during
0059  *         instruction phase.
0060  * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
0061  *         two data bytes where bit 1 of the second byte is one.
0062  *         [...]
0063  *         Writing only one byte to the status register has the side-effect of
0064  *         clearing status register 2, including the QE bit. The 100b code is
0065  *         used if writing one byte to the status register does not modify
0066  *         status register 2.
0067  * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
0068  *         one data byte where bit 6 is one.
0069  *         [...]
0070  * - 011b: QE is bit 7 of status register 2. It is set via Write status
0071  *         register 2 instruction 3Eh with one data byte where bit 7 is one.
0072  *         [...]
0073  *         The status register 2 is read using instruction 3Fh.
0074  * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
0075  *         two data bytes where bit 1 of the second byte is one.
0076  *         [...]
0077  *         In contrast to the 001b code, writing one byte to the status
0078  *         register does not modify status register 2.
0079  * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
0080  *         Read Status instruction 05h. Status register2 is read using
0081  *         instruction 35h. QE is set via Write Status instruction 01h with
0082  *         two data bytes where bit 1 of the second byte is one.
0083  *         [...]
0084  */
0085 #define BFPT_DWORD15_QER_MASK           GENMASK(22, 20)
0086 #define BFPT_DWORD15_QER_NONE           (0x0UL << 20) /* Micron */
0087 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY     (0x1UL << 20)
0088 #define BFPT_DWORD15_QER_SR1_BIT6       (0x2UL << 20) /* Macronix */
0089 #define BFPT_DWORD15_QER_SR2_BIT7       (0x3UL << 20)
0090 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD     (0x4UL << 20)
0091 #define BFPT_DWORD15_QER_SR2_BIT1       (0x5UL << 20) /* Spansion */
0092
0093 #define BFPT_DWORD16_SWRST_EN_RST       BIT(12)
0094
0095 #define BFPT_DWORD18_CMD_EXT_MASK       GENMASK(30, 29)
0096 #define BFPT_DWORD18_CMD_EXT_REP        (0x0UL << 29) /* Repeat */
0097 #define BFPT_DWORD18_CMD_EXT_INV        (0x1UL << 29) /* Invert */
0098 #define BFPT_DWORD18_CMD_EXT_RES        (0x2UL << 29) /* Reserved */
0099 #define BFPT_DWORD18_CMD_EXT_16B        (0x3UL << 29) /* 16-bit opcode */
0100
0101 struct sfdp_parameter_header {
0102     u8      id_lsb;
0103     u8      minor;
0104     u8      major;
0105     u8      length; /* in double words */
0106     u8      parameter_table_pointer[3]; /* byte address */
0107     u8      id_msb;
0108 };
0109
0110 int spi_nor_parse_sfdp(struct spi_nor *nor);
0111
0112 #endif /* __LINUX_MTD_SFDP_H */