mtd/spi-nor/gigadevice.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2005, Intec Automation Inc.
0004  * Copyright (C) 2014, Freescale Semiconductor, Inc.
0005  */
0006
0007 #include <linux/mtd/spi-nor.h>
0008
0009 #include "core.h"
0010
0011 static void gd25q256_default_init(struct spi_nor *nor)
0012 {
0013     /*
0014      * Some manufacturer like GigaDevice may use different
0015      * bit to set QE on different memories, so the MFR can't
0016      * indicate the quad_enable method for this case, we need
0017      * to set it in the default_init fixup hook.
0018      */
0019     nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
0020 }
0021
0022 static const struct spi_nor_fixups gd25q256_fixups = {
0023     .default_init = gd25q256_default_init,
0024 };
0025
0026 static const struct flash_info gigadevice_nor_parts[] = {
0027     { "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32)
0028         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0029         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0030                   SPI_NOR_QUAD_READ) },
0031     { "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64)
0032         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0033         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0034                   SPI_NOR_QUAD_READ) },
0035     { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
0036         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0037         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0038                   SPI_NOR_QUAD_READ) },
0039     { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
0040         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0041         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0042                   SPI_NOR_QUAD_READ) },
0043     { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
0044         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0045         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0046                   SPI_NOR_QUAD_READ) },
0047     { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
0048         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0049         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0050                   SPI_NOR_QUAD_READ) },
0051     { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
0052         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
0053         NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
0054                   SPI_NOR_QUAD_READ) },
0055     { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512)
0056         PARSE_SFDP
0057         FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
0058         FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
0059         .fixups = &gd25q256_fixups },
0060 };
0061
0062 const struct spi_nor_manufacturer spi_nor_gigadevice = {
0063     .name = "gigadevice",
0064     .parts = gigadevice_nor_parts,
0065     .nparts = ARRAY_SIZE(gigadevice_nor_parts),
0066 };