spi-nor/controllers/nxp-spifi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
0004  *
0005  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0006  *
0007  * Based on Freescale QuadSPI driver:
0008  * Copyright (C) 2013 Freescale Semiconductor, Inc.
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/module.h>
0016 #include <linux/mtd/mtd.h>
0017 #include <linux/mtd/partitions.h>
0018 #include <linux/mtd/spi-nor.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/spi/spi.h>
0023
0024 /* NXP SPIFI registers, bits and macros */
0025 #define SPIFI_CTRL              0x000
0026 #define  SPIFI_CTRL_TIMEOUT(timeout)        (timeout)
0027 #define  SPIFI_CTRL_CSHIGH(cshigh)      ((cshigh) << 16)
0028 #define  SPIFI_CTRL_MODE3           BIT(23)
0029 #define  SPIFI_CTRL_DUAL            BIT(28)
0030 #define  SPIFI_CTRL_FBCLK           BIT(30)
0031 #define SPIFI_CMD               0x004
0032 #define  SPIFI_CMD_DATALEN(dlen)        ((dlen) & 0x3fff)
0033 #define  SPIFI_CMD_DOUT             BIT(15)
0034 #define  SPIFI_CMD_INTLEN(ilen)         ((ilen) << 16)
0035 #define  SPIFI_CMD_FIELDFORM(field)     ((field) << 19)
0036 #define  SPIFI_CMD_FIELDFORM_ALL_SERIAL     SPIFI_CMD_FIELDFORM(0x0)
0037 #define  SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1)
0038 #define  SPIFI_CMD_FRAMEFORM(frame)     ((frame) << 21)
0039 #define  SPIFI_CMD_FRAMEFORM_OPCODE_ONLY    SPIFI_CMD_FRAMEFORM(0x1)
0040 #define  SPIFI_CMD_OPCODE(op)           ((op) << 24)
0041 #define SPIFI_ADDR              0x008
0042 #define SPIFI_IDATA             0x00c
0043 #define SPIFI_CLIMIT                0x010
0044 #define SPIFI_DATA              0x014
0045 #define SPIFI_MCMD              0x018
0046 #define SPIFI_STAT              0x01c
0047 #define  SPIFI_STAT_MCINIT          BIT(0)
0048 #define  SPIFI_STAT_CMD             BIT(1)
0049 #define  SPIFI_STAT_RESET           BIT(4)
0050
0051 #define SPI_NOR_MAX_ID_LEN  6
0052
0053 struct nxp_spifi {
0054     struct device *dev;
0055     struct clk *clk_spifi;
0056     struct clk *clk_reg;
0057     void __iomem *io_base;
0058     void __iomem *flash_base;
0059     struct spi_nor nor;
0060     bool memory_mode;
0061     u32 mcmd;
0062 };
0063
0064 static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
0065 {
0066     u8 stat;
0067     int ret;
0068
0069     ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
0070                  !(stat & SPIFI_STAT_CMD), 10, 30);
0071     if (ret)
0072         dev_warn(spifi->dev, "command timed out\n");
0073
0074     return ret;
0075 }
0076
0077 static int nxp_spifi_reset(struct nxp_spifi *spifi)
0078 {
0079     u8 stat;
0080     int ret;
0081
0082     writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
0083     ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
0084                  !(stat & SPIFI_STAT_RESET), 10, 30);
0085     if (ret)
0086         dev_warn(spifi->dev, "state reset timed out\n");
0087
0088     return ret;
0089 }
0090
0091 static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
0092 {
0093     int ret;
0094
0095     if (!spifi->memory_mode)
0096         return 0;
0097
0098     ret = nxp_spifi_reset(spifi);
0099     if (ret)
0100         dev_err(spifi->dev, "unable to enter command mode\n");
0101     else
0102         spifi->memory_mode = false;
0103
0104     return ret;
0105 }
0106
0107 static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
0108 {
0109     u8 stat;
0110     int ret;
0111
0112     if (spifi->memory_mode)
0113         return 0;
0114
0115     writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
0116     ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
0117                  stat & SPIFI_STAT_MCINIT, 10, 30);
0118     if (ret)
0119         dev_err(spifi->dev, "unable to enter memory mode\n");
0120     else
0121         spifi->memory_mode = true;
0122
0123     return ret;
0124 }
0125
0126 static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
0127                   size_t len)
0128 {
0129     struct nxp_spifi *spifi = nor->priv;
0130     u32 cmd;
0131     int ret;
0132
0133     ret = nxp_spifi_set_memory_mode_off(spifi);
0134     if (ret)
0135         return ret;
0136
0137     cmd = SPIFI_CMD_DATALEN(len) |
0138           SPIFI_CMD_OPCODE(opcode) |
0139           SPIFI_CMD_FIELDFORM_ALL_SERIAL |
0140           SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
0141     writel(cmd, spifi->io_base + SPIFI_CMD);
0142
0143     while (len--)
0144         *buf++ = readb(spifi->io_base + SPIFI_DATA);
0145
0146     return nxp_spifi_wait_for_cmd(spifi);
0147 }
0148
0149 static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
0150                    size_t len)
0151 {
0152     struct nxp_spifi *spifi = nor->priv;
0153     u32 cmd;
0154     int ret;
0155
0156     ret = nxp_spifi_set_memory_mode_off(spifi);
0157     if (ret)
0158         return ret;
0159
0160     cmd = SPIFI_CMD_DOUT |
0161           SPIFI_CMD_DATALEN(len) |
0162           SPIFI_CMD_OPCODE(opcode) |
0163           SPIFI_CMD_FIELDFORM_ALL_SERIAL |
0164           SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
0165     writel(cmd, spifi->io_base + SPIFI_CMD);
0166
0167     while (len--)
0168         writeb(*buf++, spifi->io_base + SPIFI_DATA);
0169
0170     return nxp_spifi_wait_for_cmd(spifi);
0171 }
0172
0173 static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
0174                   u_char *buf)
0175 {
0176     struct nxp_spifi *spifi = nor->priv;
0177     int ret;
0178
0179     ret = nxp_spifi_set_memory_mode_on(spifi);
0180     if (ret)
0181         return ret;
0182
0183     memcpy_fromio(buf, spifi->flash_base + from, len);
0184
0185     return len;
0186 }
0187
0188 static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
0189                    const u_char *buf)
0190 {
0191     struct nxp_spifi *spifi = nor->priv;
0192     u32 cmd;
0193     int ret;
0194     size_t i;
0195
0196     ret = nxp_spifi_set_memory_mode_off(spifi);
0197     if (ret)
0198         return ret;
0199
0200     writel(to, spifi->io_base + SPIFI_ADDR);
0201
0202     cmd = SPIFI_CMD_DOUT |
0203           SPIFI_CMD_DATALEN(len) |
0204           SPIFI_CMD_FIELDFORM_ALL_SERIAL |
0205           SPIFI_CMD_OPCODE(nor->program_opcode) |
0206           SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
0207     writel(cmd, spifi->io_base + SPIFI_CMD);
0208
0209     for (i = 0; i < len; i++)
0210         writeb(buf[i], spifi->io_base + SPIFI_DATA);
0211
0212     ret = nxp_spifi_wait_for_cmd(spifi);
0213     if (ret)
0214         return ret;
0215
0216     return len;
0217 }
0218
0219 static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
0220 {
0221     struct nxp_spifi *spifi = nor->priv;
0222     u32 cmd;
0223     int ret;
0224
0225     ret = nxp_spifi_set_memory_mode_off(spifi);
0226     if (ret)
0227         return ret;
0228
0229     writel(offs, spifi->io_base + SPIFI_ADDR);
0230
0231     cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
0232           SPIFI_CMD_OPCODE(nor->erase_opcode) |
0233           SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
0234     writel(cmd, spifi->io_base + SPIFI_CMD);
0235
0236     return nxp_spifi_wait_for_cmd(spifi);
0237 }
0238
0239 static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
0240 {
0241     switch (spifi->nor.read_proto) {
0242     case SNOR_PROTO_1_1_1:
0243         spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
0244         break;
0245     case SNOR_PROTO_1_1_2:
0246     case SNOR_PROTO_1_1_4:
0247         spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
0248         break;
0249     default:
0250         dev_err(spifi->dev, "unsupported SPI read mode\n");
0251         return -EINVAL;
0252     }
0253
0254     /* Memory mode supports address length between 1 and 4 */
0255     if (spifi->nor.addr_nbytes < 1 || spifi->nor.addr_nbytes > 4)
0256         return -EINVAL;
0257
0258     spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
0259                SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
0260                SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
0261
0262     return 0;
0263 }
0264
0265 static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
0266 {
0267     u8 id[SPI_NOR_MAX_ID_LEN];
0268     nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
0269                       SPI_NOR_MAX_ID_LEN);
0270 }
0271
0272 static const struct spi_nor_controller_ops nxp_spifi_controller_ops = {
0273     .read_reg  = nxp_spifi_read_reg,
0274     .write_reg = nxp_spifi_write_reg,
0275     .read  = nxp_spifi_read,
0276     .write = nxp_spifi_write,
0277     .erase = nxp_spifi_erase,
0278 };
0279
0280 static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
0281                  struct device_node *np)
0282 {
0283     struct spi_nor_hwcaps hwcaps = {
0284         .mask = SNOR_HWCAPS_READ |
0285             SNOR_HWCAPS_READ_FAST |
0286             SNOR_HWCAPS_PP,
0287     };
0288     u32 ctrl, property;
0289     u16 mode = 0;
0290     int ret;
0291
0292     if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
0293         switch (property) {
0294         case 1:
0295             break;
0296         case 2:
0297             mode |= SPI_RX_DUAL;
0298             break;
0299         case 4:
0300             mode |= SPI_RX_QUAD;
0301             break;
0302         default:
0303             dev_err(spifi->dev, "unsupported rx-bus-width\n");
0304             return -EINVAL;
0305         }
0306     }
0307
0308     if (of_find_property(np, "spi-cpha", NULL))
0309         mode |= SPI_CPHA;
0310
0311     if (of_find_property(np, "spi-cpol", NULL))
0312         mode |= SPI_CPOL;
0313
0314     /* Setup control register defaults */
0315     ctrl = SPIFI_CTRL_TIMEOUT(1000) |
0316            SPIFI_CTRL_CSHIGH(15) |
0317            SPIFI_CTRL_FBCLK;
0318
0319     if (mode & SPI_RX_DUAL) {
0320         ctrl |= SPIFI_CTRL_DUAL;
0321         hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
0322     } else if (mode & SPI_RX_QUAD) {
0323         ctrl &= ~SPIFI_CTRL_DUAL;
0324         hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
0325     } else {
0326         ctrl |= SPIFI_CTRL_DUAL;
0327     }
0328
0329     switch (mode & SPI_MODE_X_MASK) {
0330     case SPI_MODE_0:
0331         ctrl &= ~SPIFI_CTRL_MODE3;
0332         break;
0333     case SPI_MODE_3:
0334         ctrl |= SPIFI_CTRL_MODE3;
0335         break;
0336     default:
0337         dev_err(spifi->dev, "only mode 0 and 3 supported\n");
0338         return -EINVAL;
0339     }
0340
0341     writel(ctrl, spifi->io_base + SPIFI_CTRL);
0342
0343     spifi->nor.dev   = spifi->dev;
0344     spi_nor_set_flash_node(&spifi->nor, np);
0345     spifi->nor.priv  = spifi;
0346     spifi->nor.controller_ops = &nxp_spifi_controller_ops;
0347
0348     /*
0349      * The first read on a hard reset isn't reliable so do a
0350      * dummy read of the id before calling spi_nor_scan().
0351      * The reason for this problem is unknown.
0352      *
0353      * The official NXP spifilib uses more or less the same
0354      * workaround that is applied here by reading the device
0355      * id multiple times.
0356      */
0357     nxp_spifi_dummy_id_read(&spifi->nor);
0358
0359     ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
0360     if (ret) {
0361         dev_err(spifi->dev, "device scan failed\n");
0362         return ret;
0363     }
0364
0365     ret = nxp_spifi_setup_memory_cmd(spifi);
0366     if (ret) {
0367         dev_err(spifi->dev, "memory command setup failed\n");
0368         return ret;
0369     }
0370
0371     ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
0372     if (ret) {
0373         dev_err(spifi->dev, "mtd device parse failed\n");
0374         return ret;
0375     }
0376
0377     return 0;
0378 }
0379
0380 static int nxp_spifi_probe(struct platform_device *pdev)
0381 {
0382     struct device_node *flash_np;
0383     struct nxp_spifi *spifi;
0384     int ret;
0385
0386     spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
0387     if (!spifi)
0388         return -ENOMEM;
0389
0390     spifi->io_base = devm_platform_ioremap_resource_byname(pdev, "spifi");
0391     if (IS_ERR(spifi->io_base))
0392         return PTR_ERR(spifi->io_base);
0393
0394     spifi->flash_base = devm_platform_ioremap_resource_byname(pdev, "flash");
0395     if (IS_ERR(spifi->flash_base))
0396         return PTR_ERR(spifi->flash_base);
0397
0398     spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
0399     if (IS_ERR(spifi->clk_spifi)) {
0400         dev_err(&pdev->dev, "spifi clock not found\n");
0401         return PTR_ERR(spifi->clk_spifi);
0402     }
0403
0404     spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
0405     if (IS_ERR(spifi->clk_reg)) {
0406         dev_err(&pdev->dev, "reg clock not found\n");
0407         return PTR_ERR(spifi->clk_reg);
0408     }
0409
0410     ret = clk_prepare_enable(spifi->clk_reg);
0411     if (ret) {
0412         dev_err(&pdev->dev, "unable to enable reg clock\n");
0413         return ret;
0414     }
0415
0416     ret = clk_prepare_enable(spifi->clk_spifi);
0417     if (ret) {
0418         dev_err(&pdev->dev, "unable to enable spifi clock\n");
0419         goto dis_clk_reg;
0420     }
0421
0422     spifi->dev = &pdev->dev;
0423     platform_set_drvdata(pdev, spifi);
0424
0425     /* Initialize and reset device */
0426     nxp_spifi_reset(spifi);
0427     writel(0, spifi->io_base + SPIFI_IDATA);
0428     writel(0, spifi->io_base + SPIFI_MCMD);
0429     nxp_spifi_reset(spifi);
0430
0431     flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
0432     if (!flash_np) {
0433         dev_err(&pdev->dev, "no SPI flash device to configure\n");
0434         ret = -ENODEV;
0435         goto dis_clks;
0436     }
0437
0438     ret = nxp_spifi_setup_flash(spifi, flash_np);
0439     of_node_put(flash_np);
0440     if (ret) {
0441         dev_err(&pdev->dev, "unable to setup flash chip\n");
0442         goto dis_clks;
0443     }
0444
0445     return 0;
0446
0447 dis_clks:
0448     clk_disable_unprepare(spifi->clk_spifi);
0449 dis_clk_reg:
0450     clk_disable_unprepare(spifi->clk_reg);
0451     return ret;
0452 }
0453
0454 static int nxp_spifi_remove(struct platform_device *pdev)
0455 {
0456     struct nxp_spifi *spifi = platform_get_drvdata(pdev);
0457
0458     mtd_device_unregister(&spifi->nor.mtd);
0459     clk_disable_unprepare(spifi->clk_spifi);
0460     clk_disable_unprepare(spifi->clk_reg);
0461
0462     return 0;
0463 }
0464
0465 static const struct of_device_id nxp_spifi_match[] = {
0466     {.compatible = "nxp,lpc1773-spifi"},
0467     { /* sentinel */ }
0468 };
0469 MODULE_DEVICE_TABLE(of, nxp_spifi_match);
0470
0471 static struct platform_driver nxp_spifi_driver = {
0472     .probe  = nxp_spifi_probe,
0473     .remove = nxp_spifi_remove,
0474     .driver = {
0475         .name = "nxp-spifi",
0476         .of_match_table = nxp_spifi_match,
0477     },
0478 };
0479 module_platform_driver(nxp_spifi_driver);
0480
0481 MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
0482 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
0483 MODULE_LICENSE("GPL v2");