spi-nor/controllers/hisi-sfc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * HiSilicon FMC SPI NOR flash controller driver
0004  *
0005  * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
0006  */
0007 #include <linux/bitops.h>
0008 #include <linux/clk.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/module.h>
0012 #include <linux/mtd/mtd.h>
0013 #include <linux/mtd/spi-nor.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017
0018 /* Hardware register offsets and field definitions */
0019 #define FMC_CFG             0x00
0020 #define FMC_CFG_OP_MODE_MASK        BIT_MASK(0)
0021 #define FMC_CFG_OP_MODE_BOOT        0
0022 #define FMC_CFG_OP_MODE_NORMAL      1
0023 #define FMC_CFG_FLASH_SEL(type)     (((type) & 0x3) << 1)
0024 #define FMC_CFG_FLASH_SEL_MASK      0x6
0025 #define FMC_ECC_TYPE(type)      (((type) & 0x7) << 5)
0026 #define FMC_ECC_TYPE_MASK       GENMASK(7, 5)
0027 #define SPI_NOR_ADDR_MODE_MASK      BIT_MASK(10)
0028 #define SPI_NOR_ADDR_MODE_3BYTES    (0x0 << 10)
0029 #define SPI_NOR_ADDR_MODE_4BYTES    (0x1 << 10)
0030 #define FMC_GLOBAL_CFG          0x04
0031 #define FMC_GLOBAL_CFG_WP_ENABLE    BIT(6)
0032 #define FMC_SPI_TIMING_CFG      0x08
0033 #define TIMING_CFG_TCSH(nr)     (((nr) & 0xf) << 8)
0034 #define TIMING_CFG_TCSS(nr)     (((nr) & 0xf) << 4)
0035 #define TIMING_CFG_TSHSL(nr)        ((nr) & 0xf)
0036 #define CS_HOLD_TIME            0x6
0037 #define CS_SETUP_TIME           0x6
0038 #define CS_DESELECT_TIME        0xf
0039 #define FMC_INT             0x18
0040 #define FMC_INT_OP_DONE         BIT(0)
0041 #define FMC_INT_CLR         0x20
0042 #define FMC_CMD             0x24
0043 #define FMC_CMD_CMD1(cmd)       ((cmd) & 0xff)
0044 #define FMC_ADDRL           0x2c
0045 #define FMC_OP_CFG          0x30
0046 #define OP_CFG_FM_CS(cs)        ((cs) << 11)
0047 #define OP_CFG_MEM_IF_TYPE(type)    (((type) & 0x7) << 7)
0048 #define OP_CFG_ADDR_NUM(addr)       (((addr) & 0x7) << 4)
0049 #define OP_CFG_DUMMY_NUM(dummy)     ((dummy) & 0xf)
0050 #define FMC_DATA_NUM            0x38
0051 #define FMC_DATA_NUM_CNT(cnt)       ((cnt) & GENMASK(13, 0))
0052 #define FMC_OP              0x3c
0053 #define FMC_OP_DUMMY_EN         BIT(8)
0054 #define FMC_OP_CMD1_EN          BIT(7)
0055 #define FMC_OP_ADDR_EN          BIT(6)
0056 #define FMC_OP_WRITE_DATA_EN        BIT(5)
0057 #define FMC_OP_READ_DATA_EN     BIT(2)
0058 #define FMC_OP_READ_STATUS_EN       BIT(1)
0059 #define FMC_OP_REG_OP_START     BIT(0)
0060 #define FMC_DMA_LEN         0x40
0061 #define FMC_DMA_LEN_SET(len)        ((len) & GENMASK(27, 0))
0062 #define FMC_DMA_SADDR_D0        0x4c
0063 #define HIFMC_DMA_MAX_LEN       (4096)
0064 #define HIFMC_DMA_MASK          (HIFMC_DMA_MAX_LEN - 1)
0065 #define FMC_OP_DMA          0x68
0066 #define OP_CTRL_RD_OPCODE(code)     (((code) & 0xff) << 16)
0067 #define OP_CTRL_WR_OPCODE(code)     (((code) & 0xff) << 8)
0068 #define OP_CTRL_RW_OP(op)       ((op) << 1)
0069 #define OP_CTRL_DMA_OP_READY        BIT(0)
0070 #define FMC_OP_READ         0x0
0071 #define FMC_OP_WRITE            0x1
0072 #define FMC_WAIT_TIMEOUT        1000000
0073
0074 enum hifmc_iftype {
0075     IF_TYPE_STD,
0076     IF_TYPE_DUAL,
0077     IF_TYPE_DIO,
0078     IF_TYPE_QUAD,
0079     IF_TYPE_QIO,
0080 };
0081
0082 struct hifmc_priv {
0083     u32 chipselect;
0084     u32 clkrate;
0085     struct hifmc_host *host;
0086 };
0087
0088 #define HIFMC_MAX_CHIP_NUM      2
0089 struct hifmc_host {
0090     struct device *dev;
0091     struct mutex lock;
0092
0093     void __iomem *regbase;
0094     void __iomem *iobase;
0095     struct clk *clk;
0096     void *buffer;
0097     dma_addr_t dma_buffer;
0098
0099     struct spi_nor  *nor[HIFMC_MAX_CHIP_NUM];
0100     u32 num_chip;
0101 };
0102
0103 static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
0104 {
0105     u32 reg;
0106
0107     return readl_poll_timeout(host->regbase + FMC_INT, reg,
0108         (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
0109 }
0110
0111 static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
0112 {
0113     enum hifmc_iftype if_type;
0114
0115     switch (proto) {
0116     case SNOR_PROTO_1_1_2:
0117         if_type = IF_TYPE_DUAL;
0118         break;
0119     case SNOR_PROTO_1_2_2:
0120         if_type = IF_TYPE_DIO;
0121         break;
0122     case SNOR_PROTO_1_1_4:
0123         if_type = IF_TYPE_QUAD;
0124         break;
0125     case SNOR_PROTO_1_4_4:
0126         if_type = IF_TYPE_QIO;
0127         break;
0128     case SNOR_PROTO_1_1_1:
0129     default:
0130         if_type = IF_TYPE_STD;
0131         break;
0132     }
0133
0134     return if_type;
0135 }
0136
0137 static void hisi_spi_nor_init(struct hifmc_host *host)
0138 {
0139     u32 reg;
0140
0141     reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
0142         | TIMING_CFG_TCSS(CS_SETUP_TIME)
0143         | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
0144     writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
0145 }
0146
0147 static int hisi_spi_nor_prep(struct spi_nor *nor)
0148 {
0149     struct hifmc_priv *priv = nor->priv;
0150     struct hifmc_host *host = priv->host;
0151     int ret;
0152
0153     mutex_lock(&host->lock);
0154
0155     ret = clk_set_rate(host->clk, priv->clkrate);
0156     if (ret)
0157         goto out;
0158
0159     ret = clk_prepare_enable(host->clk);
0160     if (ret)
0161         goto out;
0162
0163     return 0;
0164
0165 out:
0166     mutex_unlock(&host->lock);
0167     return ret;
0168 }
0169
0170 static void hisi_spi_nor_unprep(struct spi_nor *nor)
0171 {
0172     struct hifmc_priv *priv = nor->priv;
0173     struct hifmc_host *host = priv->host;
0174
0175     clk_disable_unprepare(host->clk);
0176     mutex_unlock(&host->lock);
0177 }
0178
0179 static int hisi_spi_nor_op_reg(struct spi_nor *nor,
0180                 u8 opcode, size_t len, u8 optype)
0181 {
0182     struct hifmc_priv *priv = nor->priv;
0183     struct hifmc_host *host = priv->host;
0184     u32 reg;
0185
0186     reg = FMC_CMD_CMD1(opcode);
0187     writel(reg, host->regbase + FMC_CMD);
0188
0189     reg = FMC_DATA_NUM_CNT(len);
0190     writel(reg, host->regbase + FMC_DATA_NUM);
0191
0192     reg = OP_CFG_FM_CS(priv->chipselect);
0193     writel(reg, host->regbase + FMC_OP_CFG);
0194
0195     writel(0xff, host->regbase + FMC_INT_CLR);
0196     reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
0197     writel(reg, host->regbase + FMC_OP);
0198
0199     return hisi_spi_nor_wait_op_finish(host);
0200 }
0201
0202 static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
0203                  size_t len)
0204 {
0205     struct hifmc_priv *priv = nor->priv;
0206     struct hifmc_host *host = priv->host;
0207     int ret;
0208
0209     ret = hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN);
0210     if (ret)
0211         return ret;
0212
0213     memcpy_fromio(buf, host->iobase, len);
0214     return 0;
0215 }
0216
0217 static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
0218                   const u8 *buf, size_t len)
0219 {
0220     struct hifmc_priv *priv = nor->priv;
0221     struct hifmc_host *host = priv->host;
0222
0223     if (len)
0224         memcpy_toio(host->iobase, buf, len);
0225
0226     return hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN);
0227 }
0228
0229 static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
0230         dma_addr_t dma_buf, size_t len, u8 op_type)
0231 {
0232     struct hifmc_priv *priv = nor->priv;
0233     struct hifmc_host *host = priv->host;
0234     u8 if_type = 0;
0235     u32 reg;
0236
0237     reg = readl(host->regbase + FMC_CFG);
0238     reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
0239     reg |= FMC_CFG_OP_MODE_NORMAL;
0240     reg |= (nor->addr_nbytes == 4) ? SPI_NOR_ADDR_MODE_4BYTES
0241         : SPI_NOR_ADDR_MODE_3BYTES;
0242     writel(reg, host->regbase + FMC_CFG);
0243
0244     writel(start_off, host->regbase + FMC_ADDRL);
0245     writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
0246     writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
0247
0248     reg = OP_CFG_FM_CS(priv->chipselect);
0249     if (op_type == FMC_OP_READ)
0250         if_type = hisi_spi_nor_get_if_type(nor->read_proto);
0251     else
0252         if_type = hisi_spi_nor_get_if_type(nor->write_proto);
0253     reg |= OP_CFG_MEM_IF_TYPE(if_type);
0254     if (op_type == FMC_OP_READ)
0255         reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
0256     writel(reg, host->regbase + FMC_OP_CFG);
0257
0258     writel(0xff, host->regbase + FMC_INT_CLR);
0259     reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
0260     reg |= (op_type == FMC_OP_READ)
0261         ? OP_CTRL_RD_OPCODE(nor->read_opcode)
0262         : OP_CTRL_WR_OPCODE(nor->program_opcode);
0263     writel(reg, host->regbase + FMC_OP_DMA);
0264
0265     return hisi_spi_nor_wait_op_finish(host);
0266 }
0267
0268 static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
0269         u_char *read_buf)
0270 {
0271     struct hifmc_priv *priv = nor->priv;
0272     struct hifmc_host *host = priv->host;
0273     size_t offset;
0274     int ret;
0275
0276     for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
0277         size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
0278
0279         ret = hisi_spi_nor_dma_transfer(nor,
0280             from + offset, host->dma_buffer, trans, FMC_OP_READ);
0281         if (ret) {
0282             dev_warn(nor->dev, "DMA read timeout\n");
0283             return ret;
0284         }
0285         memcpy(read_buf + offset, host->buffer, trans);
0286     }
0287
0288     return len;
0289 }
0290
0291 static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
0292             size_t len, const u_char *write_buf)
0293 {
0294     struct hifmc_priv *priv = nor->priv;
0295     struct hifmc_host *host = priv->host;
0296     size_t offset;
0297     int ret;
0298
0299     for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
0300         size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
0301
0302         memcpy(host->buffer, write_buf + offset, trans);
0303         ret = hisi_spi_nor_dma_transfer(nor,
0304             to + offset, host->dma_buffer, trans, FMC_OP_WRITE);
0305         if (ret) {
0306             dev_warn(nor->dev, "DMA write timeout\n");
0307             return ret;
0308         }
0309     }
0310
0311     return len;
0312 }
0313
0314 static const struct spi_nor_controller_ops hisi_controller_ops = {
0315     .prepare = hisi_spi_nor_prep,
0316     .unprepare = hisi_spi_nor_unprep,
0317     .read_reg = hisi_spi_nor_read_reg,
0318     .write_reg = hisi_spi_nor_write_reg,
0319     .read = hisi_spi_nor_read,
0320     .write = hisi_spi_nor_write,
0321 };
0322
0323 /*
0324  * Get spi flash device information and register it as a mtd device.
0325  */
0326 static int hisi_spi_nor_register(struct device_node *np,
0327                 struct hifmc_host *host)
0328 {
0329     const struct spi_nor_hwcaps hwcaps = {
0330         .mask = SNOR_HWCAPS_READ |
0331             SNOR_HWCAPS_READ_FAST |
0332             SNOR_HWCAPS_READ_1_1_2 |
0333             SNOR_HWCAPS_READ_1_1_4 |
0334             SNOR_HWCAPS_PP,
0335     };
0336     struct device *dev = host->dev;
0337     struct spi_nor *nor;
0338     struct hifmc_priv *priv;
0339     struct mtd_info *mtd;
0340     int ret;
0341
0342     nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
0343     if (!nor)
0344         return -ENOMEM;
0345
0346     nor->dev = dev;
0347     spi_nor_set_flash_node(nor, np);
0348
0349     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0350     if (!priv)
0351         return -ENOMEM;
0352
0353     ret = of_property_read_u32(np, "reg", &priv->chipselect);
0354     if (ret) {
0355         dev_err(dev, "There's no reg property for %pOF\n",
0356             np);
0357         return ret;
0358     }
0359
0360     ret = of_property_read_u32(np, "spi-max-frequency",
0361             &priv->clkrate);
0362     if (ret) {
0363         dev_err(dev, "There's no spi-max-frequency property for %pOF\n",
0364             np);
0365         return ret;
0366     }
0367     priv->host = host;
0368     nor->priv = priv;
0369     nor->controller_ops = &hisi_controller_ops;
0370
0371     ret = spi_nor_scan(nor, NULL, &hwcaps);
0372     if (ret)
0373         return ret;
0374
0375     mtd = &nor->mtd;
0376     mtd->name = np->name;
0377     ret = mtd_device_register(mtd, NULL, 0);
0378     if (ret)
0379         return ret;
0380
0381     host->nor[host->num_chip] = nor;
0382     host->num_chip++;
0383     return 0;
0384 }
0385
0386 static void hisi_spi_nor_unregister_all(struct hifmc_host *host)
0387 {
0388     int i;
0389
0390     for (i = 0; i < host->num_chip; i++)
0391         mtd_device_unregister(&host->nor[i]->mtd);
0392 }
0393
0394 static int hisi_spi_nor_register_all(struct hifmc_host *host)
0395 {
0396     struct device *dev = host->dev;
0397     struct device_node *np;
0398     int ret;
0399
0400     for_each_available_child_of_node(dev->of_node, np) {
0401         ret = hisi_spi_nor_register(np, host);
0402         if (ret) {
0403             of_node_put(np);
0404             goto fail;
0405         }
0406
0407         if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
0408             dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n");
0409             of_node_put(np);
0410             break;
0411         }
0412     }
0413
0414     return 0;
0415
0416 fail:
0417     hisi_spi_nor_unregister_all(host);
0418     return ret;
0419 }
0420
0421 static int hisi_spi_nor_probe(struct platform_device *pdev)
0422 {
0423     struct device *dev = &pdev->dev;
0424     struct hifmc_host *host;
0425     int ret;
0426
0427     host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
0428     if (!host)
0429         return -ENOMEM;
0430
0431     platform_set_drvdata(pdev, host);
0432     host->dev = dev;
0433
0434     host->regbase = devm_platform_ioremap_resource_byname(pdev, "control");
0435     if (IS_ERR(host->regbase))
0436         return PTR_ERR(host->regbase);
0437
0438     host->iobase = devm_platform_ioremap_resource_byname(pdev, "memory");
0439     if (IS_ERR(host->iobase))
0440         return PTR_ERR(host->iobase);
0441
0442     host->clk = devm_clk_get(dev, NULL);
0443     if (IS_ERR(host->clk))
0444         return PTR_ERR(host->clk);
0445
0446     ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0447     if (ret) {
0448         dev_warn(dev, "Unable to set dma mask\n");
0449         return ret;
0450     }
0451
0452     host->buffer = dmam_alloc_coherent(dev, HIFMC_DMA_MAX_LEN,
0453             &host->dma_buffer, GFP_KERNEL);
0454     if (!host->buffer)
0455         return -ENOMEM;
0456
0457     ret = clk_prepare_enable(host->clk);
0458     if (ret)
0459         return ret;
0460
0461     mutex_init(&host->lock);
0462     hisi_spi_nor_init(host);
0463     ret = hisi_spi_nor_register_all(host);
0464     if (ret)
0465         mutex_destroy(&host->lock);
0466
0467     clk_disable_unprepare(host->clk);
0468     return ret;
0469 }
0470
0471 static int hisi_spi_nor_remove(struct platform_device *pdev)
0472 {
0473     struct hifmc_host *host = platform_get_drvdata(pdev);
0474
0475     hisi_spi_nor_unregister_all(host);
0476     mutex_destroy(&host->lock);
0477     return 0;
0478 }
0479
0480 static const struct of_device_id hisi_spi_nor_dt_ids[] = {
0481     { .compatible = "hisilicon,fmc-spi-nor"},
0482     { /* sentinel */ }
0483 };
0484 MODULE_DEVICE_TABLE(of, hisi_spi_nor_dt_ids);
0485
0486 static struct platform_driver hisi_spi_nor_driver = {
0487     .driver = {
0488         .name   = "hisi-sfc",
0489         .of_match_table = hisi_spi_nor_dt_ids,
0490     },
0491     .probe  = hisi_spi_nor_probe,
0492     .remove = hisi_spi_nor_remove,
0493 };
0494 module_platform_driver(hisi_spi_nor_driver);
0495
0496 MODULE_LICENSE("GPL v2");
0497 MODULE_DESCRIPTION("HiSilicon SPI Nor Flash Controller Driver");