nand/raw/xway_nand.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright © 2012 John Crispin <john@phrozen.org>
0005  *  Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
0006  */
0007
0008 #include <linux/mtd/rawnand.h>
0009 #include <linux/of_gpio.h>
0010 #include <linux/of_platform.h>
0011
0012 #include <lantiq_soc.h>
0013
0014 /* nand registers */
0015 #define EBU_ADDSEL1     0x24
0016 #define EBU_NAND_CON        0xB0
0017 #define EBU_NAND_WAIT       0xB4
0018 #define  NAND_WAIT_RD       BIT(0) /* NAND flash status output */
0019 #define  NAND_WAIT_WR_C     BIT(3) /* NAND Write/Read complete */
0020 #define EBU_NAND_ECC0       0xB8
0021 #define EBU_NAND_ECC_AC     0xBC
0022
0023 /*
0024  * nand commands
0025  * The pins of the NAND chip are selected based on the address bits of the
0026  * "register" read and write. There are no special registers, but an
0027  * address range and the lower address bits are used to activate the
0028  * correct line. For example when the bit (1 << 2) is set in the address
0029  * the ALE pin will be activated.
0030  */
0031 #define NAND_CMD_ALE        BIT(2) /* address latch enable */
0032 #define NAND_CMD_CLE        BIT(3) /* command latch enable */
0033 #define NAND_CMD_CS     BIT(4) /* chip select */
0034 #define NAND_CMD_SE     BIT(5) /* spare area access latch */
0035 #define NAND_CMD_WP     BIT(6) /* write protect */
0036 #define NAND_WRITE_CMD      (NAND_CMD_CS | NAND_CMD_CLE)
0037 #define NAND_WRITE_ADDR     (NAND_CMD_CS | NAND_CMD_ALE)
0038 #define NAND_WRITE_DATA     (NAND_CMD_CS)
0039 #define NAND_READ_DATA      (NAND_CMD_CS)
0040
0041 /* we need to tel the ebu which addr we mapped the nand to */
0042 #define ADDSEL1_MASK(x)     (x << 4)
0043 #define ADDSEL1_REGEN       1
0044
0045 /* we need to tell the EBU that we have nand attached and set it up properly */
0046 #define BUSCON1_SETUP       (1 << 22)
0047 #define BUSCON1_BCGEN_RES   (0x3 << 12)
0048 #define BUSCON1_WAITWRC2    (2 << 8)
0049 #define BUSCON1_WAITRDC2    (2 << 6)
0050 #define BUSCON1_HOLDC1      (1 << 4)
0051 #define BUSCON1_RECOVC1     (1 << 2)
0052 #define BUSCON1_CMULT4      1
0053
0054 #define NAND_CON_CE     (1 << 20)
0055 #define NAND_CON_OUT_CS1    (1 << 10)
0056 #define NAND_CON_IN_CS1     (1 << 8)
0057 #define NAND_CON_PRE_P      (1 << 7)
0058 #define NAND_CON_WP_P       (1 << 6)
0059 #define NAND_CON_SE_P       (1 << 5)
0060 #define NAND_CON_CS_P       (1 << 4)
0061 #define NAND_CON_CSMUX      (1 << 1)
0062 #define NAND_CON_NANDM      1
0063
0064 struct xway_nand_data {
0065     struct nand_controller  controller;
0066     struct nand_chip    chip;
0067     unsigned long       csflags;
0068     void __iomem        *nandaddr;
0069 };
0070
0071 static u8 xway_readb(struct mtd_info *mtd, int op)
0072 {
0073     struct nand_chip *chip = mtd_to_nand(mtd);
0074     struct xway_nand_data *data = nand_get_controller_data(chip);
0075
0076     return readb(data->nandaddr + op);
0077 }
0078
0079 static void xway_writeb(struct mtd_info *mtd, int op, u8 value)
0080 {
0081     struct nand_chip *chip = mtd_to_nand(mtd);
0082     struct xway_nand_data *data = nand_get_controller_data(chip);
0083
0084     writeb(value, data->nandaddr + op);
0085 }
0086
0087 static void xway_select_chip(struct nand_chip *chip, int select)
0088 {
0089     struct xway_nand_data *data = nand_get_controller_data(chip);
0090
0091     switch (select) {
0092     case -1:
0093         ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
0094         ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
0095         spin_unlock_irqrestore(&ebu_lock, data->csflags);
0096         break;
0097     case 0:
0098         spin_lock_irqsave(&ebu_lock, data->csflags);
0099         ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
0100         ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
0101         break;
0102     default:
0103         BUG();
0104     }
0105 }
0106
0107 static void xway_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
0108 {
0109     struct mtd_info *mtd = nand_to_mtd(chip);
0110
0111     if (cmd == NAND_CMD_NONE)
0112         return;
0113
0114     if (ctrl & NAND_CLE)
0115         xway_writeb(mtd, NAND_WRITE_CMD, cmd);
0116     else if (ctrl & NAND_ALE)
0117         xway_writeb(mtd, NAND_WRITE_ADDR, cmd);
0118
0119     while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
0120         ;
0121 }
0122
0123 static int xway_dev_ready(struct nand_chip *chip)
0124 {
0125     return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
0126 }
0127
0128 static unsigned char xway_read_byte(struct nand_chip *chip)
0129 {
0130     return xway_readb(nand_to_mtd(chip), NAND_READ_DATA);
0131 }
0132
0133 static void xway_read_buf(struct nand_chip *chip, u_char *buf, int len)
0134 {
0135     int i;
0136
0137     for (i = 0; i < len; i++)
0138         buf[i] = xway_readb(nand_to_mtd(chip), NAND_WRITE_DATA);
0139 }
0140
0141 static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len)
0142 {
0143     int i;
0144
0145     for (i = 0; i < len; i++)
0146         xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]);
0147 }
0148
0149 static int xway_attach_chip(struct nand_chip *chip)
0150 {
0151     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
0152         chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
0153         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0154
0155     return 0;
0156 }
0157
0158 static const struct nand_controller_ops xway_nand_ops = {
0159     .attach_chip = xway_attach_chip,
0160 };
0161
0162 /*
0163  * Probe for the NAND device.
0164  */
0165 static int xway_nand_probe(struct platform_device *pdev)
0166 {
0167     struct xway_nand_data *data;
0168     struct mtd_info *mtd;
0169     int err;
0170     u32 cs;
0171     u32 cs_flag = 0;
0172
0173     /* Allocate memory for the device structure (and zero it) */
0174     data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
0175                 GFP_KERNEL);
0176     if (!data)
0177         return -ENOMEM;
0178
0179     data->nandaddr = devm_platform_ioremap_resource(pdev, 0);
0180     if (IS_ERR(data->nandaddr))
0181         return PTR_ERR(data->nandaddr);
0182
0183     nand_set_flash_node(&data->chip, pdev->dev.of_node);
0184     mtd = nand_to_mtd(&data->chip);
0185     mtd->dev.parent = &pdev->dev;
0186
0187     data->chip.legacy.cmd_ctrl = xway_cmd_ctrl;
0188     data->chip.legacy.dev_ready = xway_dev_ready;
0189     data->chip.legacy.select_chip = xway_select_chip;
0190     data->chip.legacy.write_buf = xway_write_buf;
0191     data->chip.legacy.read_buf = xway_read_buf;
0192     data->chip.legacy.read_byte = xway_read_byte;
0193     data->chip.legacy.chip_delay = 30;
0194
0195     nand_controller_init(&data->controller);
0196     data->controller.ops = &xway_nand_ops;
0197     data->chip.controller = &data->controller;
0198
0199     platform_set_drvdata(pdev, data);
0200     nand_set_controller_data(&data->chip, data);
0201
0202     /* load our CS from the DT. Either we find a valid 1 or default to 0 */
0203     err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);
0204     if (!err && cs == 1)
0205         cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
0206
0207     /* setup the EBU to run in NAND mode on our base addr */
0208     ltq_ebu_w32(CPHYSADDR(data->nandaddr)
0209             | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
0210
0211     ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
0212             | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
0213             | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
0214
0215     ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
0216             | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
0217             | cs_flag, EBU_NAND_CON);
0218
0219     /*
0220      * This driver assumes that the default ECC engine should be TYPE_SOFT.
0221      * Set ->engine_type before registering the NAND devices in order to
0222      * provide a driver specific default value.
0223      */
0224     data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0225
0226     /* Scan to find existence of the device */
0227     err = nand_scan(&data->chip, 1);
0228     if (err)
0229         return err;
0230
0231     err = mtd_device_register(mtd, NULL, 0);
0232     if (err)
0233         nand_cleanup(&data->chip);
0234
0235     return err;
0236 }
0237
0238 /*
0239  * Remove a NAND device.
0240  */
0241 static int xway_nand_remove(struct platform_device *pdev)
0242 {
0243     struct xway_nand_data *data = platform_get_drvdata(pdev);
0244     struct nand_chip *chip = &data->chip;
0245     int ret;
0246
0247     ret = mtd_device_unregister(nand_to_mtd(chip));
0248     WARN_ON(ret);
0249     nand_cleanup(chip);
0250
0251     return 0;
0252 }
0253
0254 static const struct of_device_id xway_nand_match[] = {
0255     { .compatible = "lantiq,nand-xway" },
0256     {},
0257 };
0258
0259 static struct platform_driver xway_nand_driver = {
0260     .probe  = xway_nand_probe,
0261     .remove = xway_nand_remove,
0262     .driver = {
0263         .name       = "lantiq,nand-xway",
0264         .of_match_table = xway_nand_match,
0265     },
0266 };
0267
0268 builtin_platform_driver(xway_nand_driver);