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0001 /*
0002  * Toshiba TMIO NAND flash controller driver
0003  *
0004  * Slightly murky pre-git history of the driver:
0005  *
0006  * Copyright (c) Ian Molton 2004, 2005, 2008
0007  *    Original work, independent of sharps code. Included hardware ECC support.
0008  *    Hard ECC did not work for writes in the early revisions.
0009  * Copyright (c) Dirk Opfer 2005.
0010  *    Modifications developed from sharps code but
0011  *    NOT containing any, ported onto Ians base.
0012  * Copyright (c) Chris Humbert 2005
0013  * Copyright (c) Dmitry Baryshkov 2008
0014  *    Minor fixes
0015  *
0016  * Parts copyright Sebastian Carlier
0017  *
0018  * This file is licensed under
0019  * the terms of the GNU General Public License version 2. This program
0020  * is licensed "as is" without any warranty of any kind, whether express
0021  * or implied.
0022  *
0023  */
0024 
0025 
0026 #include <linux/kernel.h>
0027 #include <linux/module.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/mfd/core.h>
0030 #include <linux/mfd/tmio.h>
0031 #include <linux/delay.h>
0032 #include <linux/io.h>
0033 #include <linux/irq.h>
0034 #include <linux/interrupt.h>
0035 #include <linux/ioport.h>
0036 #include <linux/mtd/mtd.h>
0037 #include <linux/mtd/rawnand.h>
0038 #include <linux/mtd/partitions.h>
0039 #include <linux/slab.h>
0040 
0041 /*--------------------------------------------------------------------------*/
0042 
0043 /*
0044  * NAND Flash Host Controller Configuration Register
0045  */
0046 #define CCR_COMMAND 0x04    /* w Command                */
0047 #define CCR_BASE    0x10    /* l NAND Flash Control Reg Base Addr   */
0048 #define CCR_INTP    0x3d    /* b Interrupt Pin          */
0049 #define CCR_INTE    0x48    /* b Interrupt Enable           */
0050 #define CCR_EC      0x4a    /* b Event Control          */
0051 #define CCR_ICC     0x4c    /* b Internal Clock Control     */
0052 #define CCR_ECCC    0x5b    /* b ECC Control            */
0053 #define CCR_NFTC    0x60    /* b NAND Flash Transaction Control */
0054 #define CCR_NFM     0x61    /* b NAND Flash Monitor         */
0055 #define CCR_NFPSC   0x62    /* b NAND Flash Power Supply Control    */
0056 #define CCR_NFDC    0x63    /* b NAND Flash Detect Control      */
0057 
0058 /*
0059  * NAND Flash Control Register
0060  */
0061 #define FCR_DATA    0x00    /* bwl Data Register            */
0062 #define FCR_MODE    0x04    /* b Mode Register          */
0063 #define FCR_STATUS  0x05    /* b Status Register            */
0064 #define FCR_ISR     0x06    /* b Interrupt Status Register      */
0065 #define FCR_IMR     0x07    /* b Interrupt Mask Register        */
0066 
0067 /* FCR_MODE Register Command List */
0068 #define FCR_MODE_DATA   0x94    /* Data Data_Mode */
0069 #define FCR_MODE_COMMAND 0x95   /* Data Command_Mode */
0070 #define FCR_MODE_ADDRESS 0x96   /* Data Address_Mode */
0071 
0072 #define FCR_MODE_HWECC_CALC 0xB4    /* HW-ECC Data */
0073 #define FCR_MODE_HWECC_RESULT   0xD4    /* HW-ECC Calc result Read_Mode */
0074 #define FCR_MODE_HWECC_RESET    0xF4    /* HW-ECC Reset */
0075 
0076 #define FCR_MODE_POWER_ON   0x0C    /* Power Supply ON  to SSFDC card */
0077 #define FCR_MODE_POWER_OFF  0x08    /* Power Supply OFF to SSFDC card */
0078 
0079 #define FCR_MODE_LED_OFF    0x00    /* LED OFF */
0080 #define FCR_MODE_LED_ON     0x04    /* LED ON */
0081 
0082 #define FCR_MODE_EJECT_ON   0x68    /* Ejection events active  */
0083 #define FCR_MODE_EJECT_OFF  0x08    /* Ejection events ignored */
0084 
0085 #define FCR_MODE_LOCK       0x6C    /* Lock_Mode. Eject Switch Invalid */
0086 #define FCR_MODE_UNLOCK     0x0C    /* UnLock_Mode. Eject Switch is valid */
0087 
0088 #define FCR_MODE_CONTROLLER_ID  0x40    /* Controller ID Read */
0089 #define FCR_MODE_STANDBY    0x00    /* SSFDC card Changes Standby State */
0090 
0091 #define FCR_MODE_WE     0x80
0092 #define FCR_MODE_ECC1       0x40
0093 #define FCR_MODE_ECC0       0x20
0094 #define FCR_MODE_CE     0x10
0095 #define FCR_MODE_PCNT1      0x08
0096 #define FCR_MODE_PCNT0      0x04
0097 #define FCR_MODE_ALE        0x02
0098 #define FCR_MODE_CLE        0x01
0099 
0100 #define FCR_STATUS_BUSY     0x80
0101 
0102 /*--------------------------------------------------------------------------*/
0103 
0104 struct tmio_nand {
0105     struct nand_controller controller;
0106     struct nand_chip chip;
0107     struct completion comp;
0108 
0109     struct platform_device *dev;
0110 
0111     void __iomem *ccr;
0112     void __iomem *fcr;
0113     unsigned long fcr_base;
0114 
0115     unsigned int irq;
0116 
0117     /* for tmio_nand_read_byte */
0118     u8          read;
0119     unsigned read_good:1;
0120 };
0121 
0122 static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
0123 {
0124     return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
0125 }
0126 
0127 
0128 /*--------------------------------------------------------------------------*/
0129 
0130 static void tmio_nand_hwcontrol(struct nand_chip *chip, int cmd,
0131                 unsigned int ctrl)
0132 {
0133     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0134 
0135     if (ctrl & NAND_CTRL_CHANGE) {
0136         u8 mode;
0137 
0138         if (ctrl & NAND_NCE) {
0139             mode = FCR_MODE_DATA;
0140 
0141             if (ctrl & NAND_CLE)
0142                 mode |=  FCR_MODE_CLE;
0143             else
0144                 mode &= ~FCR_MODE_CLE;
0145 
0146             if (ctrl & NAND_ALE)
0147                 mode |=  FCR_MODE_ALE;
0148             else
0149                 mode &= ~FCR_MODE_ALE;
0150         } else {
0151             mode = FCR_MODE_STANDBY;
0152         }
0153 
0154         tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
0155         tmio->read_good = 0;
0156     }
0157 
0158     if (cmd != NAND_CMD_NONE)
0159         tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W);
0160 }
0161 
0162 static int tmio_nand_dev_ready(struct nand_chip *chip)
0163 {
0164     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0165 
0166     return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
0167 }
0168 
0169 static irqreturn_t tmio_irq(int irq, void *__tmio)
0170 {
0171     struct tmio_nand *tmio = __tmio;
0172 
0173     /* disable RDYREQ interrupt */
0174     tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
0175     complete(&tmio->comp);
0176 
0177     return IRQ_HANDLED;
0178 }
0179 
0180 /*
0181   *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
0182   *This interrupt is normally disabled, but for long operations like
0183   *erase and write, we enable it to wake us up.  The irq handler
0184   *disables the interrupt.
0185  */
0186 static int tmio_nand_wait(struct nand_chip *nand_chip)
0187 {
0188     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(nand_chip));
0189     long timeout;
0190     u8 status;
0191 
0192     /* enable RDYREQ interrupt */
0193 
0194     tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
0195     reinit_completion(&tmio->comp);
0196     tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
0197 
0198     timeout = 400;
0199     timeout = wait_for_completion_timeout(&tmio->comp,
0200                           msecs_to_jiffies(timeout));
0201 
0202     if (unlikely(!tmio_nand_dev_ready(nand_chip))) {
0203         tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
0204         dev_warn(&tmio->dev->dev, "still busy after 400 ms\n");
0205 
0206     } else if (unlikely(!timeout)) {
0207         tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
0208         dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
0209     }
0210 
0211     nand_status_op(nand_chip, &status);
0212     return status;
0213 }
0214 
0215 /*
0216   *The TMIO controller combines two 8-bit data bytes into one 16-bit
0217   *word. This function separates them so nand_base.c works as expected,
0218   *especially its NAND_CMD_READID routines.
0219  *
0220   *To prevent stale data from being read, tmio_nand_hwcontrol() clears
0221   *tmio->read_good.
0222  */
0223 static u_char tmio_nand_read_byte(struct nand_chip *chip)
0224 {
0225     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0226     unsigned int data;
0227 
0228     if (tmio->read_good--)
0229         return tmio->read;
0230 
0231     data = tmio_ioread16(tmio->fcr + FCR_DATA);
0232     tmio->read = data >> 8;
0233     return data;
0234 }
0235 
0236 /*
0237   *The TMIO controller converts an 8-bit NAND interface to a 16-bit
0238   *bus interface, so all data reads and writes must be 16-bit wide.
0239   *Thus, we implement 16-bit versions of the read, write, and verify
0240   *buffer functions.
0241  */
0242 static void
0243 tmio_nand_write_buf(struct nand_chip *chip, const u_char *buf, int len)
0244 {
0245     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0246 
0247     tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
0248 }
0249 
0250 static void tmio_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
0251 {
0252     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0253 
0254     tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
0255 }
0256 
0257 static void tmio_nand_enable_hwecc(struct nand_chip *chip, int mode)
0258 {
0259     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0260 
0261     tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
0262     tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
0263     tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
0264 }
0265 
0266 static int tmio_nand_calculate_ecc(struct nand_chip *chip, const u_char *dat,
0267                    u_char *ecc_code)
0268 {
0269     struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
0270     unsigned int ecc;
0271 
0272     tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
0273 
0274     ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
0275     ecc_code[1] = ecc;  /* 000-255 LP7-0 */
0276     ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
0277     ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
0278     ecc_code[2] = ecc;  /* 000-255 CP5-0,11b */
0279     ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
0280     ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
0281     ecc_code[3] = ecc;  /* 256-511 LP15-8 */
0282     ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
0283 
0284     tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
0285     return 0;
0286 }
0287 
0288 static int tmio_nand_correct_data(struct nand_chip *chip, unsigned char *buf,
0289                   unsigned char *read_ecc,
0290                   unsigned char *calc_ecc)
0291 {
0292     int r0, r1;
0293 
0294     /* assume ecc.size = 512 and ecc.bytes = 6 */
0295     r0 = rawnand_sw_hamming_correct(chip, buf, read_ecc, calc_ecc);
0296     if (r0 < 0)
0297         return r0;
0298     r1 = rawnand_sw_hamming_correct(chip, buf + 256, read_ecc + 3,
0299                     calc_ecc + 3);
0300     if (r1 < 0)
0301         return r1;
0302     return r0 + r1;
0303 }
0304 
0305 static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
0306 {
0307     const struct mfd_cell *cell = mfd_get_cell(dev);
0308     int ret;
0309 
0310     if (cell->enable) {
0311         ret = cell->enable(dev);
0312         if (ret)
0313             return ret;
0314     }
0315 
0316     /* (4Ch) CLKRUN Enable    1st spcrunc */
0317     tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
0318 
0319     /* (10h)BaseAddress    0x1000 spba.spba2 */
0320     tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
0321     tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
0322 
0323     /* (04h)Command Register I/O spcmd */
0324     tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
0325 
0326     /* (62h) Power Supply Control ssmpwc */
0327     /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
0328     tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
0329 
0330     /* (63h) Detect Control ssmdtc */
0331     tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
0332 
0333     /* Interrupt status register clear sintst */
0334     tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
0335 
0336     /* After power supply, Media are reset smode */
0337     tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
0338     tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
0339     tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
0340 
0341     /* Standby Mode smode */
0342     tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
0343 
0344     mdelay(5);
0345 
0346     return 0;
0347 }
0348 
0349 static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
0350 {
0351     const struct mfd_cell *cell = mfd_get_cell(dev);
0352 
0353     tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
0354     if (cell->disable)
0355         cell->disable(dev);
0356 }
0357 
0358 static int tmio_attach_chip(struct nand_chip *chip)
0359 {
0360     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0361         return 0;
0362 
0363     chip->ecc.size = 512;
0364     chip->ecc.bytes = 6;
0365     chip->ecc.strength = 2;
0366     chip->ecc.hwctl = tmio_nand_enable_hwecc;
0367     chip->ecc.calculate = tmio_nand_calculate_ecc;
0368     chip->ecc.correct = tmio_nand_correct_data;
0369 
0370     return 0;
0371 }
0372 
0373 static const struct nand_controller_ops tmio_ops = {
0374     .attach_chip = tmio_attach_chip,
0375 };
0376 
0377 static int tmio_probe(struct platform_device *dev)
0378 {
0379     struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
0380     struct resource *fcr = platform_get_resource(dev,
0381             IORESOURCE_MEM, 0);
0382     struct resource *ccr = platform_get_resource(dev,
0383             IORESOURCE_MEM, 1);
0384     int irq = platform_get_irq(dev, 0);
0385     struct tmio_nand *tmio;
0386     struct mtd_info *mtd;
0387     struct nand_chip *nand_chip;
0388     int retval;
0389 
0390     if (data == NULL)
0391         dev_warn(&dev->dev, "NULL platform data!\n");
0392 
0393     if (!ccr || !fcr)
0394         return -EINVAL;
0395 
0396     tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
0397     if (!tmio)
0398         return -ENOMEM;
0399 
0400     init_completion(&tmio->comp);
0401 
0402     tmio->dev = dev;
0403 
0404     platform_set_drvdata(dev, tmio);
0405     nand_chip = &tmio->chip;
0406     mtd = nand_to_mtd(nand_chip);
0407     mtd->name = "tmio-nand";
0408     mtd->dev.parent = &dev->dev;
0409 
0410     nand_controller_init(&tmio->controller);
0411     tmio->controller.ops = &tmio_ops;
0412     nand_chip->controller = &tmio->controller;
0413 
0414     tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
0415     if (!tmio->ccr)
0416         return -EIO;
0417 
0418     tmio->fcr_base = fcr->start & 0xfffff;
0419     tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
0420     if (!tmio->fcr)
0421         return -EIO;
0422 
0423     retval = tmio_hw_init(dev, tmio);
0424     if (retval)
0425         return retval;
0426 
0427     /* Set address of NAND IO lines */
0428     nand_chip->legacy.IO_ADDR_R = tmio->fcr;
0429     nand_chip->legacy.IO_ADDR_W = tmio->fcr;
0430 
0431     /* Set address of hardware control function */
0432     nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol;
0433     nand_chip->legacy.dev_ready = tmio_nand_dev_ready;
0434     nand_chip->legacy.read_byte = tmio_nand_read_byte;
0435     nand_chip->legacy.write_buf = tmio_nand_write_buf;
0436     nand_chip->legacy.read_buf = tmio_nand_read_buf;
0437 
0438     if (data)
0439         nand_chip->badblock_pattern = data->badblock_pattern;
0440 
0441     /* 15 us command delay time */
0442     nand_chip->legacy.chip_delay = 15;
0443 
0444     retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
0445                   dev_name(&dev->dev), tmio);
0446     if (retval) {
0447         dev_err(&dev->dev, "request_irq error %d\n", retval);
0448         goto err_irq;
0449     }
0450 
0451     tmio->irq = irq;
0452     nand_chip->legacy.waitfunc = tmio_nand_wait;
0453 
0454     /* Scan to find existence of the device */
0455     retval = nand_scan(nand_chip, 1);
0456     if (retval)
0457         goto err_irq;
0458 
0459     /* Register the partitions */
0460     retval = mtd_device_parse_register(mtd,
0461                        data ? data->part_parsers : NULL,
0462                        NULL,
0463                        data ? data->partition : NULL,
0464                        data ? data->num_partitions : 0);
0465     if (!retval)
0466         return retval;
0467 
0468     nand_cleanup(nand_chip);
0469 
0470 err_irq:
0471     tmio_hw_stop(dev, tmio);
0472     return retval;
0473 }
0474 
0475 static int tmio_remove(struct platform_device *dev)
0476 {
0477     struct tmio_nand *tmio = platform_get_drvdata(dev);
0478     struct nand_chip *chip = &tmio->chip;
0479     int ret;
0480 
0481     ret = mtd_device_unregister(nand_to_mtd(chip));
0482     WARN_ON(ret);
0483     nand_cleanup(chip);
0484     tmio_hw_stop(dev, tmio);
0485     return 0;
0486 }
0487 
0488 #ifdef CONFIG_PM
0489 static int tmio_suspend(struct platform_device *dev, pm_message_t state)
0490 {
0491     const struct mfd_cell *cell = mfd_get_cell(dev);
0492 
0493     if (cell->suspend)
0494         cell->suspend(dev);
0495 
0496     tmio_hw_stop(dev, platform_get_drvdata(dev));
0497     return 0;
0498 }
0499 
0500 static int tmio_resume(struct platform_device *dev)
0501 {
0502     const struct mfd_cell *cell = mfd_get_cell(dev);
0503 
0504     /* FIXME - is this required or merely another attack of the broken
0505      * SHARP platform? Looks suspicious.
0506      */
0507     tmio_hw_init(dev, platform_get_drvdata(dev));
0508 
0509     if (cell->resume)
0510         cell->resume(dev);
0511 
0512     return 0;
0513 }
0514 #else
0515 #define tmio_suspend NULL
0516 #define tmio_resume NULL
0517 #endif
0518 
0519 static struct platform_driver tmio_driver = {
0520     .driver.name    = "tmio-nand",
0521     .driver.owner   = THIS_MODULE,
0522     .probe      = tmio_probe,
0523     .remove     = tmio_remove,
0524     .suspend    = tmio_suspend,
0525     .resume     = tmio_resume,
0526 };
0527 
0528 module_platform_driver(tmio_driver);
0529 
0530 MODULE_LICENSE("GPL v2");
0531 MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
0532 MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
0533 MODULE_ALIAS("platform:tmio-nand");
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