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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH FLCTL nand controller
0004  *
0005  * Copyright (c) 2008 Renesas Solutions Corp.
0006  * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
0007  *
0008  * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/completion.h>
0014 #include <linux/delay.h>
0015 #include <linux/dmaengine.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/sh_dma.h>
0024 #include <linux/slab.h>
0025 #include <linux/string.h>
0026 
0027 #include <linux/mtd/mtd.h>
0028 #include <linux/mtd/rawnand.h>
0029 #include <linux/mtd/partitions.h>
0030 #include <linux/mtd/sh_flctl.h>
0031 
0032 static int flctl_4secc_ooblayout_sp_ecc(struct mtd_info *mtd, int section,
0033                     struct mtd_oob_region *oobregion)
0034 {
0035     struct nand_chip *chip = mtd_to_nand(mtd);
0036 
0037     if (section)
0038         return -ERANGE;
0039 
0040     oobregion->offset = 0;
0041     oobregion->length = chip->ecc.bytes;
0042 
0043     return 0;
0044 }
0045 
0046 static int flctl_4secc_ooblayout_sp_free(struct mtd_info *mtd, int section,
0047                      struct mtd_oob_region *oobregion)
0048 {
0049     if (section)
0050         return -ERANGE;
0051 
0052     oobregion->offset = 12;
0053     oobregion->length = 4;
0054 
0055     return 0;
0056 }
0057 
0058 static const struct mtd_ooblayout_ops flctl_4secc_oob_smallpage_ops = {
0059     .ecc = flctl_4secc_ooblayout_sp_ecc,
0060     .free = flctl_4secc_ooblayout_sp_free,
0061 };
0062 
0063 static int flctl_4secc_ooblayout_lp_ecc(struct mtd_info *mtd, int section,
0064                     struct mtd_oob_region *oobregion)
0065 {
0066     struct nand_chip *chip = mtd_to_nand(mtd);
0067 
0068     if (section >= chip->ecc.steps)
0069         return -ERANGE;
0070 
0071     oobregion->offset = (section * 16) + 6;
0072     oobregion->length = chip->ecc.bytes;
0073 
0074     return 0;
0075 }
0076 
0077 static int flctl_4secc_ooblayout_lp_free(struct mtd_info *mtd, int section,
0078                      struct mtd_oob_region *oobregion)
0079 {
0080     struct nand_chip *chip = mtd_to_nand(mtd);
0081 
0082     if (section >= chip->ecc.steps)
0083         return -ERANGE;
0084 
0085     oobregion->offset = section * 16;
0086     oobregion->length = 6;
0087 
0088     if (!section) {
0089         oobregion->offset += 2;
0090         oobregion->length -= 2;
0091     }
0092 
0093     return 0;
0094 }
0095 
0096 static const struct mtd_ooblayout_ops flctl_4secc_oob_largepage_ops = {
0097     .ecc = flctl_4secc_ooblayout_lp_ecc,
0098     .free = flctl_4secc_ooblayout_lp_free,
0099 };
0100 
0101 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
0102 
0103 static struct nand_bbt_descr flctl_4secc_smallpage = {
0104     .offs = 11,
0105     .len = 1,
0106     .pattern = scan_ff_pattern,
0107 };
0108 
0109 static struct nand_bbt_descr flctl_4secc_largepage = {
0110     .offs = 0,
0111     .len = 2,
0112     .pattern = scan_ff_pattern,
0113 };
0114 
0115 static void empty_fifo(struct sh_flctl *flctl)
0116 {
0117     writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
0118     writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
0119 }
0120 
0121 static void start_translation(struct sh_flctl *flctl)
0122 {
0123     writeb(TRSTRT, FLTRCR(flctl));
0124 }
0125 
0126 static void timeout_error(struct sh_flctl *flctl, const char *str)
0127 {
0128     dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str);
0129 }
0130 
0131 static void wait_completion(struct sh_flctl *flctl)
0132 {
0133     uint32_t timeout = LOOP_TIMEOUT_MAX;
0134 
0135     while (timeout--) {
0136         if (readb(FLTRCR(flctl)) & TREND) {
0137             writeb(0x0, FLTRCR(flctl));
0138             return;
0139         }
0140         udelay(1);
0141     }
0142 
0143     timeout_error(flctl, __func__);
0144     writeb(0x0, FLTRCR(flctl));
0145 }
0146 
0147 static void flctl_dma_complete(void *param)
0148 {
0149     struct sh_flctl *flctl = param;
0150 
0151     complete(&flctl->dma_complete);
0152 }
0153 
0154 static void flctl_release_dma(struct sh_flctl *flctl)
0155 {
0156     if (flctl->chan_fifo0_rx) {
0157         dma_release_channel(flctl->chan_fifo0_rx);
0158         flctl->chan_fifo0_rx = NULL;
0159     }
0160     if (flctl->chan_fifo0_tx) {
0161         dma_release_channel(flctl->chan_fifo0_tx);
0162         flctl->chan_fifo0_tx = NULL;
0163     }
0164 }
0165 
0166 static void flctl_setup_dma(struct sh_flctl *flctl)
0167 {
0168     dma_cap_mask_t mask;
0169     struct dma_slave_config cfg;
0170     struct platform_device *pdev = flctl->pdev;
0171     struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev);
0172     int ret;
0173 
0174     if (!pdata)
0175         return;
0176 
0177     if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
0178         return;
0179 
0180     /* We can only either use DMA for both Tx and Rx or not use it at all */
0181     dma_cap_zero(mask);
0182     dma_cap_set(DMA_SLAVE, mask);
0183 
0184     flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
0185                 (void *)(uintptr_t)pdata->slave_id_fifo0_tx);
0186     dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
0187         flctl->chan_fifo0_tx);
0188 
0189     if (!flctl->chan_fifo0_tx)
0190         return;
0191 
0192     memset(&cfg, 0, sizeof(cfg));
0193     cfg.direction = DMA_MEM_TO_DEV;
0194     cfg.dst_addr = flctl->fifo;
0195     cfg.src_addr = 0;
0196     ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
0197     if (ret < 0)
0198         goto err;
0199 
0200     flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
0201                 (void *)(uintptr_t)pdata->slave_id_fifo0_rx);
0202     dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
0203         flctl->chan_fifo0_rx);
0204 
0205     if (!flctl->chan_fifo0_rx)
0206         goto err;
0207 
0208     cfg.direction = DMA_DEV_TO_MEM;
0209     cfg.dst_addr = 0;
0210     cfg.src_addr = flctl->fifo;
0211     ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
0212     if (ret < 0)
0213         goto err;
0214 
0215     init_completion(&flctl->dma_complete);
0216 
0217     return;
0218 
0219 err:
0220     flctl_release_dma(flctl);
0221 }
0222 
0223 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
0224 {
0225     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0226     uint32_t addr = 0;
0227 
0228     if (column == -1) {
0229         addr = page_addr;   /* ERASE1 */
0230     } else if (page_addr != -1) {
0231         /* SEQIN, READ0, etc.. */
0232         if (flctl->chip.options & NAND_BUSWIDTH_16)
0233             column >>= 1;
0234         if (flctl->page_size) {
0235             addr = column & 0x0FFF;
0236             addr |= (page_addr & 0xff) << 16;
0237             addr |= ((page_addr >> 8) & 0xff) << 24;
0238             /* big than 128MB */
0239             if (flctl->rw_ADRCNT == ADRCNT2_E) {
0240                 uint32_t    addr2;
0241                 addr2 = (page_addr >> 16) & 0xff;
0242                 writel(addr2, FLADR2(flctl));
0243             }
0244         } else {
0245             addr = column;
0246             addr |= (page_addr & 0xff) << 8;
0247             addr |= ((page_addr >> 8) & 0xff) << 16;
0248             addr |= ((page_addr >> 16) & 0xff) << 24;
0249         }
0250     }
0251     writel(addr, FLADR(flctl));
0252 }
0253 
0254 static void wait_rfifo_ready(struct sh_flctl *flctl)
0255 {
0256     uint32_t timeout = LOOP_TIMEOUT_MAX;
0257 
0258     while (timeout--) {
0259         uint32_t val;
0260         /* check FIFO */
0261         val = readl(FLDTCNTR(flctl)) >> 16;
0262         if (val & 0xFF)
0263             return;
0264         udelay(1);
0265     }
0266     timeout_error(flctl, __func__);
0267 }
0268 
0269 static void wait_wfifo_ready(struct sh_flctl *flctl)
0270 {
0271     uint32_t len, timeout = LOOP_TIMEOUT_MAX;
0272 
0273     while (timeout--) {
0274         /* check FIFO */
0275         len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
0276         if (len >= 4)
0277             return;
0278         udelay(1);
0279     }
0280     timeout_error(flctl, __func__);
0281 }
0282 
0283 static enum flctl_ecc_res_t wait_recfifo_ready
0284         (struct sh_flctl *flctl, int sector_number)
0285 {
0286     uint32_t timeout = LOOP_TIMEOUT_MAX;
0287     void __iomem *ecc_reg[4];
0288     int i;
0289     int state = FL_SUCCESS;
0290     uint32_t data, size;
0291 
0292     /*
0293      * First this loops checks in FLDTCNTR if we are ready to read out the
0294      * oob data. This is the case if either all went fine without errors or
0295      * if the bottom part of the loop corrected the errors or marked them as
0296      * uncorrectable and the controller is given time to push the data into
0297      * the FIFO.
0298      */
0299     while (timeout--) {
0300         /* check if all is ok and we can read out the OOB */
0301         size = readl(FLDTCNTR(flctl)) >> 24;
0302         if ((size & 0xFF) == 4)
0303             return state;
0304 
0305         /* check if a correction code has been calculated */
0306         if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) {
0307             /*
0308              * either we wait for the fifo to be filled or a
0309              * correction pattern is being generated
0310              */
0311             udelay(1);
0312             continue;
0313         }
0314 
0315         /* check for an uncorrectable error */
0316         if (readl(FL4ECCCR(flctl)) & _4ECCFA) {
0317             /* check if we face a non-empty page */
0318             for (i = 0; i < 512; i++) {
0319                 if (flctl->done_buff[i] != 0xff) {
0320                     state = FL_ERROR; /* can't correct */
0321                     break;
0322                 }
0323             }
0324 
0325             if (state == FL_SUCCESS)
0326                 dev_dbg(&flctl->pdev->dev,
0327                 "reading empty sector %d, ecc error ignored\n",
0328                 sector_number);
0329 
0330             writel(0, FL4ECCCR(flctl));
0331             continue;
0332         }
0333 
0334         /* start error correction */
0335         ecc_reg[0] = FL4ECCRESULT0(flctl);
0336         ecc_reg[1] = FL4ECCRESULT1(flctl);
0337         ecc_reg[2] = FL4ECCRESULT2(flctl);
0338         ecc_reg[3] = FL4ECCRESULT3(flctl);
0339 
0340         for (i = 0; i < 3; i++) {
0341             uint8_t org;
0342             unsigned int index;
0343 
0344             data = readl(ecc_reg[i]);
0345 
0346             if (flctl->page_size)
0347                 index = (512 * sector_number) +
0348                     (data >> 16);
0349             else
0350                 index = data >> 16;
0351 
0352             org = flctl->done_buff[index];
0353             flctl->done_buff[index] = org ^ (data & 0xFF);
0354         }
0355         state = FL_REPAIRABLE;
0356         writel(0, FL4ECCCR(flctl));
0357     }
0358 
0359     timeout_error(flctl, __func__);
0360     return FL_TIMEOUT;  /* timeout */
0361 }
0362 
0363 static void wait_wecfifo_ready(struct sh_flctl *flctl)
0364 {
0365     uint32_t timeout = LOOP_TIMEOUT_MAX;
0366     uint32_t len;
0367 
0368     while (timeout--) {
0369         /* check FLECFIFO */
0370         len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
0371         if (len >= 4)
0372             return;
0373         udelay(1);
0374     }
0375     timeout_error(flctl, __func__);
0376 }
0377 
0378 static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
0379                     int len, enum dma_data_direction dir)
0380 {
0381     struct dma_async_tx_descriptor *desc = NULL;
0382     struct dma_chan *chan;
0383     enum dma_transfer_direction tr_dir;
0384     dma_addr_t dma_addr;
0385     dma_cookie_t cookie;
0386     uint32_t reg;
0387     int ret = 0;
0388     unsigned long time_left;
0389 
0390     if (dir == DMA_FROM_DEVICE) {
0391         chan = flctl->chan_fifo0_rx;
0392         tr_dir = DMA_DEV_TO_MEM;
0393     } else {
0394         chan = flctl->chan_fifo0_tx;
0395         tr_dir = DMA_MEM_TO_DEV;
0396     }
0397 
0398     dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
0399 
0400     if (!dma_mapping_error(chan->device->dev, dma_addr))
0401         desc = dmaengine_prep_slave_single(chan, dma_addr, len,
0402             tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0403 
0404     if (desc) {
0405         reg = readl(FLINTDMACR(flctl));
0406         reg |= DREQ0EN;
0407         writel(reg, FLINTDMACR(flctl));
0408 
0409         desc->callback = flctl_dma_complete;
0410         desc->callback_param = flctl;
0411         cookie = dmaengine_submit(desc);
0412         if (dma_submit_error(cookie)) {
0413             ret = dma_submit_error(cookie);
0414             dev_warn(&flctl->pdev->dev,
0415                  "DMA submit failed, falling back to PIO\n");
0416             goto out;
0417         }
0418 
0419         dma_async_issue_pending(chan);
0420     } else {
0421         /* DMA failed, fall back to PIO */
0422         flctl_release_dma(flctl);
0423         dev_warn(&flctl->pdev->dev,
0424              "DMA failed, falling back to PIO\n");
0425         ret = -EIO;
0426         goto out;
0427     }
0428 
0429     time_left =
0430     wait_for_completion_timeout(&flctl->dma_complete,
0431                 msecs_to_jiffies(3000));
0432 
0433     if (time_left == 0) {
0434         dmaengine_terminate_all(chan);
0435         dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
0436         ret = -ETIMEDOUT;
0437     }
0438 
0439 out:
0440     reg = readl(FLINTDMACR(flctl));
0441     reg &= ~DREQ0EN;
0442     writel(reg, FLINTDMACR(flctl));
0443 
0444     dma_unmap_single(chan->device->dev, dma_addr, len, dir);
0445 
0446     /* ret == 0 is success */
0447     return ret;
0448 }
0449 
0450 static void read_datareg(struct sh_flctl *flctl, int offset)
0451 {
0452     unsigned long data;
0453     unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
0454 
0455     wait_completion(flctl);
0456 
0457     data = readl(FLDATAR(flctl));
0458     *buf = le32_to_cpu(data);
0459 }
0460 
0461 static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
0462 {
0463     int i, len_4align;
0464     unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
0465 
0466     len_4align = (rlen + 3) / 4;
0467 
0468     /* initiate DMA transfer */
0469     if (flctl->chan_fifo0_rx && rlen >= 32 &&
0470         !flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_FROM_DEVICE))
0471             goto convert;   /* DMA success */
0472 
0473     /* do polling transfer */
0474     for (i = 0; i < len_4align; i++) {
0475         wait_rfifo_ready(flctl);
0476         buf[i] = readl(FLDTFIFO(flctl));
0477     }
0478 
0479 convert:
0480     for (i = 0; i < len_4align; i++)
0481         buf[i] = be32_to_cpu(buf[i]);
0482 }
0483 
0484 static enum flctl_ecc_res_t read_ecfiforeg
0485         (struct sh_flctl *flctl, uint8_t *buff, int sector)
0486 {
0487     int i;
0488     enum flctl_ecc_res_t res;
0489     unsigned long *ecc_buf = (unsigned long *)buff;
0490 
0491     res = wait_recfifo_ready(flctl , sector);
0492 
0493     if (res != FL_ERROR) {
0494         for (i = 0; i < 4; i++) {
0495             ecc_buf[i] = readl(FLECFIFO(flctl));
0496             ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
0497         }
0498     }
0499 
0500     return res;
0501 }
0502 
0503 static void write_fiforeg(struct sh_flctl *flctl, int rlen,
0504                         unsigned int offset)
0505 {
0506     int i, len_4align;
0507     unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
0508 
0509     len_4align = (rlen + 3) / 4;
0510     for (i = 0; i < len_4align; i++) {
0511         wait_wfifo_ready(flctl);
0512         writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
0513     }
0514 }
0515 
0516 static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
0517                         unsigned int offset)
0518 {
0519     int i, len_4align;
0520     unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
0521 
0522     len_4align = (rlen + 3) / 4;
0523 
0524     for (i = 0; i < len_4align; i++)
0525         buf[i] = cpu_to_be32(buf[i]);
0526 
0527     /* initiate DMA transfer */
0528     if (flctl->chan_fifo0_tx && rlen >= 32 &&
0529         !flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_TO_DEVICE))
0530             return; /* DMA success */
0531 
0532     /* do polling transfer */
0533     for (i = 0; i < len_4align; i++) {
0534         wait_wecfifo_ready(flctl);
0535         writel(buf[i], FLECFIFO(flctl));
0536     }
0537 }
0538 
0539 static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
0540 {
0541     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0542     uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
0543     uint32_t flcmdcr_val, addr_len_bytes = 0;
0544 
0545     /* Set SNAND bit if page size is 2048byte */
0546     if (flctl->page_size)
0547         flcmncr_val |= SNAND_E;
0548     else
0549         flcmncr_val &= ~SNAND_E;
0550 
0551     /* default FLCMDCR val */
0552     flcmdcr_val = DOCMD1_E | DOADR_E;
0553 
0554     /* Set for FLCMDCR */
0555     switch (cmd) {
0556     case NAND_CMD_ERASE1:
0557         addr_len_bytes = flctl->erase_ADRCNT;
0558         flcmdcr_val |= DOCMD2_E;
0559         break;
0560     case NAND_CMD_READ0:
0561     case NAND_CMD_READOOB:
0562     case NAND_CMD_RNDOUT:
0563         addr_len_bytes = flctl->rw_ADRCNT;
0564         flcmdcr_val |= CDSRC_E;
0565         if (flctl->chip.options & NAND_BUSWIDTH_16)
0566             flcmncr_val |= SEL_16BIT;
0567         break;
0568     case NAND_CMD_SEQIN:
0569         /* This case is that cmd is READ0 or READ1 or READ00 */
0570         flcmdcr_val &= ~DOADR_E;    /* ONLY execute 1st cmd */
0571         break;
0572     case NAND_CMD_PAGEPROG:
0573         addr_len_bytes = flctl->rw_ADRCNT;
0574         flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
0575         if (flctl->chip.options & NAND_BUSWIDTH_16)
0576             flcmncr_val |= SEL_16BIT;
0577         break;
0578     case NAND_CMD_READID:
0579         flcmncr_val &= ~SNAND_E;
0580         flcmdcr_val |= CDSRC_E;
0581         addr_len_bytes = ADRCNT_1;
0582         break;
0583     case NAND_CMD_STATUS:
0584     case NAND_CMD_RESET:
0585         flcmncr_val &= ~SNAND_E;
0586         flcmdcr_val &= ~(DOADR_E | DOSR_E);
0587         break;
0588     default:
0589         break;
0590     }
0591 
0592     /* Set address bytes parameter */
0593     flcmdcr_val |= addr_len_bytes;
0594 
0595     /* Now actually write */
0596     writel(flcmncr_val, FLCMNCR(flctl));
0597     writel(flcmdcr_val, FLCMDCR(flctl));
0598     writel(flcmcdr_val, FLCMCDR(flctl));
0599 }
0600 
0601 static int flctl_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
0602                  int oob_required, int page)
0603 {
0604     struct mtd_info *mtd = nand_to_mtd(chip);
0605 
0606     nand_read_page_op(chip, page, 0, buf, mtd->writesize);
0607     if (oob_required)
0608         chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
0609     return 0;
0610 }
0611 
0612 static int flctl_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
0613                   int oob_required, int page)
0614 {
0615     struct mtd_info *mtd = nand_to_mtd(chip);
0616 
0617     nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
0618     chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
0619     return nand_prog_page_end_op(chip);
0620 }
0621 
0622 static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
0623 {
0624     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0625     int sector, page_sectors;
0626     enum flctl_ecc_res_t ecc_result;
0627 
0628     page_sectors = flctl->page_size ? 4 : 1;
0629 
0630     set_cmd_regs(mtd, NAND_CMD_READ0,
0631         (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
0632 
0633     writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
0634          FLCMNCR(flctl));
0635     writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
0636     writel(page_addr << 2, FLADR(flctl));
0637 
0638     empty_fifo(flctl);
0639     start_translation(flctl);
0640 
0641     for (sector = 0; sector < page_sectors; sector++) {
0642         read_fiforeg(flctl, 512, 512 * sector);
0643 
0644         ecc_result = read_ecfiforeg(flctl,
0645             &flctl->done_buff[mtd->writesize + 16 * sector],
0646             sector);
0647 
0648         switch (ecc_result) {
0649         case FL_REPAIRABLE:
0650             dev_info(&flctl->pdev->dev,
0651                 "applied ecc on page 0x%x", page_addr);
0652             mtd->ecc_stats.corrected++;
0653             break;
0654         case FL_ERROR:
0655             dev_warn(&flctl->pdev->dev,
0656                 "page 0x%x contains corrupted data\n",
0657                 page_addr);
0658             mtd->ecc_stats.failed++;
0659             break;
0660         default:
0661             ;
0662         }
0663     }
0664 
0665     wait_completion(flctl);
0666 
0667     writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
0668             FLCMNCR(flctl));
0669 }
0670 
0671 static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
0672 {
0673     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0674     int page_sectors = flctl->page_size ? 4 : 1;
0675     int i;
0676 
0677     set_cmd_regs(mtd, NAND_CMD_READ0,
0678         (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
0679 
0680     empty_fifo(flctl);
0681 
0682     for (i = 0; i < page_sectors; i++) {
0683         set_addr(mtd, (512 + 16) * i + 512 , page_addr);
0684         writel(16, FLDTCNTR(flctl));
0685 
0686         start_translation(flctl);
0687         read_fiforeg(flctl, 16, 16 * i);
0688         wait_completion(flctl);
0689     }
0690 }
0691 
0692 static void execmd_write_page_sector(struct mtd_info *mtd)
0693 {
0694     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0695     int page_addr = flctl->seqin_page_addr;
0696     int sector, page_sectors;
0697 
0698     page_sectors = flctl->page_size ? 4 : 1;
0699 
0700     set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
0701             (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
0702 
0703     empty_fifo(flctl);
0704     writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
0705     writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
0706     writel(page_addr << 2, FLADR(flctl));
0707     start_translation(flctl);
0708 
0709     for (sector = 0; sector < page_sectors; sector++) {
0710         write_fiforeg(flctl, 512, 512 * sector);
0711         write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector);
0712     }
0713 
0714     wait_completion(flctl);
0715     writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
0716 }
0717 
0718 static void execmd_write_oob(struct mtd_info *mtd)
0719 {
0720     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0721     int page_addr = flctl->seqin_page_addr;
0722     int sector, page_sectors;
0723 
0724     page_sectors = flctl->page_size ? 4 : 1;
0725 
0726     set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
0727             (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
0728 
0729     for (sector = 0; sector < page_sectors; sector++) {
0730         empty_fifo(flctl);
0731         set_addr(mtd, sector * 528 + 512, page_addr);
0732         writel(16, FLDTCNTR(flctl));    /* set read size */
0733 
0734         start_translation(flctl);
0735         write_fiforeg(flctl, 16, 16 * sector);
0736         wait_completion(flctl);
0737     }
0738 }
0739 
0740 static void flctl_cmdfunc(struct nand_chip *chip, unsigned int command,
0741             int column, int page_addr)
0742 {
0743     struct mtd_info *mtd = nand_to_mtd(chip);
0744     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0745     uint32_t read_cmd = 0;
0746 
0747     pm_runtime_get_sync(&flctl->pdev->dev);
0748 
0749     flctl->read_bytes = 0;
0750     if (command != NAND_CMD_PAGEPROG)
0751         flctl->index = 0;
0752 
0753     switch (command) {
0754     case NAND_CMD_READ1:
0755     case NAND_CMD_READ0:
0756         if (flctl->hwecc) {
0757             /* read page with hwecc */
0758             execmd_read_page_sector(mtd, page_addr);
0759             break;
0760         }
0761         if (flctl->page_size)
0762             set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
0763                 | command);
0764         else
0765             set_cmd_regs(mtd, command, command);
0766 
0767         set_addr(mtd, 0, page_addr);
0768 
0769         flctl->read_bytes = mtd->writesize + mtd->oobsize;
0770         if (flctl->chip.options & NAND_BUSWIDTH_16)
0771             column >>= 1;
0772         flctl->index += column;
0773         goto read_normal_exit;
0774 
0775     case NAND_CMD_READOOB:
0776         if (flctl->hwecc) {
0777             /* read page with hwecc */
0778             execmd_read_oob(mtd, page_addr);
0779             break;
0780         }
0781 
0782         if (flctl->page_size) {
0783             set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
0784                 | NAND_CMD_READ0);
0785             set_addr(mtd, mtd->writesize, page_addr);
0786         } else {
0787             set_cmd_regs(mtd, command, command);
0788             set_addr(mtd, 0, page_addr);
0789         }
0790         flctl->read_bytes = mtd->oobsize;
0791         goto read_normal_exit;
0792 
0793     case NAND_CMD_RNDOUT:
0794         if (flctl->hwecc)
0795             break;
0796 
0797         if (flctl->page_size)
0798             set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
0799                 | command);
0800         else
0801             set_cmd_regs(mtd, command, command);
0802 
0803         set_addr(mtd, column, 0);
0804 
0805         flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
0806         goto read_normal_exit;
0807 
0808     case NAND_CMD_READID:
0809         set_cmd_regs(mtd, command, command);
0810 
0811         /* READID is always performed using an 8-bit bus */
0812         if (flctl->chip.options & NAND_BUSWIDTH_16)
0813             column <<= 1;
0814         set_addr(mtd, column, 0);
0815 
0816         flctl->read_bytes = 8;
0817         writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
0818         empty_fifo(flctl);
0819         start_translation(flctl);
0820         read_fiforeg(flctl, flctl->read_bytes, 0);
0821         wait_completion(flctl);
0822         break;
0823 
0824     case NAND_CMD_ERASE1:
0825         flctl->erase1_page_addr = page_addr;
0826         break;
0827 
0828     case NAND_CMD_ERASE2:
0829         set_cmd_regs(mtd, NAND_CMD_ERASE1,
0830             (command << 8) | NAND_CMD_ERASE1);
0831         set_addr(mtd, -1, flctl->erase1_page_addr);
0832         start_translation(flctl);
0833         wait_completion(flctl);
0834         break;
0835 
0836     case NAND_CMD_SEQIN:
0837         if (!flctl->page_size) {
0838             /* output read command */
0839             if (column >= mtd->writesize) {
0840                 column -= mtd->writesize;
0841                 read_cmd = NAND_CMD_READOOB;
0842             } else if (column < 256) {
0843                 read_cmd = NAND_CMD_READ0;
0844             } else {
0845                 column -= 256;
0846                 read_cmd = NAND_CMD_READ1;
0847             }
0848         }
0849         flctl->seqin_column = column;
0850         flctl->seqin_page_addr = page_addr;
0851         flctl->seqin_read_cmd = read_cmd;
0852         break;
0853 
0854     case NAND_CMD_PAGEPROG:
0855         empty_fifo(flctl);
0856         if (!flctl->page_size) {
0857             set_cmd_regs(mtd, NAND_CMD_SEQIN,
0858                     flctl->seqin_read_cmd);
0859             set_addr(mtd, -1, -1);
0860             writel(0, FLDTCNTR(flctl)); /* set 0 size */
0861             start_translation(flctl);
0862             wait_completion(flctl);
0863         }
0864         if (flctl->hwecc) {
0865             /* write page with hwecc */
0866             if (flctl->seqin_column == mtd->writesize)
0867                 execmd_write_oob(mtd);
0868             else if (!flctl->seqin_column)
0869                 execmd_write_page_sector(mtd);
0870             else
0871                 pr_err("Invalid address !?\n");
0872             break;
0873         }
0874         set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
0875         set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
0876         writel(flctl->index, FLDTCNTR(flctl));  /* set write size */
0877         start_translation(flctl);
0878         write_fiforeg(flctl, flctl->index, 0);
0879         wait_completion(flctl);
0880         break;
0881 
0882     case NAND_CMD_STATUS:
0883         set_cmd_regs(mtd, command, command);
0884         set_addr(mtd, -1, -1);
0885 
0886         flctl->read_bytes = 1;
0887         writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
0888         start_translation(flctl);
0889         read_datareg(flctl, 0); /* read and end */
0890         break;
0891 
0892     case NAND_CMD_RESET:
0893         set_cmd_regs(mtd, command, command);
0894         set_addr(mtd, -1, -1);
0895 
0896         writel(0, FLDTCNTR(flctl)); /* set 0 size */
0897         start_translation(flctl);
0898         wait_completion(flctl);
0899         break;
0900 
0901     default:
0902         break;
0903     }
0904     goto runtime_exit;
0905 
0906 read_normal_exit:
0907     writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
0908     empty_fifo(flctl);
0909     start_translation(flctl);
0910     read_fiforeg(flctl, flctl->read_bytes, 0);
0911     wait_completion(flctl);
0912 runtime_exit:
0913     pm_runtime_put_sync(&flctl->pdev->dev);
0914     return;
0915 }
0916 
0917 static void flctl_select_chip(struct nand_chip *chip, int chipnr)
0918 {
0919     struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
0920     int ret;
0921 
0922     switch (chipnr) {
0923     case -1:
0924         flctl->flcmncr_base &= ~CE0_ENABLE;
0925 
0926         pm_runtime_get_sync(&flctl->pdev->dev);
0927         writel(flctl->flcmncr_base, FLCMNCR(flctl));
0928 
0929         if (flctl->qos_request) {
0930             dev_pm_qos_remove_request(&flctl->pm_qos);
0931             flctl->qos_request = 0;
0932         }
0933 
0934         pm_runtime_put_sync(&flctl->pdev->dev);
0935         break;
0936     case 0:
0937         flctl->flcmncr_base |= CE0_ENABLE;
0938 
0939         if (!flctl->qos_request) {
0940             ret = dev_pm_qos_add_request(&flctl->pdev->dev,
0941                             &flctl->pm_qos,
0942                             DEV_PM_QOS_RESUME_LATENCY,
0943                             100);
0944             if (ret < 0)
0945                 dev_err(&flctl->pdev->dev,
0946                     "PM QoS request failed: %d\n", ret);
0947             flctl->qos_request = 1;
0948         }
0949 
0950         if (flctl->holden) {
0951             pm_runtime_get_sync(&flctl->pdev->dev);
0952             writel(HOLDEN, FLHOLDCR(flctl));
0953             pm_runtime_put_sync(&flctl->pdev->dev);
0954         }
0955         break;
0956     default:
0957         BUG();
0958     }
0959 }
0960 
0961 static void flctl_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
0962 {
0963     struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
0964 
0965     memcpy(&flctl->done_buff[flctl->index], buf, len);
0966     flctl->index += len;
0967 }
0968 
0969 static uint8_t flctl_read_byte(struct nand_chip *chip)
0970 {
0971     struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
0972     uint8_t data;
0973 
0974     data = flctl->done_buff[flctl->index];
0975     flctl->index++;
0976     return data;
0977 }
0978 
0979 static void flctl_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0980 {
0981     struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
0982 
0983     memcpy(buf, &flctl->done_buff[flctl->index], len);
0984     flctl->index += len;
0985 }
0986 
0987 static int flctl_chip_attach_chip(struct nand_chip *chip)
0988 {
0989     u64 targetsize = nanddev_target_size(&chip->base);
0990     struct mtd_info *mtd = nand_to_mtd(chip);
0991     struct sh_flctl *flctl = mtd_to_flctl(mtd);
0992 
0993     /*
0994      * NAND_BUSWIDTH_16 may have been set by nand_scan_ident().
0995      * Add the SEL_16BIT flag in flctl->flcmncr_base.
0996      */
0997     if (chip->options & NAND_BUSWIDTH_16)
0998         flctl->flcmncr_base |= SEL_16BIT;
0999 
1000     if (mtd->writesize == 512) {
1001         flctl->page_size = 0;
1002         if (targetsize > (32 << 20)) {
1003             /* big than 32MB */
1004             flctl->rw_ADRCNT = ADRCNT_4;
1005             flctl->erase_ADRCNT = ADRCNT_3;
1006         } else if (targetsize > (2 << 16)) {
1007             /* big than 128KB */
1008             flctl->rw_ADRCNT = ADRCNT_3;
1009             flctl->erase_ADRCNT = ADRCNT_2;
1010         } else {
1011             flctl->rw_ADRCNT = ADRCNT_2;
1012             flctl->erase_ADRCNT = ADRCNT_1;
1013         }
1014     } else {
1015         flctl->page_size = 1;
1016         if (targetsize > (128 << 20)) {
1017             /* big than 128MB */
1018             flctl->rw_ADRCNT = ADRCNT2_E;
1019             flctl->erase_ADRCNT = ADRCNT_3;
1020         } else if (targetsize > (8 << 16)) {
1021             /* big than 512KB */
1022             flctl->rw_ADRCNT = ADRCNT_4;
1023             flctl->erase_ADRCNT = ADRCNT_2;
1024         } else {
1025             flctl->rw_ADRCNT = ADRCNT_3;
1026             flctl->erase_ADRCNT = ADRCNT_1;
1027         }
1028     }
1029 
1030     if (flctl->hwecc) {
1031         if (mtd->writesize == 512) {
1032             mtd_set_ooblayout(mtd, &flctl_4secc_oob_smallpage_ops);
1033             chip->badblock_pattern = &flctl_4secc_smallpage;
1034         } else {
1035             mtd_set_ooblayout(mtd, &flctl_4secc_oob_largepage_ops);
1036             chip->badblock_pattern = &flctl_4secc_largepage;
1037         }
1038 
1039         chip->ecc.size = 512;
1040         chip->ecc.bytes = 10;
1041         chip->ecc.strength = 4;
1042         chip->ecc.read_page = flctl_read_page_hwecc;
1043         chip->ecc.write_page = flctl_write_page_hwecc;
1044         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1045 
1046         /* 4 symbols ECC enabled */
1047         flctl->flcmncr_base |= _4ECCEN;
1048     } else {
1049         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
1050         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
1051     }
1052 
1053     return 0;
1054 }
1055 
1056 static const struct nand_controller_ops flctl_nand_controller_ops = {
1057     .attach_chip = flctl_chip_attach_chip,
1058 };
1059 
1060 static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
1061 {
1062     struct sh_flctl *flctl = dev_id;
1063 
1064     dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl)));
1065     writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
1066 
1067     return IRQ_HANDLED;
1068 }
1069 
1070 struct flctl_soc_config {
1071     unsigned long flcmncr_val;
1072     unsigned has_hwecc:1;
1073     unsigned use_holden:1;
1074 };
1075 
1076 static struct flctl_soc_config flctl_sh7372_config = {
1077     .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
1078     .has_hwecc = 1,
1079     .use_holden = 1,
1080 };
1081 
1082 static const struct of_device_id of_flctl_match[] = {
1083     { .compatible = "renesas,shmobile-flctl-sh7372",
1084                 .data = &flctl_sh7372_config },
1085     {},
1086 };
1087 MODULE_DEVICE_TABLE(of, of_flctl_match);
1088 
1089 static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
1090 {
1091     const struct flctl_soc_config *config;
1092     struct sh_flctl_platform_data *pdata;
1093 
1094     config = of_device_get_match_data(dev);
1095     if (!config) {
1096         dev_err(dev, "%s: no OF configuration attached\n", __func__);
1097         return NULL;
1098     }
1099 
1100     pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
1101                                 GFP_KERNEL);
1102     if (!pdata)
1103         return NULL;
1104 
1105     /* set SoC specific options */
1106     pdata->flcmncr_val = config->flcmncr_val;
1107     pdata->has_hwecc = config->has_hwecc;
1108     pdata->use_holden = config->use_holden;
1109 
1110     return pdata;
1111 }
1112 
1113 static int flctl_probe(struct platform_device *pdev)
1114 {
1115     struct resource *res;
1116     struct sh_flctl *flctl;
1117     struct mtd_info *flctl_mtd;
1118     struct nand_chip *nand;
1119     struct sh_flctl_platform_data *pdata;
1120     int ret;
1121     int irq;
1122 
1123     flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
1124     if (!flctl)
1125         return -ENOMEM;
1126 
1127     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1128     flctl->reg = devm_ioremap_resource(&pdev->dev, res);
1129     if (IS_ERR(flctl->reg))
1130         return PTR_ERR(flctl->reg);
1131     flctl->fifo = res->start + 0x24; /* FLDTFIFO */
1132 
1133     irq = platform_get_irq(pdev, 0);
1134     if (irq < 0)
1135         return irq;
1136 
1137     ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
1138                    "flste", flctl);
1139     if (ret) {
1140         dev_err(&pdev->dev, "request interrupt failed.\n");
1141         return ret;
1142     }
1143 
1144     if (pdev->dev.of_node)
1145         pdata = flctl_parse_dt(&pdev->dev);
1146     else
1147         pdata = dev_get_platdata(&pdev->dev);
1148 
1149     if (!pdata) {
1150         dev_err(&pdev->dev, "no setup data defined\n");
1151         return -EINVAL;
1152     }
1153 
1154     platform_set_drvdata(pdev, flctl);
1155     nand = &flctl->chip;
1156     flctl_mtd = nand_to_mtd(nand);
1157     nand_set_flash_node(nand, pdev->dev.of_node);
1158     flctl_mtd->dev.parent = &pdev->dev;
1159     flctl->pdev = pdev;
1160     flctl->hwecc = pdata->has_hwecc;
1161     flctl->holden = pdata->use_holden;
1162     flctl->flcmncr_base = pdata->flcmncr_val;
1163     flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
1164 
1165     /* Set address of hardware control function */
1166     /* 20 us command delay time */
1167     nand->legacy.chip_delay = 20;
1168 
1169     nand->legacy.read_byte = flctl_read_byte;
1170     nand->legacy.write_buf = flctl_write_buf;
1171     nand->legacy.read_buf = flctl_read_buf;
1172     nand->legacy.select_chip = flctl_select_chip;
1173     nand->legacy.cmdfunc = flctl_cmdfunc;
1174     nand->legacy.set_features = nand_get_set_features_notsupp;
1175     nand->legacy.get_features = nand_get_set_features_notsupp;
1176 
1177     if (pdata->flcmncr_val & SEL_16BIT)
1178         nand->options |= NAND_BUSWIDTH_16;
1179 
1180     nand->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
1181 
1182     pm_runtime_enable(&pdev->dev);
1183     pm_runtime_resume(&pdev->dev);
1184 
1185     flctl_setup_dma(flctl);
1186 
1187     nand->legacy.dummy_controller.ops = &flctl_nand_controller_ops;
1188     ret = nand_scan(nand, 1);
1189     if (ret)
1190         goto err_chip;
1191 
1192     ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
1193     if (ret)
1194         goto cleanup_nand;
1195 
1196     return 0;
1197 
1198 cleanup_nand:
1199     nand_cleanup(nand);
1200 err_chip:
1201     flctl_release_dma(flctl);
1202     pm_runtime_disable(&pdev->dev);
1203     return ret;
1204 }
1205 
1206 static int flctl_remove(struct platform_device *pdev)
1207 {
1208     struct sh_flctl *flctl = platform_get_drvdata(pdev);
1209     struct nand_chip *chip = &flctl->chip;
1210     int ret;
1211 
1212     flctl_release_dma(flctl);
1213     ret = mtd_device_unregister(nand_to_mtd(chip));
1214     WARN_ON(ret);
1215     nand_cleanup(chip);
1216     pm_runtime_disable(&pdev->dev);
1217 
1218     return 0;
1219 }
1220 
1221 static struct platform_driver flctl_driver = {
1222     .remove     = flctl_remove,
1223     .driver = {
1224         .name   = "sh_flctl",
1225         .of_match_table = of_flctl_match,
1226     },
1227 };
1228 
1229 module_platform_driver_probe(flctl_driver, flctl_probe);
1230 
1231 MODULE_LICENSE("GPL v2");
1232 MODULE_AUTHOR("Yoshihiro Shimoda");
1233 MODULE_DESCRIPTION("SuperH FLCTL driver");
1234 MODULE_ALIAS("platform:sh_flctl");
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