Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * Rockchip NAND Flash controller driver.
0004  * Copyright (C) 2020 Rockchip Inc.
0005  * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/module.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 
0022 /*
0023  * NFC Page Data Layout:
0024  *  1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
0025  *  1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
0026  *  ......
0027  * NAND Page Data Layout:
0028  *  1024 * n data + m Bytes oob
0029  * Original Bad Block Mask Location:
0030  *  First byte of oob(spare).
0031  * nand_chip->oob_poi data layout:
0032  *  4Bytes sys data + .... + 4Bytes sys data + ECC data.
0033  */
0034 
0035 /* NAND controller register definition */
0036 #define NFC_READ            (0)
0037 #define NFC_WRITE           (1)
0038 
0039 #define NFC_FMCTL           (0x00)
0040 #define   FMCTL_CE_SEL_M        0xFF
0041 #define   FMCTL_CE_SEL(x)       (1 << (x))
0042 #define   FMCTL_WP          BIT(8)
0043 #define   FMCTL_RDY         BIT(9)
0044 
0045 #define NFC_FMWAIT          (0x04)
0046 #define   FLCTL_RST         BIT(0)
0047 #define   FLCTL_WR          (1) /* 0: read, 1: write */
0048 #define   FLCTL_XFER_ST         BIT(2)
0049 #define   FLCTL_XFER_EN         BIT(3)
0050 #define   FLCTL_ACORRECT        BIT(10) /* Auto correct error bits. */
0051 #define   FLCTL_XFER_READY      BIT(20)
0052 #define   FLCTL_XFER_SECTOR     (22)
0053 #define   FLCTL_TOG_FIX         BIT(29)
0054 
0055 #define   BCHCTL_BANK_M         (7 << 5)
0056 #define   BCHCTL_BANK           (5)
0057 
0058 #define   DMA_ST            BIT(0)
0059 #define   DMA_WR            (1) /* 0: write, 1: read */
0060 #define   DMA_EN            BIT(2)
0061 #define   DMA_AHB_SIZE          (3) /* 0: 1, 1: 2, 2: 4 */
0062 #define   DMA_BURST_SIZE        (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */
0063 #define   DMA_INC_NUM           (9) /* 1 - 16 */
0064 
0065 #define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\
0066       (((x) >> (e).high) & (e).high_mask) << (e).low_bn)
0067 #define   INT_DMA           BIT(0)
0068 #define NFC_BANK            (0x800)
0069 #define NFC_BANK_STEP           (0x100)
0070 #define   BANK_DATA         (0x00)
0071 #define   BANK_ADDR         (0x04)
0072 #define   BANK_CMD          (0x08)
0073 #define NFC_SRAM0           (0x1000)
0074 #define NFC_SRAM1           (0x1400)
0075 #define NFC_SRAM_SIZE           (0x400)
0076 #define NFC_TIMEOUT         (500000)
0077 #define NFC_MAX_OOB_PER_STEP        128
0078 #define NFC_MIN_OOB_PER_STEP        64
0079 #define MAX_DATA_SIZE           0xFFFC
0080 #define MAX_ADDRESS_CYC         6
0081 #define NFC_ECC_MAX_MODES       4
0082 #define NFC_MAX_NSELS           (8) /* Some Socs only have 1 or 2 CSs. */
0083 #define NFC_SYS_DATA_SIZE       (4) /* 4 bytes sys data in oob pre 1024 data.*/
0084 #define RK_DEFAULT_CLOCK_RATE       (150 * 1000 * 1000) /* 150 Mhz */
0085 #define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs))
0086 
0087 enum nfc_type {
0088     NFC_V6,
0089     NFC_V8,
0090     NFC_V9,
0091 };
0092 
0093 /**
0094  * struct rk_ecc_cnt_status: represent a ecc status data.
0095  * @err_flag_bit: error flag bit index at register.
0096  * @low: ECC count low bit index at register.
0097  * @low_mask: mask bit.
0098  * @low_bn: ECC count low bit number.
0099  * @high: ECC count high bit index at register.
0100  * @high_mask: mask bit
0101  */
0102 struct ecc_cnt_status {
0103     u8 err_flag_bit;
0104     u8 low;
0105     u8 low_mask;
0106     u8 low_bn;
0107     u8 high;
0108     u8 high_mask;
0109 };
0110 
0111 /**
0112  * @type: NFC version
0113  * @ecc_strengths: ECC strengths
0114  * @ecc_cfgs: ECC config values
0115  * @flctl_off: FLCTL register offset
0116  * @bchctl_off: BCHCTL register offset
0117  * @dma_data_buf_off: DMA_DATA_BUF register offset
0118  * @dma_oob_buf_off: DMA_OOB_BUF register offset
0119  * @dma_cfg_off: DMA_CFG register offset
0120  * @dma_st_off: DMA_ST register offset
0121  * @bch_st_off: BCG_ST register offset
0122  * @randmz_off: RANDMZ register offset
0123  * @int_en_off: interrupt enable register offset
0124  * @int_clr_off: interrupt clean register offset
0125  * @int_st_off: interrupt status register offset
0126  * @oob0_off: oob0 register offset
0127  * @oob1_off: oob1 register offset
0128  * @ecc0: represent ECC0 status data
0129  * @ecc1: represent ECC1 status data
0130  */
0131 struct nfc_cfg {
0132     enum nfc_type type;
0133     u8 ecc_strengths[NFC_ECC_MAX_MODES];
0134     u32 ecc_cfgs[NFC_ECC_MAX_MODES];
0135     u32 flctl_off;
0136     u32 bchctl_off;
0137     u32 dma_cfg_off;
0138     u32 dma_data_buf_off;
0139     u32 dma_oob_buf_off;
0140     u32 dma_st_off;
0141     u32 bch_st_off;
0142     u32 randmz_off;
0143     u32 int_en_off;
0144     u32 int_clr_off;
0145     u32 int_st_off;
0146     u32 oob0_off;
0147     u32 oob1_off;
0148     struct ecc_cnt_status ecc0;
0149     struct ecc_cnt_status ecc1;
0150 };
0151 
0152 struct rk_nfc_nand_chip {
0153     struct list_head node;
0154     struct nand_chip chip;
0155 
0156     u16 boot_blks;
0157     u16 metadata_size;
0158     u32 boot_ecc;
0159     u32 timing;
0160 
0161     u8 nsels;
0162     u8 sels[];
0163     /* Nothing after this field. */
0164 };
0165 
0166 struct rk_nfc {
0167     struct nand_controller controller;
0168     const struct nfc_cfg *cfg;
0169     struct device *dev;
0170 
0171     struct clk *nfc_clk;
0172     struct clk *ahb_clk;
0173     void __iomem *regs;
0174 
0175     u32 selected_bank;
0176     u32 band_offset;
0177     u32 cur_ecc;
0178     u32 cur_timing;
0179 
0180     struct completion done;
0181     struct list_head chips;
0182 
0183     u8 *page_buf;
0184     u32 *oob_buf;
0185     u32 page_buf_size;
0186     u32 oob_buf_size;
0187 
0188     unsigned long assigned_cs;
0189 };
0190 
0191 static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip)
0192 {
0193     return container_of(chip, struct rk_nfc_nand_chip, chip);
0194 }
0195 
0196 static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i)
0197 {
0198     return (u8 *)p + i * chip->ecc.size;
0199 }
0200 
0201 static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i)
0202 {
0203     u8 *poi;
0204 
0205     poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE;
0206 
0207     return poi;
0208 }
0209 
0210 static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i)
0211 {
0212     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0213     u8 *poi;
0214 
0215     poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i;
0216 
0217     return poi;
0218 }
0219 
0220 static inline int rk_nfc_data_len(struct nand_chip *chip)
0221 {
0222     return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE;
0223 }
0224 
0225 static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i)
0226 {
0227     struct rk_nfc *nfc = nand_get_controller_data(chip);
0228 
0229     return nfc->page_buf + i * rk_nfc_data_len(chip);
0230 }
0231 
0232 static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i)
0233 {
0234     struct rk_nfc *nfc = nand_get_controller_data(chip);
0235 
0236     return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size;
0237 }
0238 
0239 static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength)
0240 {
0241     struct rk_nfc *nfc = nand_get_controller_data(chip);
0242     u32 reg, i;
0243 
0244     for (i = 0; i < NFC_ECC_MAX_MODES; i++) {
0245         if (strength == nfc->cfg->ecc_strengths[i]) {
0246             reg = nfc->cfg->ecc_cfgs[i];
0247             break;
0248         }
0249     }
0250 
0251     if (i >= NFC_ECC_MAX_MODES)
0252         return -EINVAL;
0253 
0254     writel(reg, nfc->regs + nfc->cfg->bchctl_off);
0255 
0256     /* Save chip ECC setting */
0257     nfc->cur_ecc = strength;
0258 
0259     return 0;
0260 }
0261 
0262 static void rk_nfc_select_chip(struct nand_chip *chip, int cs)
0263 {
0264     struct rk_nfc *nfc = nand_get_controller_data(chip);
0265     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0266     struct nand_ecc_ctrl *ecc = &chip->ecc;
0267     u32 val;
0268 
0269     if (cs < 0) {
0270         nfc->selected_bank = -1;
0271         /* Deselect the currently selected target. */
0272         val = readl_relaxed(nfc->regs + NFC_FMCTL);
0273         val &= ~FMCTL_CE_SEL_M;
0274         writel(val, nfc->regs + NFC_FMCTL);
0275         return;
0276     }
0277 
0278     nfc->selected_bank = rknand->sels[cs];
0279     nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP;
0280 
0281     val = readl_relaxed(nfc->regs + NFC_FMCTL);
0282     val &= ~FMCTL_CE_SEL_M;
0283     val |= FMCTL_CE_SEL(nfc->selected_bank);
0284 
0285     writel(val, nfc->regs + NFC_FMCTL);
0286 
0287     /*
0288      * Compare current chip timing with selected chip timing and
0289      * change if needed.
0290      */
0291     if (nfc->cur_timing != rknand->timing) {
0292         writel(rknand->timing, nfc->regs + NFC_FMWAIT);
0293         nfc->cur_timing = rknand->timing;
0294     }
0295 
0296     /*
0297      * Compare current chip ECC setting with selected chip ECC setting and
0298      * change if needed.
0299      */
0300     if (nfc->cur_ecc != ecc->strength)
0301         rk_nfc_hw_ecc_setup(chip, ecc->strength);
0302 }
0303 
0304 static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc)
0305 {
0306     int rc;
0307     u32 val;
0308 
0309     rc = readl_relaxed_poll_timeout(nfc->regs + NFC_FMCTL, val,
0310                     val & FMCTL_RDY, 10, NFC_TIMEOUT);
0311 
0312     return rc;
0313 }
0314 
0315 static void rk_nfc_read_buf(struct rk_nfc *nfc, u8 *buf, int len)
0316 {
0317     int i;
0318 
0319     for (i = 0; i < len; i++)
0320         buf[i] = readb_relaxed(nfc->regs + nfc->band_offset +
0321                        BANK_DATA);
0322 }
0323 
0324 static void rk_nfc_write_buf(struct rk_nfc *nfc, const u8 *buf, int len)
0325 {
0326     int i;
0327 
0328     for (i = 0; i < len; i++)
0329         writeb(buf[i], nfc->regs + nfc->band_offset + BANK_DATA);
0330 }
0331 
0332 static int rk_nfc_cmd(struct nand_chip *chip,
0333               const struct nand_subop *subop)
0334 {
0335     struct rk_nfc *nfc = nand_get_controller_data(chip);
0336     unsigned int i, j, remaining, start;
0337     int reg_offset = nfc->band_offset;
0338     u8 *inbuf = NULL;
0339     const u8 *outbuf;
0340     u32 cnt = 0;
0341     int ret = 0;
0342 
0343     for (i = 0; i < subop->ninstrs; i++) {
0344         const struct nand_op_instr *instr = &subop->instrs[i];
0345 
0346         switch (instr->type) {
0347         case NAND_OP_CMD_INSTR:
0348             writeb(instr->ctx.cmd.opcode,
0349                    nfc->regs + reg_offset + BANK_CMD);
0350             break;
0351 
0352         case NAND_OP_ADDR_INSTR:
0353             remaining = nand_subop_get_num_addr_cyc(subop, i);
0354             start = nand_subop_get_addr_start_off(subop, i);
0355 
0356             for (j = 0; j < 8 && j + start < remaining; j++)
0357                 writeb(instr->ctx.addr.addrs[j + start],
0358                        nfc->regs + reg_offset + BANK_ADDR);
0359             break;
0360 
0361         case NAND_OP_DATA_IN_INSTR:
0362         case NAND_OP_DATA_OUT_INSTR:
0363             start = nand_subop_get_data_start_off(subop, i);
0364             cnt = nand_subop_get_data_len(subop, i);
0365 
0366             if (instr->type == NAND_OP_DATA_OUT_INSTR) {
0367                 outbuf = instr->ctx.data.buf.out + start;
0368                 rk_nfc_write_buf(nfc, outbuf, cnt);
0369             } else {
0370                 inbuf = instr->ctx.data.buf.in + start;
0371                 rk_nfc_read_buf(nfc, inbuf, cnt);
0372             }
0373             break;
0374 
0375         case NAND_OP_WAITRDY_INSTR:
0376             if (rk_nfc_wait_ioready(nfc) < 0) {
0377                 ret = -ETIMEDOUT;
0378                 dev_err(nfc->dev, "IO not ready\n");
0379             }
0380             break;
0381         }
0382     }
0383 
0384     return ret;
0385 }
0386 
0387 static const struct nand_op_parser rk_nfc_op_parser = NAND_OP_PARSER(
0388     NAND_OP_PARSER_PATTERN(
0389         rk_nfc_cmd,
0390         NAND_OP_PARSER_PAT_CMD_ELEM(true),
0391         NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC),
0392         NAND_OP_PARSER_PAT_CMD_ELEM(true),
0393         NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
0394         NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)),
0395     NAND_OP_PARSER_PATTERN(
0396         rk_nfc_cmd,
0397         NAND_OP_PARSER_PAT_CMD_ELEM(true),
0398         NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC),
0399         NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, MAX_DATA_SIZE),
0400         NAND_OP_PARSER_PAT_CMD_ELEM(true),
0401         NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
0402 );
0403 
0404 static int rk_nfc_exec_op(struct nand_chip *chip,
0405               const struct nand_operation *op,
0406               bool check_only)
0407 {
0408     if (!check_only)
0409         rk_nfc_select_chip(chip, op->cs);
0410 
0411     return nand_op_parser_exec_op(chip, &rk_nfc_op_parser, op,
0412                       check_only);
0413 }
0414 
0415 static int rk_nfc_setup_interface(struct nand_chip *chip, int target,
0416                   const struct nand_interface_config *conf)
0417 {
0418     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0419     struct rk_nfc *nfc = nand_get_controller_data(chip);
0420     const struct nand_sdr_timings *timings;
0421     u32 rate, tc2rw, trwpw, trw2c;
0422     u32 temp;
0423 
0424     if (target < 0)
0425         return 0;
0426 
0427     timings = nand_get_sdr_timings(conf);
0428     if (IS_ERR(timings))
0429         return -EOPNOTSUPP;
0430 
0431     if (IS_ERR(nfc->nfc_clk))
0432         rate = clk_get_rate(nfc->ahb_clk);
0433     else
0434         rate = clk_get_rate(nfc->nfc_clk);
0435 
0436     /* Turn clock rate into kHz. */
0437     rate /= 1000;
0438 
0439     tc2rw = 1;
0440     trw2c = 1;
0441 
0442     trwpw = max(timings->tWC_min, timings->tRC_min) / 1000;
0443     trwpw = DIV_ROUND_UP(trwpw * rate, 1000000);
0444 
0445     temp = timings->tREA_max / 1000;
0446     temp = DIV_ROUND_UP(temp * rate, 1000000);
0447 
0448     if (trwpw < temp)
0449         trwpw = temp;
0450 
0451     /*
0452      * ACCON: access timing control register
0453      * -------------------------------------
0454      * 31:18: reserved
0455      * 17:12: csrw, clock cycles from the falling edge of CSn to the
0456      *   falling edge of RDn or WRn
0457      * 11:11: reserved
0458      * 10:05: rwpw, the width of RDn or WRn in processor clock cycles
0459      * 04:00: rwcs, clock cycles from the rising edge of RDn or WRn to the
0460      *   rising edge of CSn
0461      */
0462 
0463     /* Save chip timing */
0464     rknand->timing = ACCTIMING(tc2rw, trwpw, trw2c);
0465 
0466     return 0;
0467 }
0468 
0469 static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB,
0470                   dma_addr_t dma_data, dma_addr_t dma_oob)
0471 {
0472     u32 dma_reg, fl_reg, bch_reg;
0473 
0474     dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) |
0475           (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM);
0476 
0477     fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT |
0478          (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX;
0479 
0480     if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) {
0481         bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off);
0482         bch_reg = (bch_reg & (~BCHCTL_BANK_M)) |
0483               (nfc->selected_bank << BCHCTL_BANK);
0484         writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off);
0485     }
0486 
0487     writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
0488     writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off);
0489     writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off);
0490     writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
0491     fl_reg |= FLCTL_XFER_ST;
0492     writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
0493 }
0494 
0495 static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc)
0496 {
0497     void __iomem *ptr;
0498     u32 reg;
0499 
0500     ptr = nfc->regs + nfc->cfg->flctl_off;
0501 
0502     return readl_relaxed_poll_timeout(ptr, reg,
0503                      reg & FLCTL_XFER_READY,
0504                      10, NFC_TIMEOUT);
0505 }
0506 
0507 static int rk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf,
0508                  int oob_on, int page)
0509 {
0510     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0511     struct rk_nfc *nfc = nand_get_controller_data(chip);
0512     struct mtd_info *mtd = nand_to_mtd(chip);
0513     struct nand_ecc_ctrl *ecc = &chip->ecc;
0514     int i, pages_per_blk;
0515 
0516     pages_per_blk = mtd->erasesize / mtd->writesize;
0517     if ((chip->options & NAND_IS_BOOT_MEDIUM) &&
0518         (page < (pages_per_blk * rknand->boot_blks)) &&
0519         rknand->boot_ecc != ecc->strength) {
0520         /*
0521          * There's currently no method to notify the MTD framework that
0522          * a different ECC strength is in use for the boot blocks.
0523          */
0524         return -EIO;
0525     }
0526 
0527     if (!buf)
0528         memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize);
0529 
0530     for (i = 0; i < ecc->steps; i++) {
0531         /* Copy data to the NFC buffer. */
0532         if (buf)
0533             memcpy(rk_nfc_data_ptr(chip, i),
0534                    rk_nfc_buf_to_data_ptr(chip, buf, i),
0535                    ecc->size);
0536         /*
0537          * The first four bytes of OOB are reserved for the
0538          * boot ROM. In some debugging cases, such as with a
0539          * read, erase and write back test these 4 bytes stored
0540          * in OOB also need to be written back.
0541          *
0542          * The function nand_block_bad detects bad blocks like:
0543          *
0544          * bad = chip->oob_poi[chip->badblockpos];
0545          *
0546          * chip->badblockpos == 0 for a large page NAND Flash,
0547          * so chip->oob_poi[0] is the bad block mask (BBM).
0548          *
0549          * The OOB data layout on the NFC is:
0550          *
0551          *    PA0  PA1  PA2  PA3  | BBM OOB1 OOB2 OOB3 | ...
0552          *
0553          * or
0554          *
0555          *    0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
0556          *
0557          * The code here just swaps the first 4 bytes with the last
0558          * 4 bytes without losing any data.
0559          *
0560          * The chip->oob_poi data layout:
0561          *
0562          *    BBM  OOB1 OOB2 OOB3 |......|  PA0  PA1  PA2  PA3
0563          *
0564          * The rk_nfc_ooblayout_free() function already has reserved
0565          * these 4 bytes with:
0566          *
0567          * oob_region->offset = NFC_SYS_DATA_SIZE + 2;
0568          */
0569         if (!i)
0570             memcpy(rk_nfc_oob_ptr(chip, i),
0571                    rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
0572                    NFC_SYS_DATA_SIZE);
0573         else
0574             memcpy(rk_nfc_oob_ptr(chip, i),
0575                    rk_nfc_buf_to_oob_ptr(chip, i - 1),
0576                    NFC_SYS_DATA_SIZE);
0577         /* Copy ECC data to the NFC buffer. */
0578         memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
0579                rk_nfc_buf_to_oob_ecc_ptr(chip, i),
0580                ecc->bytes);
0581     }
0582 
0583     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0584     rk_nfc_write_buf(nfc, buf, mtd->writesize + mtd->oobsize);
0585     return nand_prog_page_end_op(chip);
0586 }
0587 
0588 static int rk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
0589                    int oob_on, int page)
0590 {
0591     struct mtd_info *mtd = nand_to_mtd(chip);
0592     struct rk_nfc *nfc = nand_get_controller_data(chip);
0593     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0594     struct nand_ecc_ctrl *ecc = &chip->ecc;
0595     int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
0596             NFC_MIN_OOB_PER_STEP;
0597     int pages_per_blk = mtd->erasesize / mtd->writesize;
0598     int ret = 0, i, boot_rom_mode = 0;
0599     dma_addr_t dma_data, dma_oob;
0600     u32 reg;
0601     u8 *oob;
0602 
0603     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0604 
0605     if (buf)
0606         memcpy(nfc->page_buf, buf, mtd->writesize);
0607     else
0608         memset(nfc->page_buf, 0xFF, mtd->writesize);
0609 
0610     /*
0611      * The first blocks (4, 8 or 16 depending on the device) are used
0612      * by the boot ROM and the first 32 bits of OOB need to link to
0613      * the next page address in the same block. We can't directly copy
0614      * OOB data from the MTD framework, because this page address
0615      * conflicts for example with the bad block marker (BBM),
0616      * so we shift all OOB data including the BBM with 4 byte positions.
0617      * As a consequence the OOB size available to the MTD framework is
0618      * also reduced with 4 bytes.
0619      *
0620      *    PA0  PA1  PA2  PA3 | BBM OOB1 OOB2 OOB3 | ...
0621      *
0622      * If a NAND is not a boot medium or the page is not a boot block,
0623      * the first 4 bytes are left untouched by writing 0xFF to them.
0624      *
0625      *   0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
0626      *
0627      * Configure the ECC algorithm supported by the boot ROM.
0628      */
0629     if ((page < (pages_per_blk * rknand->boot_blks)) &&
0630         (chip->options & NAND_IS_BOOT_MEDIUM)) {
0631         boot_rom_mode = 1;
0632         if (rknand->boot_ecc != ecc->strength)
0633             rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
0634     }
0635 
0636     for (i = 0; i < ecc->steps; i++) {
0637         if (!i) {
0638             reg = 0xFFFFFFFF;
0639         } else {
0640             oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
0641             reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
0642                   oob[3] << 24;
0643         }
0644 
0645         if (!i && boot_rom_mode)
0646             reg = (page & (pages_per_blk - 1)) * 4;
0647 
0648         if (nfc->cfg->type == NFC_V9)
0649             nfc->oob_buf[i] = reg;
0650         else
0651             nfc->oob_buf[i * (oob_step / 4)] = reg;
0652     }
0653 
0654     dma_data = dma_map_single(nfc->dev, (void *)nfc->page_buf,
0655                   mtd->writesize, DMA_TO_DEVICE);
0656     dma_oob = dma_map_single(nfc->dev, nfc->oob_buf,
0657                  ecc->steps * oob_step,
0658                  DMA_TO_DEVICE);
0659 
0660     reinit_completion(&nfc->done);
0661     writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off);
0662 
0663     rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data,
0664               dma_oob);
0665     ret = wait_for_completion_timeout(&nfc->done,
0666                       msecs_to_jiffies(100));
0667     if (!ret)
0668         dev_warn(nfc->dev, "write: wait dma done timeout.\n");
0669     /*
0670      * Whether the DMA transfer is completed or not. The driver
0671      * needs to check the NFC`s status register to see if the data
0672      * transfer was completed.
0673      */
0674     ret = rk_nfc_wait_for_xfer_done(nfc);
0675 
0676     dma_unmap_single(nfc->dev, dma_data, mtd->writesize,
0677              DMA_TO_DEVICE);
0678     dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step,
0679              DMA_TO_DEVICE);
0680 
0681     if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
0682         rk_nfc_hw_ecc_setup(chip, ecc->strength);
0683 
0684     if (ret) {
0685         dev_err(nfc->dev, "write: wait transfer done timeout.\n");
0686         return -ETIMEDOUT;
0687     }
0688 
0689     return nand_prog_page_end_op(chip);
0690 }
0691 
0692 static int rk_nfc_write_oob(struct nand_chip *chip, int page)
0693 {
0694     return rk_nfc_write_page_hwecc(chip, NULL, 1, page);
0695 }
0696 
0697 static int rk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on,
0698                 int page)
0699 {
0700     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0701     struct rk_nfc *nfc = nand_get_controller_data(chip);
0702     struct mtd_info *mtd = nand_to_mtd(chip);
0703     struct nand_ecc_ctrl *ecc = &chip->ecc;
0704     int i, pages_per_blk;
0705 
0706     pages_per_blk = mtd->erasesize / mtd->writesize;
0707     if ((chip->options & NAND_IS_BOOT_MEDIUM) &&
0708         (page < (pages_per_blk * rknand->boot_blks)) &&
0709         rknand->boot_ecc != ecc->strength) {
0710         /*
0711          * There's currently no method to notify the MTD framework that
0712          * a different ECC strength is in use for the boot blocks.
0713          */
0714         return -EIO;
0715     }
0716 
0717     nand_read_page_op(chip, page, 0, NULL, 0);
0718     rk_nfc_read_buf(nfc, nfc->page_buf, mtd->writesize + mtd->oobsize);
0719     for (i = 0; i < ecc->steps; i++) {
0720         /*
0721          * The first four bytes of OOB are reserved for the
0722          * boot ROM. In some debugging cases, such as with a read,
0723          * erase and write back test, these 4 bytes also must be
0724          * saved somewhere, otherwise this information will be
0725          * lost during a write back.
0726          */
0727         if (!i)
0728             memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
0729                    rk_nfc_oob_ptr(chip, i),
0730                    NFC_SYS_DATA_SIZE);
0731         else
0732             memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1),
0733                    rk_nfc_oob_ptr(chip, i),
0734                    NFC_SYS_DATA_SIZE);
0735 
0736         /* Copy ECC data from the NFC buffer. */
0737         memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i),
0738                rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
0739                ecc->bytes);
0740 
0741         /* Copy data from the NFC buffer. */
0742         if (buf)
0743             memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i),
0744                    rk_nfc_data_ptr(chip, i),
0745                    ecc->size);
0746     }
0747 
0748     return 0;
0749 }
0750 
0751 static int rk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *buf, int oob_on,
0752                   int page)
0753 {
0754     struct mtd_info *mtd = nand_to_mtd(chip);
0755     struct rk_nfc *nfc = nand_get_controller_data(chip);
0756     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0757     struct nand_ecc_ctrl *ecc = &chip->ecc;
0758     int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
0759             NFC_MIN_OOB_PER_STEP;
0760     int pages_per_blk = mtd->erasesize / mtd->writesize;
0761     dma_addr_t dma_data, dma_oob;
0762     int ret = 0, i, cnt, boot_rom_mode = 0;
0763     int max_bitflips = 0, bch_st, ecc_fail = 0;
0764     u8 *oob;
0765     u32 tmp;
0766 
0767     nand_read_page_op(chip, page, 0, NULL, 0);
0768 
0769     dma_data = dma_map_single(nfc->dev, nfc->page_buf,
0770                   mtd->writesize,
0771                   DMA_FROM_DEVICE);
0772     dma_oob = dma_map_single(nfc->dev, nfc->oob_buf,
0773                  ecc->steps * oob_step,
0774                  DMA_FROM_DEVICE);
0775 
0776     /*
0777      * The first blocks (4, 8 or 16 depending on the device)
0778      * are used by the boot ROM.
0779      * Configure the ECC algorithm supported by the boot ROM.
0780      */
0781     if ((page < (pages_per_blk * rknand->boot_blks)) &&
0782         (chip->options & NAND_IS_BOOT_MEDIUM)) {
0783         boot_rom_mode = 1;
0784         if (rknand->boot_ecc != ecc->strength)
0785             rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
0786     }
0787 
0788     reinit_completion(&nfc->done);
0789     writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off);
0790     rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data,
0791               dma_oob);
0792     ret = wait_for_completion_timeout(&nfc->done,
0793                       msecs_to_jiffies(100));
0794     if (!ret)
0795         dev_warn(nfc->dev, "read: wait dma done timeout.\n");
0796     /*
0797      * Whether the DMA transfer is completed or not. The driver
0798      * needs to check the NFC`s status register to see if the data
0799      * transfer was completed.
0800      */
0801     ret = rk_nfc_wait_for_xfer_done(nfc);
0802 
0803     dma_unmap_single(nfc->dev, dma_data, mtd->writesize,
0804              DMA_FROM_DEVICE);
0805     dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step,
0806              DMA_FROM_DEVICE);
0807 
0808     if (ret) {
0809         ret = -ETIMEDOUT;
0810         dev_err(nfc->dev, "read: wait transfer done timeout.\n");
0811         goto timeout_err;
0812     }
0813 
0814     for (i = 1; i < ecc->steps; i++) {
0815         oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
0816         if (nfc->cfg->type == NFC_V9)
0817             tmp = nfc->oob_buf[i];
0818         else
0819             tmp = nfc->oob_buf[i * (oob_step / 4)];
0820         *oob++ = (u8)tmp;
0821         *oob++ = (u8)(tmp >> 8);
0822         *oob++ = (u8)(tmp >> 16);
0823         *oob++ = (u8)(tmp >> 24);
0824     }
0825 
0826     for (i = 0; i < (ecc->steps / 2); i++) {
0827         bch_st = readl_relaxed(nfc->regs +
0828                        nfc->cfg->bch_st_off + i * 4);
0829         if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) ||
0830             bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) {
0831             mtd->ecc_stats.failed++;
0832             ecc_fail = 1;
0833         } else {
0834             cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0);
0835             mtd->ecc_stats.corrected += cnt;
0836             max_bitflips = max_t(u32, max_bitflips, cnt);
0837 
0838             cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1);
0839             mtd->ecc_stats.corrected += cnt;
0840             max_bitflips = max_t(u32, max_bitflips, cnt);
0841         }
0842     }
0843 
0844     if (buf)
0845         memcpy(buf, nfc->page_buf, mtd->writesize);
0846 
0847 timeout_err:
0848     if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
0849         rk_nfc_hw_ecc_setup(chip, ecc->strength);
0850 
0851     if (ret)
0852         return ret;
0853 
0854     if (ecc_fail) {
0855         dev_err(nfc->dev, "read page: %x ecc error!\n", page);
0856         return 0;
0857     }
0858 
0859     return max_bitflips;
0860 }
0861 
0862 static int rk_nfc_read_oob(struct nand_chip *chip, int page)
0863 {
0864     return rk_nfc_read_page_hwecc(chip, NULL, 1, page);
0865 }
0866 
0867 static inline void rk_nfc_hw_init(struct rk_nfc *nfc)
0868 {
0869     /* Disable flash wp. */
0870     writel(FMCTL_WP, nfc->regs + NFC_FMCTL);
0871     /* Config default timing 40ns at 150 Mhz NFC clock. */
0872     writel(0x1081, nfc->regs + NFC_FMWAIT);
0873     nfc->cur_timing = 0x1081;
0874     /* Disable randomizer and DMA. */
0875     writel(0, nfc->regs + nfc->cfg->randmz_off);
0876     writel(0, nfc->regs + nfc->cfg->dma_cfg_off);
0877     writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off);
0878 }
0879 
0880 static irqreturn_t rk_nfc_irq(int irq, void *id)
0881 {
0882     struct rk_nfc *nfc = id;
0883     u32 sta, ien;
0884 
0885     sta = readl_relaxed(nfc->regs + nfc->cfg->int_st_off);
0886     ien = readl_relaxed(nfc->regs + nfc->cfg->int_en_off);
0887 
0888     if (!(sta & ien))
0889         return IRQ_NONE;
0890 
0891     writel(sta, nfc->regs + nfc->cfg->int_clr_off);
0892     writel(~sta & ien, nfc->regs + nfc->cfg->int_en_off);
0893 
0894     complete(&nfc->done);
0895 
0896     return IRQ_HANDLED;
0897 }
0898 
0899 static int rk_nfc_enable_clks(struct device *dev, struct rk_nfc *nfc)
0900 {
0901     int ret;
0902 
0903     if (!IS_ERR(nfc->nfc_clk)) {
0904         ret = clk_prepare_enable(nfc->nfc_clk);
0905         if (ret) {
0906             dev_err(dev, "failed to enable NFC clk\n");
0907             return ret;
0908         }
0909     }
0910 
0911     ret = clk_prepare_enable(nfc->ahb_clk);
0912     if (ret) {
0913         dev_err(dev, "failed to enable ahb clk\n");
0914         clk_disable_unprepare(nfc->nfc_clk);
0915         return ret;
0916     }
0917 
0918     return 0;
0919 }
0920 
0921 static void rk_nfc_disable_clks(struct rk_nfc *nfc)
0922 {
0923     clk_disable_unprepare(nfc->nfc_clk);
0924     clk_disable_unprepare(nfc->ahb_clk);
0925 }
0926 
0927 static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
0928                  struct mtd_oob_region *oob_region)
0929 {
0930     struct nand_chip *chip = mtd_to_nand(mtd);
0931     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0932 
0933     if (section)
0934         return -ERANGE;
0935 
0936     /*
0937      * The beginning of the OOB area stores the reserved data for the NFC,
0938      * the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
0939      */
0940     oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
0941     oob_region->offset = NFC_SYS_DATA_SIZE + 2;
0942 
0943     return 0;
0944 }
0945 
0946 static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
0947                 struct mtd_oob_region *oob_region)
0948 {
0949     struct nand_chip *chip = mtd_to_nand(mtd);
0950     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
0951 
0952     if (section)
0953         return -ERANGE;
0954 
0955     oob_region->length = mtd->oobsize - rknand->metadata_size;
0956     oob_region->offset = rknand->metadata_size;
0957 
0958     return 0;
0959 }
0960 
0961 static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
0962     .free = rk_nfc_ooblayout_free,
0963     .ecc = rk_nfc_ooblayout_ecc,
0964 };
0965 
0966 static int rk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
0967 {
0968     struct nand_chip *chip = mtd_to_nand(mtd);
0969     struct rk_nfc *nfc = nand_get_controller_data(chip);
0970     struct nand_ecc_ctrl *ecc = &chip->ecc;
0971     const u8 *strengths = nfc->cfg->ecc_strengths;
0972     u8 max_strength, nfc_max_strength;
0973     int i;
0974 
0975     nfc_max_strength = nfc->cfg->ecc_strengths[0];
0976     /* If optional dt settings not present. */
0977     if (!ecc->size || !ecc->strength ||
0978         ecc->strength > nfc_max_strength) {
0979         chip->ecc.size = 1024;
0980         ecc->steps = mtd->writesize / ecc->size;
0981 
0982         /*
0983          * HW ECC always requests the number of ECC bytes per 1024 byte
0984          * blocks. The first 4 OOB bytes are reserved for sys data.
0985          */
0986         max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 /
0987                  fls(8 * 1024);
0988         if (max_strength > nfc_max_strength)
0989             max_strength = nfc_max_strength;
0990 
0991         for (i = 0; i < 4; i++) {
0992             if (max_strength >= strengths[i])
0993                 break;
0994         }
0995 
0996         if (i >= 4) {
0997             dev_err(nfc->dev, "unsupported ECC strength\n");
0998             return -EOPNOTSUPP;
0999         }
1000 
1001         ecc->strength = strengths[i];
1002     }
1003     ecc->steps = mtd->writesize / ecc->size;
1004     ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
1005 
1006     return 0;
1007 }
1008 
1009 static int rk_nfc_attach_chip(struct nand_chip *chip)
1010 {
1011     struct mtd_info *mtd = nand_to_mtd(chip);
1012     struct device *dev = mtd->dev.parent;
1013     struct rk_nfc *nfc = nand_get_controller_data(chip);
1014     struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
1015     struct nand_ecc_ctrl *ecc = &chip->ecc;
1016     int new_page_len, new_oob_len;
1017     void *buf;
1018     int ret;
1019 
1020     if (chip->options & NAND_BUSWIDTH_16) {
1021         dev_err(dev, "16 bits bus width not supported");
1022         return -EINVAL;
1023     }
1024 
1025     if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1026         return 0;
1027 
1028     ret = rk_nfc_ecc_init(dev, mtd);
1029     if (ret)
1030         return ret;
1031 
1032     rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps;
1033 
1034     if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) {
1035         dev_err(dev,
1036             "driver needs at least %d bytes of meta data\n",
1037             NFC_SYS_DATA_SIZE + 2);
1038         return -EIO;
1039     }
1040 
1041     /* Check buffer first, avoid duplicate alloc buffer. */
1042     new_page_len = mtd->writesize + mtd->oobsize;
1043     if (nfc->page_buf && new_page_len > nfc->page_buf_size) {
1044         buf = krealloc(nfc->page_buf, new_page_len,
1045                    GFP_KERNEL | GFP_DMA);
1046         if (!buf)
1047             return -ENOMEM;
1048         nfc->page_buf = buf;
1049         nfc->page_buf_size = new_page_len;
1050     }
1051 
1052     new_oob_len = ecc->steps * NFC_MAX_OOB_PER_STEP;
1053     if (nfc->oob_buf && new_oob_len > nfc->oob_buf_size) {
1054         buf = krealloc(nfc->oob_buf, new_oob_len,
1055                    GFP_KERNEL | GFP_DMA);
1056         if (!buf) {
1057             kfree(nfc->page_buf);
1058             nfc->page_buf = NULL;
1059             return -ENOMEM;
1060         }
1061         nfc->oob_buf = buf;
1062         nfc->oob_buf_size = new_oob_len;
1063     }
1064 
1065     if (!nfc->page_buf) {
1066         nfc->page_buf = kzalloc(new_page_len, GFP_KERNEL | GFP_DMA);
1067         if (!nfc->page_buf)
1068             return -ENOMEM;
1069         nfc->page_buf_size = new_page_len;
1070     }
1071 
1072     if (!nfc->oob_buf) {
1073         nfc->oob_buf = kzalloc(new_oob_len, GFP_KERNEL | GFP_DMA);
1074         if (!nfc->oob_buf) {
1075             kfree(nfc->page_buf);
1076             nfc->page_buf = NULL;
1077             return -ENOMEM;
1078         }
1079         nfc->oob_buf_size = new_oob_len;
1080     }
1081 
1082     chip->ecc.write_page_raw = rk_nfc_write_page_raw;
1083     chip->ecc.write_page = rk_nfc_write_page_hwecc;
1084     chip->ecc.write_oob = rk_nfc_write_oob;
1085 
1086     chip->ecc.read_page_raw = rk_nfc_read_page_raw;
1087     chip->ecc.read_page = rk_nfc_read_page_hwecc;
1088     chip->ecc.read_oob = rk_nfc_read_oob;
1089 
1090     return 0;
1091 }
1092 
1093 static const struct nand_controller_ops rk_nfc_controller_ops = {
1094     .attach_chip = rk_nfc_attach_chip,
1095     .exec_op = rk_nfc_exec_op,
1096     .setup_interface = rk_nfc_setup_interface,
1097 };
1098 
1099 static int rk_nfc_nand_chip_init(struct device *dev, struct rk_nfc *nfc,
1100                  struct device_node *np)
1101 {
1102     struct rk_nfc_nand_chip *rknand;
1103     struct nand_chip *chip;
1104     struct mtd_info *mtd;
1105     int nsels;
1106     u32 tmp;
1107     int ret;
1108     int i;
1109 
1110     if (!of_get_property(np, "reg", &nsels))
1111         return -ENODEV;
1112     nsels /= sizeof(u32);
1113     if (!nsels || nsels > NFC_MAX_NSELS) {
1114         dev_err(dev, "invalid reg property size %d\n", nsels);
1115         return -EINVAL;
1116     }
1117 
1118     rknand = devm_kzalloc(dev, sizeof(*rknand) + nsels * sizeof(u8),
1119                   GFP_KERNEL);
1120     if (!rknand)
1121         return -ENOMEM;
1122 
1123     rknand->nsels = nsels;
1124     for (i = 0; i < nsels; i++) {
1125         ret = of_property_read_u32_index(np, "reg", i, &tmp);
1126         if (ret) {
1127             dev_err(dev, "reg property failure : %d\n", ret);
1128             return ret;
1129         }
1130 
1131         if (tmp >= NFC_MAX_NSELS) {
1132             dev_err(dev, "invalid CS: %u\n", tmp);
1133             return -EINVAL;
1134         }
1135 
1136         if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1137             dev_err(dev, "CS %u already assigned\n", tmp);
1138             return -EINVAL;
1139         }
1140 
1141         rknand->sels[i] = tmp;
1142     }
1143 
1144     chip = &rknand->chip;
1145     chip->controller = &nfc->controller;
1146 
1147     nand_set_flash_node(chip, np);
1148 
1149     nand_set_controller_data(chip, nfc);
1150 
1151     chip->options |= NAND_USES_DMA | NAND_NO_SUBPAGE_WRITE;
1152     chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1153 
1154     /* Set default mode in case dt entry is missing. */
1155     chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1156 
1157     mtd = nand_to_mtd(chip);
1158     mtd->owner = THIS_MODULE;
1159     mtd->dev.parent = dev;
1160 
1161     if (!mtd->name) {
1162         dev_err(nfc->dev, "NAND label property is mandatory\n");
1163         return -EINVAL;
1164     }
1165 
1166     mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops);
1167     rk_nfc_hw_init(nfc);
1168     ret = nand_scan(chip, nsels);
1169     if (ret)
1170         return ret;
1171 
1172     if (chip->options & NAND_IS_BOOT_MEDIUM) {
1173         ret = of_property_read_u32(np, "rockchip,boot-blks", &tmp);
1174         rknand->boot_blks = ret ? 0 : tmp;
1175 
1176         ret = of_property_read_u32(np, "rockchip,boot-ecc-strength",
1177                        &tmp);
1178         rknand->boot_ecc = ret ? chip->ecc.strength : tmp;
1179     }
1180 
1181     ret = mtd_device_register(mtd, NULL, 0);
1182     if (ret) {
1183         dev_err(dev, "MTD parse partition error\n");
1184         nand_cleanup(chip);
1185         return ret;
1186     }
1187 
1188     list_add_tail(&rknand->node, &nfc->chips);
1189 
1190     return 0;
1191 }
1192 
1193 static void rk_nfc_chips_cleanup(struct rk_nfc *nfc)
1194 {
1195     struct rk_nfc_nand_chip *rknand, *tmp;
1196     struct nand_chip *chip;
1197     int ret;
1198 
1199     list_for_each_entry_safe(rknand, tmp, &nfc->chips, node) {
1200         chip = &rknand->chip;
1201         ret = mtd_device_unregister(nand_to_mtd(chip));
1202         WARN_ON(ret);
1203         nand_cleanup(chip);
1204         list_del(&rknand->node);
1205     }
1206 }
1207 
1208 static int rk_nfc_nand_chips_init(struct device *dev, struct rk_nfc *nfc)
1209 {
1210     struct device_node *np = dev->of_node, *nand_np;
1211     int nchips = of_get_child_count(np);
1212     int ret;
1213 
1214     if (!nchips || nchips > NFC_MAX_NSELS) {
1215         dev_err(nfc->dev, "incorrect number of NAND chips (%d)\n",
1216             nchips);
1217         return -EINVAL;
1218     }
1219 
1220     for_each_child_of_node(np, nand_np) {
1221         ret = rk_nfc_nand_chip_init(dev, nfc, nand_np);
1222         if (ret) {
1223             of_node_put(nand_np);
1224             rk_nfc_chips_cleanup(nfc);
1225             return ret;
1226         }
1227     }
1228 
1229     return 0;
1230 }
1231 
1232 static struct nfc_cfg nfc_v6_cfg = {
1233         .type           = NFC_V6,
1234         .ecc_strengths      = {60, 40, 24, 16},
1235         .ecc_cfgs       = {
1236             0x00040011, 0x00040001, 0x00000011, 0x00000001,
1237         },
1238         .flctl_off      = 0x08,
1239         .bchctl_off     = 0x0C,
1240         .dma_cfg_off        = 0x10,
1241         .dma_data_buf_off   = 0x14,
1242         .dma_oob_buf_off    = 0x18,
1243         .dma_st_off     = 0x1C,
1244         .bch_st_off     = 0x20,
1245         .randmz_off     = 0x150,
1246         .int_en_off     = 0x16C,
1247         .int_clr_off        = 0x170,
1248         .int_st_off     = 0x174,
1249         .oob0_off       = 0x200,
1250         .oob1_off       = 0x230,
1251         .ecc0           = {
1252             .err_flag_bit   = 2,
1253             .low        = 3,
1254             .low_mask   = 0x1F,
1255             .low_bn     = 5,
1256             .high       = 27,
1257             .high_mask  = 0x1,
1258         },
1259         .ecc1           = {
1260             .err_flag_bit   = 15,
1261             .low        = 16,
1262             .low_mask   = 0x1F,
1263             .low_bn     = 5,
1264             .high       = 29,
1265             .high_mask  = 0x1,
1266         },
1267 };
1268 
1269 static struct nfc_cfg nfc_v8_cfg = {
1270         .type           = NFC_V8,
1271         .ecc_strengths      = {16, 16, 16, 16},
1272         .ecc_cfgs       = {
1273             0x00000001, 0x00000001, 0x00000001, 0x00000001,
1274         },
1275         .flctl_off      = 0x08,
1276         .bchctl_off     = 0x0C,
1277         .dma_cfg_off        = 0x10,
1278         .dma_data_buf_off   = 0x14,
1279         .dma_oob_buf_off    = 0x18,
1280         .dma_st_off     = 0x1C,
1281         .bch_st_off     = 0x20,
1282         .randmz_off     = 0x150,
1283         .int_en_off     = 0x16C,
1284         .int_clr_off        = 0x170,
1285         .int_st_off     = 0x174,
1286         .oob0_off       = 0x200,
1287         .oob1_off       = 0x230,
1288         .ecc0           = {
1289             .err_flag_bit   = 2,
1290             .low        = 3,
1291             .low_mask   = 0x1F,
1292             .low_bn     = 5,
1293             .high       = 27,
1294             .high_mask  = 0x1,
1295         },
1296         .ecc1           = {
1297             .err_flag_bit   = 15,
1298             .low        = 16,
1299             .low_mask   = 0x1F,
1300             .low_bn     = 5,
1301             .high       = 29,
1302             .high_mask  = 0x1,
1303         },
1304 };
1305 
1306 static struct nfc_cfg nfc_v9_cfg = {
1307         .type           = NFC_V9,
1308         .ecc_strengths      = {70, 60, 40, 16},
1309         .ecc_cfgs       = {
1310             0x00000001, 0x06000001, 0x04000001, 0x02000001,
1311         },
1312         .flctl_off      = 0x10,
1313         .bchctl_off     = 0x20,
1314         .dma_cfg_off        = 0x30,
1315         .dma_data_buf_off   = 0x34,
1316         .dma_oob_buf_off    = 0x38,
1317         .dma_st_off     = 0x3C,
1318         .bch_st_off     = 0x150,
1319         .randmz_off     = 0x208,
1320         .int_en_off     = 0x120,
1321         .int_clr_off        = 0x124,
1322         .int_st_off     = 0x128,
1323         .oob0_off       = 0x200,
1324         .oob1_off       = 0x204,
1325         .ecc0           = {
1326             .err_flag_bit   = 2,
1327             .low        = 3,
1328             .low_mask   = 0x7F,
1329             .low_bn     = 7,
1330             .high       = 0,
1331             .high_mask  = 0x0,
1332         },
1333         .ecc1           = {
1334             .err_flag_bit   = 18,
1335             .low        = 19,
1336             .low_mask   = 0x7F,
1337             .low_bn     = 7,
1338             .high       = 0,
1339             .high_mask  = 0x0,
1340         },
1341 };
1342 
1343 static const struct of_device_id rk_nfc_id_table[] = {
1344     {
1345         .compatible = "rockchip,px30-nfc",
1346         .data = &nfc_v9_cfg
1347     },
1348     {
1349         .compatible = "rockchip,rk2928-nfc",
1350         .data = &nfc_v6_cfg
1351     },
1352     {
1353         .compatible = "rockchip,rv1108-nfc",
1354         .data = &nfc_v8_cfg
1355     },
1356     { /* sentinel */ }
1357 };
1358 MODULE_DEVICE_TABLE(of, rk_nfc_id_table);
1359 
1360 static int rk_nfc_probe(struct platform_device *pdev)
1361 {
1362     struct device *dev = &pdev->dev;
1363     struct rk_nfc *nfc;
1364     int ret, irq;
1365 
1366     nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1367     if (!nfc)
1368         return -ENOMEM;
1369 
1370     nand_controller_init(&nfc->controller);
1371     INIT_LIST_HEAD(&nfc->chips);
1372     nfc->controller.ops = &rk_nfc_controller_ops;
1373 
1374     nfc->cfg = of_device_get_match_data(dev);
1375     nfc->dev = dev;
1376 
1377     init_completion(&nfc->done);
1378 
1379     nfc->regs = devm_platform_ioremap_resource(pdev, 0);
1380     if (IS_ERR(nfc->regs)) {
1381         ret = PTR_ERR(nfc->regs);
1382         goto release_nfc;
1383     }
1384 
1385     nfc->nfc_clk = devm_clk_get(dev, "nfc");
1386     if (IS_ERR(nfc->nfc_clk)) {
1387         dev_dbg(dev, "no NFC clk\n");
1388         /* Some earlier models, such as rk3066, have no NFC clk. */
1389     }
1390 
1391     nfc->ahb_clk = devm_clk_get(dev, "ahb");
1392     if (IS_ERR(nfc->ahb_clk)) {
1393         dev_err(dev, "no ahb clk\n");
1394         ret = PTR_ERR(nfc->ahb_clk);
1395         goto release_nfc;
1396     }
1397 
1398     ret = rk_nfc_enable_clks(dev, nfc);
1399     if (ret)
1400         goto release_nfc;
1401 
1402     irq = platform_get_irq(pdev, 0);
1403     if (irq < 0) {
1404         ret = -EINVAL;
1405         goto clk_disable;
1406     }
1407 
1408     writel(0, nfc->regs + nfc->cfg->int_en_off);
1409     ret = devm_request_irq(dev, irq, rk_nfc_irq, 0x0, "rk-nand", nfc);
1410     if (ret) {
1411         dev_err(dev, "failed to request NFC irq\n");
1412         goto clk_disable;
1413     }
1414 
1415     platform_set_drvdata(pdev, nfc);
1416 
1417     ret = rk_nfc_nand_chips_init(dev, nfc);
1418     if (ret) {
1419         dev_err(dev, "failed to init NAND chips\n");
1420         goto clk_disable;
1421     }
1422     return 0;
1423 
1424 clk_disable:
1425     rk_nfc_disable_clks(nfc);
1426 release_nfc:
1427     return ret;
1428 }
1429 
1430 static int rk_nfc_remove(struct platform_device *pdev)
1431 {
1432     struct rk_nfc *nfc = platform_get_drvdata(pdev);
1433 
1434     kfree(nfc->page_buf);
1435     kfree(nfc->oob_buf);
1436     rk_nfc_chips_cleanup(nfc);
1437     rk_nfc_disable_clks(nfc);
1438 
1439     return 0;
1440 }
1441 
1442 static int __maybe_unused rk_nfc_suspend(struct device *dev)
1443 {
1444     struct rk_nfc *nfc = dev_get_drvdata(dev);
1445 
1446     rk_nfc_disable_clks(nfc);
1447 
1448     return 0;
1449 }
1450 
1451 static int __maybe_unused rk_nfc_resume(struct device *dev)
1452 {
1453     struct rk_nfc *nfc = dev_get_drvdata(dev);
1454     struct rk_nfc_nand_chip *rknand;
1455     struct nand_chip *chip;
1456     int ret;
1457     u32 i;
1458 
1459     ret = rk_nfc_enable_clks(dev, nfc);
1460     if (ret)
1461         return ret;
1462 
1463     /* Reset NAND chip if VCC was powered off. */
1464     list_for_each_entry(rknand, &nfc->chips, node) {
1465         chip = &rknand->chip;
1466         for (i = 0; i < rknand->nsels; i++)
1467             nand_reset(chip, i);
1468     }
1469 
1470     return 0;
1471 }
1472 
1473 static const struct dev_pm_ops rk_nfc_pm_ops = {
1474     SET_SYSTEM_SLEEP_PM_OPS(rk_nfc_suspend, rk_nfc_resume)
1475 };
1476 
1477 static struct platform_driver rk_nfc_driver = {
1478     .probe = rk_nfc_probe,
1479     .remove = rk_nfc_remove,
1480     .driver = {
1481         .name = "rockchip-nfc",
1482         .of_match_table = rk_nfc_id_table,
1483         .pm = &rk_nfc_pm_ops,
1484     },
1485 };
1486 
1487 module_platform_driver(rk_nfc_driver);
1488 
1489 MODULE_LICENSE("Dual MIT/GPL");
1490 MODULE_AUTHOR("Yifeng Zhao <yifeng.zhao@rock-chips.com>");
1491 MODULE_DESCRIPTION("Rockchip Nand Flash Controller Driver");
1492 MODULE_ALIAS("platform:rockchip-nand-controller");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!