nand/raw/r852.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright © 2009 - Maxim Levitsky
0004  * driver for Ricoh xD readers
0005  */
0006
0007 #include <linux/pci.h>
0008 #include <linux/completion.h>
0009 #include <linux/workqueue.h>
0010 #include <linux/mtd/rawnand.h>
0011 #include <linux/spinlock.h>
0012
0013
0014 /* nand interface + ecc
0015    byte write/read does one cycle on nand data lines.
0016    dword write/read does 4 cycles
0017    if R852_CTL_ECC_ACCESS is set in R852_CTL, then dword read reads
0018    results of ecc correction, if DMA read was done before.
0019    If write was done two dword reads read generated ecc checksums
0020 */
0021 #define R852_DATALINE       0x00
0022
0023 /* control register */
0024 #define R852_CTL        0x04
0025 #define R852_CTL_COMMAND    0x01    /* send command (#CLE)*/
0026 #define R852_CTL_DATA       0x02    /* read/write data (#ALE)*/
0027 #define R852_CTL_ON     0x04    /* only seem to controls the hd led, */
0028                     /* but has to be set on start...*/
0029 #define R852_CTL_RESET      0x08    /* unknown, set only on start once*/
0030 #define R852_CTL_CARDENABLE 0x10    /* probably (#CE) - always set*/
0031 #define R852_CTL_ECC_ENABLE 0x20    /* enable ecc engine */
0032 #define R852_CTL_ECC_ACCESS 0x40    /* read/write ecc via reg #0*/
0033 #define R852_CTL_WRITE      0x80    /* set when performing writes (#WP) */
0034
0035 /* card detection status */
0036 #define R852_CARD_STA       0x05
0037
0038 #define R852_CARD_STA_CD    0x01    /* state of #CD line, same as 0x04 */
0039 #define R852_CARD_STA_RO    0x02    /* card is readonly */
0040 #define R852_CARD_STA_PRESENT   0x04    /* card is present (#CD) */
0041 #define R852_CARD_STA_ABSENT    0x08    /* card is absent */
0042 #define R852_CARD_STA_BUSY  0x80    /* card is busy - (#R/B) */
0043
0044 /* card detection irq status & enable*/
0045 #define R852_CARD_IRQ_STA   0x06    /* IRQ status */
0046 #define R852_CARD_IRQ_ENABLE    0x07    /* IRQ enable */
0047
0048 #define R852_CARD_IRQ_CD    0x01    /* fire when #CD lights, same as 0x04*/
0049 #define R852_CARD_IRQ_REMOVE    0x04    /* detect card removal */
0050 #define R852_CARD_IRQ_INSERT    0x08    /* detect card insert */
0051 #define R852_CARD_IRQ_UNK1  0x10    /* unknown */
0052 #define R852_CARD_IRQ_GENABLE   0x80    /* general enable */
0053 #define R852_CARD_IRQ_MASK  0x1D
0054
0055
0056
0057 /* hardware enable */
0058 #define R852_HW         0x08
0059 #define R852_HW_ENABLED     0x01    /* hw enabled */
0060 #define R852_HW_UNKNOWN     0x80
0061
0062
0063 /* dma capabilities */
0064 #define R852_DMA_CAP        0x09
0065 #define R852_SMBIT      0x20    /* if set with bit #6 or bit #7, then */
0066                     /* hw is smartmedia */
0067 #define R852_DMA1       0x40    /* if set w/bit #7, dma is supported */
0068 #define R852_DMA2       0x80    /* if set w/bit #6, dma is supported */
0069
0070
0071 /* physical DMA address - 32 bit value*/
0072 #define R852_DMA_ADDR       0x0C
0073
0074
0075 /* dma settings */
0076 #define R852_DMA_SETTINGS   0x10
0077 #define R852_DMA_MEMORY     0x01    /* (memory <-> internal hw buffer) */
0078 #define R852_DMA_READ       0x02    /* 0 = write, 1 = read */
0079 #define R852_DMA_INTERNAL   0x04    /* (internal hw buffer <-> card) */
0080
0081 /* dma IRQ status */
0082 #define R852_DMA_IRQ_STA        0x14
0083
0084 /* dma IRQ enable */
0085 #define R852_DMA_IRQ_ENABLE 0x18
0086
0087 #define R852_DMA_IRQ_MEMORY 0x01    /* (memory <-> internal hw buffer) */
0088 #define R852_DMA_IRQ_ERROR  0x02    /* error did happen */
0089 #define R852_DMA_IRQ_INTERNAL   0x04    /* (internal hw buffer <-> card) */
0090 #define R852_DMA_IRQ_MASK   0x07    /* mask of all IRQ bits */
0091
0092
0093 /* ECC syndrome format - read from reg #0 will return two copies of these for
0094    each half of the page.
0095    first byte is error byte location, and second, bit location + flags */
0096 #define R852_ECC_ERR_BIT_MSK    0x07    /* error bit location */
0097 #define R852_ECC_CORRECT        0x10    /* no errors - (guessed) */
0098 #define R852_ECC_CORRECTABLE    0x20    /* correctable error exist */
0099 #define R852_ECC_FAIL       0x40    /* non correctable error detected */
0100
0101 #define R852_DMA_LEN        512
0102
0103 #define DMA_INTERNAL    0
0104 #define DMA_MEMORY  1
0105
0106 struct r852_device {
0107     struct nand_controller      controller;
0108     void __iomem *mmio;     /* mmio */
0109     struct nand_chip *chip;     /* nand chip backpointer */
0110     struct pci_dev *pci_dev;    /* pci backpointer */
0111
0112     /* dma area */
0113     dma_addr_t phys_dma_addr;   /* bus address of buffer*/
0114     struct completion dma_done; /* data transfer done */
0115
0116     dma_addr_t phys_bounce_buffer;  /* bus address of bounce buffer */
0117     uint8_t *bounce_buffer;     /* virtual address of bounce buffer */
0118
0119     int dma_dir;            /* 1 = read, 0 = write */
0120     int dma_stage;          /* 0 - idle, 1 - first step,
0121                        2 - second step */
0122
0123     int dma_state;          /* 0 = internal, 1 = memory */
0124     int dma_error;          /* dma errors */
0125     int dma_usable;         /* is it possible to use dma */
0126
0127     /* card status area */
0128     struct delayed_work card_detect_work;
0129     struct workqueue_struct *card_workqueue;
0130     int card_registered;        /* card registered with mtd */
0131     int card_detected;      /* card detected in slot */
0132     int card_unstable;      /* whenever the card is inserted,
0133                        is not known yet */
0134     int readonly;           /* card is readonly */
0135     int sm;             /* Is card smartmedia */
0136
0137     /* interrupt handling */
0138     spinlock_t irqlock;     /* IRQ protecting lock */
0139     int irq;            /* irq num */
0140     /* misc */
0141     void *tmp_buffer;       /* temporary buffer */
0142     uint8_t ctlreg;         /* cached contents of control reg */
0143 };
0144
0145 #define dbg(format, ...) \
0146     if (debug) \
0147         pr_debug(format "\n", ## __VA_ARGS__)
0148
0149 #define dbg_verbose(format, ...) \
0150     if (debug > 1) \
0151         pr_debug(format "\n", ## __VA_ARGS__)
0152
0153
0154 #define message(format, ...) \
0155     pr_info(format "\n", ## __VA_ARGS__)