nand/raw/pasemi_nand.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2006-2007 PA Semi, Inc
0004  *
0005  * Author: Egor Martovetsky <egor@pasemi.com>
0006  * Maintained by: Olof Johansson <olof@lixom.net>
0007  *
0008  * Driver for the PWRficient onchip NAND flash interface
0009  */
0010
0011 #undef DEBUG
0012
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pci.h>
0022
0023 #include <asm/io.h>
0024
0025 #define LBICTRL_LPCCTL_NR       0x00004000
0026 #define CLE_PIN_CTL         15
0027 #define ALE_PIN_CTL         14
0028
0029 static unsigned int lpcctl;
0030 static struct mtd_info *pasemi_nand_mtd;
0031 static struct nand_controller controller;
0032 static const char driver_name[] = "pasemi-nand";
0033
0034 static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len)
0035 {
0036     while (len > 0x800) {
0037         memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800);
0038         buf += 0x800;
0039         len -= 0x800;
0040     }
0041     memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len);
0042 }
0043
0044 static void pasemi_write_buf(struct nand_chip *chip, const u_char *buf,
0045                  int len)
0046 {
0047     while (len > 0x800) {
0048         memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800);
0049         buf += 0x800;
0050         len -= 0x800;
0051     }
0052     memcpy_toio(chip->legacy.IO_ADDR_R, buf, len);
0053 }
0054
0055 static void pasemi_hwcontrol(struct nand_chip *chip, int cmd,
0056                  unsigned int ctrl)
0057 {
0058     if (cmd == NAND_CMD_NONE)
0059         return;
0060
0061     if (ctrl & NAND_CLE)
0062         out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
0063     else
0064         out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
0065
0066     /* Push out posted writes */
0067     eieio();
0068     inl(lpcctl);
0069 }
0070
0071 static int pasemi_device_ready(struct nand_chip *chip)
0072 {
0073     return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR);
0074 }
0075
0076 static int pasemi_attach_chip(struct nand_chip *chip)
0077 {
0078     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
0079         chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
0080         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0081
0082     return 0;
0083 }
0084
0085 static const struct nand_controller_ops pasemi_ops = {
0086     .attach_chip = pasemi_attach_chip,
0087 };
0088
0089 static int pasemi_nand_probe(struct platform_device *ofdev)
0090 {
0091     struct device *dev = &ofdev->dev;
0092     struct pci_dev *pdev;
0093     struct device_node *np = dev->of_node;
0094     struct resource res;
0095     struct nand_chip *chip;
0096     int err = 0;
0097
0098     err = of_address_to_resource(np, 0, &res);
0099
0100     if (err)
0101         return -EINVAL;
0102
0103     /* We only support one device at the moment */
0104     if (pasemi_nand_mtd)
0105         return -ENODEV;
0106
0107     dev_dbg(dev, "pasemi_nand at %pR\n", &res);
0108
0109     /* Allocate memory for MTD device structure and private data */
0110     chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
0111     if (!chip) {
0112         err = -ENOMEM;
0113         goto out;
0114     }
0115
0116     controller.ops = &pasemi_ops;
0117     nand_controller_init(&controller);
0118     chip->controller = &controller;
0119
0120     pasemi_nand_mtd = nand_to_mtd(chip);
0121
0122     /* Link the private data with the MTD structure */
0123     pasemi_nand_mtd->dev.parent = dev;
0124
0125     chip->legacy.IO_ADDR_R = of_iomap(np, 0);
0126     chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
0127
0128     if (!chip->legacy.IO_ADDR_R) {
0129         err = -EIO;
0130         goto out_mtd;
0131     }
0132
0133     pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
0134     if (!pdev) {
0135         err = -ENODEV;
0136         goto out_ior;
0137     }
0138
0139     lpcctl = pci_resource_start(pdev, 0);
0140     pci_dev_put(pdev);
0141
0142     if (!request_region(lpcctl, 4, driver_name)) {
0143         err = -EBUSY;
0144         goto out_ior;
0145     }
0146
0147     chip->legacy.cmd_ctrl = pasemi_hwcontrol;
0148     chip->legacy.dev_ready = pasemi_device_ready;
0149     chip->legacy.read_buf = pasemi_read_buf;
0150     chip->legacy.write_buf = pasemi_write_buf;
0151     chip->legacy.chip_delay = 0;
0152
0153     /* Enable the following for a flash based bad block table */
0154     chip->bbt_options = NAND_BBT_USE_FLASH;
0155
0156     /*
0157      * This driver assumes that the default ECC engine should be TYPE_SOFT.
0158      * Set ->engine_type before registering the NAND devices in order to
0159      * provide a driver specific default value.
0160      */
0161     chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0162
0163     /* Scan to find existence of the device */
0164     err = nand_scan(chip, 1);
0165     if (err)
0166         goto out_lpc;
0167
0168     if (mtd_device_register(pasemi_nand_mtd, NULL, 0)) {
0169         dev_err(dev, "Unable to register MTD device\n");
0170         err = -ENODEV;
0171         goto out_cleanup_nand;
0172     }
0173
0174     dev_info(dev, "PA Semi NAND flash at %pR, control at I/O %x\n", &res,
0175          lpcctl);
0176
0177     return 0;
0178
0179  out_cleanup_nand:
0180     nand_cleanup(chip);
0181  out_lpc:
0182     release_region(lpcctl, 4);
0183  out_ior:
0184     iounmap(chip->legacy.IO_ADDR_R);
0185  out_mtd:
0186     kfree(chip);
0187  out:
0188     return err;
0189 }
0190
0191 static int pasemi_nand_remove(struct platform_device *ofdev)
0192 {
0193     struct nand_chip *chip;
0194     int ret;
0195
0196     if (!pasemi_nand_mtd)
0197         return 0;
0198
0199     chip = mtd_to_nand(pasemi_nand_mtd);
0200
0201     /* Release resources, unregister device */
0202     ret = mtd_device_unregister(pasemi_nand_mtd);
0203     WARN_ON(ret);
0204     nand_cleanup(chip);
0205
0206     release_region(lpcctl, 4);
0207
0208     iounmap(chip->legacy.IO_ADDR_R);
0209
0210     /* Free the MTD device structure */
0211     kfree(chip);
0212
0213     pasemi_nand_mtd = NULL;
0214
0215     return 0;
0216 }
0217
0218 static const struct of_device_id pasemi_nand_match[] =
0219 {
0220     {
0221         .compatible   = "pasemi,localbus-nand",
0222     },
0223     {},
0224 };
0225
0226 MODULE_DEVICE_TABLE(of, pasemi_nand_match);
0227
0228 static struct platform_driver pasemi_nand_driver =
0229 {
0230     .driver = {
0231         .name = driver_name,
0232         .of_match_table = pasemi_nand_match,
0233     },
0234     .probe      = pasemi_nand_probe,
0235     .remove     = pasemi_nand_remove,
0236 };
0237
0238 module_platform_driver(pasemi_nand_driver);
0239
0240 MODULE_LICENSE("GPL");
0241 MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
0242 MODULE_DESCRIPTION("NAND flash interface driver for PA Semi PWRficient");