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0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017 #include <linux/clk.h>
0018 #include <linux/reset.h>
0019 #include <linux/mtd/mtd.h>
0020 #include <linux/mtd/rawnand.h>
0021 #include <linux/mtd/partitions.h>
0022 #include <linux/of.h>
0023
0024
0025 #define OXNAS_NAND_CMD_ALE BIT(18)
0026 #define OXNAS_NAND_CMD_CLE BIT(19)
0027
0028 #define OXNAS_NAND_MAX_CHIPS 1
0029
0030 struct oxnas_nand_ctrl {
0031 struct nand_controller base;
0032 void __iomem *io_base;
0033 struct clk *clk;
0034 struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
0035 unsigned int nchips;
0036 };
0037
0038 static uint8_t oxnas_nand_read_byte(struct nand_chip *chip)
0039 {
0040 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
0041
0042 return readb(oxnas->io_base);
0043 }
0044
0045 static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
0046 {
0047 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
0048
0049 ioread8_rep(oxnas->io_base, buf, len);
0050 }
0051
0052 static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf,
0053 int len)
0054 {
0055 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
0056
0057 iowrite8_rep(oxnas->io_base, buf, len);
0058 }
0059
0060
0061 static void oxnas_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
0062 unsigned int ctrl)
0063 {
0064 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
0065
0066 if (ctrl & NAND_CLE)
0067 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
0068 else if (ctrl & NAND_ALE)
0069 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
0070 }
0071
0072
0073
0074
0075 static int oxnas_nand_probe(struct platform_device *pdev)
0076 {
0077 struct device_node *np = pdev->dev.of_node;
0078 struct device_node *nand_np;
0079 struct oxnas_nand_ctrl *oxnas;
0080 struct nand_chip *chip;
0081 struct mtd_info *mtd;
0082 int count = 0;
0083 int err = 0;
0084 int i;
0085
0086
0087 oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas),
0088 GFP_KERNEL);
0089 if (!oxnas)
0090 return -ENOMEM;
0091
0092 nand_controller_init(&oxnas->base);
0093
0094 oxnas->io_base = devm_platform_ioremap_resource(pdev, 0);
0095 if (IS_ERR(oxnas->io_base))
0096 return PTR_ERR(oxnas->io_base);
0097
0098 oxnas->clk = devm_clk_get(&pdev->dev, NULL);
0099 if (IS_ERR(oxnas->clk))
0100 oxnas->clk = NULL;
0101
0102
0103 count = of_get_child_count(np);
0104 if (count > 1)
0105 return -EINVAL;
0106
0107 err = clk_prepare_enable(oxnas->clk);
0108 if (err)
0109 return err;
0110
0111 device_reset_optional(&pdev->dev);
0112
0113 for_each_child_of_node(np, nand_np) {
0114 chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
0115 GFP_KERNEL);
0116 if (!chip) {
0117 err = -ENOMEM;
0118 goto err_release_child;
0119 }
0120
0121 chip->controller = &oxnas->base;
0122
0123 nand_set_flash_node(chip, nand_np);
0124 nand_set_controller_data(chip, oxnas);
0125
0126 mtd = nand_to_mtd(chip);
0127 mtd->dev.parent = &pdev->dev;
0128 mtd->priv = chip;
0129
0130 chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl;
0131 chip->legacy.read_buf = oxnas_nand_read_buf;
0132 chip->legacy.read_byte = oxnas_nand_read_byte;
0133 chip->legacy.write_buf = oxnas_nand_write_buf;
0134 chip->legacy.chip_delay = 30;
0135
0136
0137 err = nand_scan(chip, 1);
0138 if (err)
0139 goto err_release_child;
0140
0141 err = mtd_device_register(mtd, NULL, 0);
0142 if (err)
0143 goto err_cleanup_nand;
0144
0145 oxnas->chips[oxnas->nchips++] = chip;
0146 }
0147
0148
0149 if (!oxnas->nchips) {
0150 err = -ENODEV;
0151 goto err_clk_unprepare;
0152 }
0153
0154 platform_set_drvdata(pdev, oxnas);
0155
0156 return 0;
0157
0158 err_cleanup_nand:
0159 nand_cleanup(chip);
0160 err_release_child:
0161 of_node_put(nand_np);
0162
0163 for (i = 0; i < oxnas->nchips; i++) {
0164 chip = oxnas->chips[i];
0165 WARN_ON(mtd_device_unregister(nand_to_mtd(chip)));
0166 nand_cleanup(chip);
0167 }
0168
0169 err_clk_unprepare:
0170 clk_disable_unprepare(oxnas->clk);
0171 return err;
0172 }
0173
0174 static int oxnas_nand_remove(struct platform_device *pdev)
0175 {
0176 struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
0177 struct nand_chip *chip;
0178 int i;
0179
0180 for (i = 0; i < oxnas->nchips; i++) {
0181 chip = oxnas->chips[i];
0182 WARN_ON(mtd_device_unregister(nand_to_mtd(chip)));
0183 nand_cleanup(chip);
0184 }
0185
0186 clk_disable_unprepare(oxnas->clk);
0187
0188 return 0;
0189 }
0190
0191 static const struct of_device_id oxnas_nand_match[] = {
0192 { .compatible = "oxsemi,ox820-nand" },
0193 {},
0194 };
0195 MODULE_DEVICE_TABLE(of, oxnas_nand_match);
0196
0197 static struct platform_driver oxnas_nand_driver = {
0198 .probe = oxnas_nand_probe,
0199 .remove = oxnas_nand_remove,
0200 .driver = {
0201 .name = "oxnas_nand",
0202 .of_match_table = oxnas_nand_match,
0203 },
0204 };
0205
0206 module_platform_driver(oxnas_nand_driver);
0207
0208 MODULE_LICENSE("GPL");
0209 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0210 MODULE_DESCRIPTION("Oxnas NAND driver");
0211 MODULE_ALIAS("platform:oxnas_nand");