nand/raw/orion_nand.c

0001 /*
0002  * NAND support for Marvell Orion SoC platforms
0003  *
0004  * Tzachi Perelstein <tzachi@marvell.com>
0005  *
0006  * This file is licensed under  the terms of the GNU General Public
0007  * License version 2. This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010
0011 #include <linux/slab.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/of.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/mtd/partitions.h>
0018 #include <linux/clk.h>
0019 #include <linux/err.h>
0020 #include <linux/io.h>
0021 #include <linux/sizes.h>
0022 #include <linux/platform_data/mtd-orion_nand.h>
0023
0024 struct orion_nand_info {
0025     struct nand_controller controller;
0026     struct nand_chip chip;
0027     struct clk *clk;
0028 };
0029
0030 static void orion_nand_cmd_ctrl(struct nand_chip *nc, int cmd,
0031                 unsigned int ctrl)
0032 {
0033     struct orion_nand_data *board = nand_get_controller_data(nc);
0034     u32 offs;
0035
0036     if (cmd == NAND_CMD_NONE)
0037         return;
0038
0039     if (ctrl & NAND_CLE)
0040         offs = (1 << board->cle);
0041     else if (ctrl & NAND_ALE)
0042         offs = (1 << board->ale);
0043     else
0044         return;
0045
0046     if (nc->options & NAND_BUSWIDTH_16)
0047         offs <<= 1;
0048
0049     writeb(cmd, nc->legacy.IO_ADDR_W + offs);
0050 }
0051
0052 static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0053 {
0054     void __iomem *io_base = chip->legacy.IO_ADDR_R;
0055 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
0056     uint64_t *buf64;
0057 #endif
0058     int i = 0;
0059
0060     while (len && (unsigned long)buf & 7) {
0061         *buf++ = readb(io_base);
0062         len--;
0063     }
0064 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
0065     buf64 = (uint64_t *)buf;
0066     while (i < len/8) {
0067         /*
0068          * Since GCC has no proper constraint (PR 43518)
0069          * force x variable to r2/r3 registers as ldrd instruction
0070          * requires first register to be even.
0071          */
0072         register uint64_t x asm ("r2");
0073
0074         asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
0075         buf64[i++] = x;
0076     }
0077     i *= 8;
0078 #else
0079     readsl(io_base, buf, len/4);
0080     i = len / 4 * 4;
0081 #endif
0082     while (i < len)
0083         buf[i++] = readb(io_base);
0084 }
0085
0086 static int orion_nand_attach_chip(struct nand_chip *chip)
0087 {
0088     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
0089         chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
0090         chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
0091
0092     return 0;
0093 }
0094
0095 static const struct nand_controller_ops orion_nand_ops = {
0096     .attach_chip = orion_nand_attach_chip,
0097 };
0098
0099 static int __init orion_nand_probe(struct platform_device *pdev)
0100 {
0101     struct orion_nand_info *info;
0102     struct mtd_info *mtd;
0103     struct nand_chip *nc;
0104     struct orion_nand_data *board;
0105     struct resource *res;
0106     void __iomem *io_base;
0107     int ret = 0;
0108     u32 val = 0;
0109
0110     info = devm_kzalloc(&pdev->dev,
0111             sizeof(struct orion_nand_info),
0112             GFP_KERNEL);
0113     if (!info)
0114         return -ENOMEM;
0115     nc = &info->chip;
0116     mtd = nand_to_mtd(nc);
0117
0118     nand_controller_init(&info->controller);
0119     info->controller.ops = &orion_nand_ops;
0120     nc->controller = &info->controller;
0121
0122     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0123     io_base = devm_ioremap_resource(&pdev->dev, res);
0124
0125     if (IS_ERR(io_base))
0126         return PTR_ERR(io_base);
0127
0128     if (pdev->dev.of_node) {
0129         board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
0130                     GFP_KERNEL);
0131         if (!board)
0132             return -ENOMEM;
0133         if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
0134             board->cle = (u8)val;
0135         else
0136             board->cle = 0;
0137         if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
0138             board->ale = (u8)val;
0139         else
0140             board->ale = 1;
0141         if (!of_property_read_u32(pdev->dev.of_node,
0142                         "bank-width", &val))
0143             board->width = (u8)val * 8;
0144         else
0145             board->width = 8;
0146         if (!of_property_read_u32(pdev->dev.of_node,
0147                         "chip-delay", &val))
0148             board->chip_delay = (u8)val;
0149     } else {
0150         board = dev_get_platdata(&pdev->dev);
0151     }
0152
0153     mtd->dev.parent = &pdev->dev;
0154
0155     nand_set_controller_data(nc, board);
0156     nand_set_flash_node(nc, pdev->dev.of_node);
0157     nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
0158     nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
0159     nc->legacy.read_buf = orion_nand_read_buf;
0160
0161     if (board->chip_delay)
0162         nc->legacy.chip_delay = board->chip_delay;
0163
0164     WARN(board->width > 16,
0165         "%d bit bus width out of range",
0166         board->width);
0167
0168     if (board->width == 16)
0169         nc->options |= NAND_BUSWIDTH_16;
0170
0171     platform_set_drvdata(pdev, info);
0172
0173     /* Not all platforms can gate the clock, so it is not
0174        an error if the clock does not exists. */
0175     info->clk = devm_clk_get(&pdev->dev, NULL);
0176     if (IS_ERR(info->clk)) {
0177         ret = PTR_ERR(info->clk);
0178         if (ret == -ENOENT) {
0179             info->clk = NULL;
0180         } else {
0181             dev_err(&pdev->dev, "failed to get clock!\n");
0182             return ret;
0183         }
0184     }
0185
0186     ret = clk_prepare_enable(info->clk);
0187     if (ret) {
0188         dev_err(&pdev->dev, "failed to prepare clock!\n");
0189         return ret;
0190     }
0191
0192     /*
0193      * This driver assumes that the default ECC engine should be TYPE_SOFT.
0194      * Set ->engine_type before registering the NAND devices in order to
0195      * provide a driver specific default value.
0196      */
0197     nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
0198
0199     ret = nand_scan(nc, 1);
0200     if (ret)
0201         goto no_dev;
0202
0203     mtd->name = "orion_nand";
0204     ret = mtd_device_register(mtd, board->parts, board->nr_parts);
0205     if (ret) {
0206         nand_cleanup(nc);
0207         goto no_dev;
0208     }
0209
0210     return 0;
0211
0212 no_dev:
0213     clk_disable_unprepare(info->clk);
0214     return ret;
0215 }
0216
0217 static int orion_nand_remove(struct platform_device *pdev)
0218 {
0219     struct orion_nand_info *info = platform_get_drvdata(pdev);
0220     struct nand_chip *chip = &info->chip;
0221     int ret;
0222
0223     ret = mtd_device_unregister(nand_to_mtd(chip));
0224     WARN_ON(ret);
0225
0226     nand_cleanup(chip);
0227
0228     clk_disable_unprepare(info->clk);
0229
0230     return 0;
0231 }
0232
0233 #ifdef CONFIG_OF
0234 static const struct of_device_id orion_nand_of_match_table[] = {
0235     { .compatible = "marvell,orion-nand", },
0236     {},
0237 };
0238 MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
0239 #endif
0240
0241 static struct platform_driver orion_nand_driver = {
0242     .remove     = orion_nand_remove,
0243     .driver     = {
0244         .name   = "orion_nand",
0245         .of_match_table = of_match_ptr(orion_nand_of_match_table),
0246     },
0247 };
0248
0249 module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
0250
0251 MODULE_LICENSE("GPL");
0252 MODULE_AUTHOR("Tzachi Perelstein");
0253 MODULE_DESCRIPTION("NAND glue for Orion platforms");
0254 MODULE_ALIAS("platform:orion_nand");