nand/raw/ndfc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Overview:
0004  *   Platform independent driver for NDFC (NanD Flash Controller)
0005  *   integrated into EP440 cores
0006  *
0007  *   Ported to an OF platform driver by Sean MacLennan
0008  *
0009  *   The NDFC supports multiple chips, but this driver only supports a
0010  *   single chip since I do not have access to any boards with
0011  *   multiple chips.
0012  *
0013  *  Author: Thomas Gleixner
0014  *
0015  *  Copyright 2006 IBM
0016  *  Copyright 2008 PIKA Technologies
0017  *    Sean MacLennan <smaclennan@pikatech.com>
0018  */
0019 #include <linux/module.h>
0020 #include <linux/mtd/rawnand.h>
0021 #include <linux/mtd/partitions.h>
0022 #include <linux/mtd/ndfc.h>
0023 #include <linux/slab.h>
0024 #include <linux/mtd/mtd.h>
0025 #include <linux/of_address.h>
0026 #include <linux/of_platform.h>
0027 #include <asm/io.h>
0028
0029 #define NDFC_MAX_CS    4
0030
0031 struct ndfc_controller {
0032     struct platform_device *ofdev;
0033     void __iomem *ndfcbase;
0034     struct nand_chip chip;
0035     int chip_select;
0036     struct nand_controller ndfc_control;
0037 };
0038
0039 static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
0040
0041 static void ndfc_select_chip(struct nand_chip *nchip, int chip)
0042 {
0043     uint32_t ccr;
0044     struct ndfc_controller *ndfc = nand_get_controller_data(nchip);
0045
0046     ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
0047     if (chip >= 0) {
0048         ccr &= ~NDFC_CCR_BS_MASK;
0049         ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
0050     } else
0051         ccr |= NDFC_CCR_RESET_CE;
0052     out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
0053 }
0054
0055 static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
0056 {
0057     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0058
0059     if (cmd == NAND_CMD_NONE)
0060         return;
0061
0062     if (ctrl & NAND_CLE)
0063         writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
0064     else
0065         writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
0066 }
0067
0068 static int ndfc_ready(struct nand_chip *chip)
0069 {
0070     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0071
0072     return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
0073 }
0074
0075 static void ndfc_enable_hwecc(struct nand_chip *chip, int mode)
0076 {
0077     uint32_t ccr;
0078     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0079
0080     ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
0081     ccr |= NDFC_CCR_RESET_ECC;
0082     out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
0083     wmb();
0084 }
0085
0086 static int ndfc_calculate_ecc(struct nand_chip *chip,
0087                   const u_char *dat, u_char *ecc_code)
0088 {
0089     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0090     uint32_t ecc;
0091     uint8_t *p = (uint8_t *)&ecc;
0092
0093     wmb();
0094     ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
0095     /* The NDFC uses Smart Media (SMC) bytes order */
0096     ecc_code[0] = p[1];
0097     ecc_code[1] = p[2];
0098     ecc_code[2] = p[3];
0099
0100     return 0;
0101 }
0102
0103 /*
0104  * Speedups for buffer read/write/verify
0105  *
0106  * NDFC allows 32bit read/write of data. So we can speed up the buffer
0107  * functions. No further checking, as nand_base will always read/write
0108  * page aligned.
0109  */
0110 static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0111 {
0112     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0113     uint32_t *p = (uint32_t *) buf;
0114
0115     for(;len > 0; len -= 4)
0116         *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
0117 }
0118
0119 static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
0120 {
0121     struct ndfc_controller *ndfc = nand_get_controller_data(chip);
0122     uint32_t *p = (uint32_t *) buf;
0123
0124     for(;len > 0; len -= 4)
0125         out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
0126 }
0127
0128 /*
0129  * Initialize chip structure
0130  */
0131 static int ndfc_chip_init(struct ndfc_controller *ndfc,
0132               struct device_node *node)
0133 {
0134     struct device_node *flash_np;
0135     struct nand_chip *chip = &ndfc->chip;
0136     struct mtd_info *mtd = nand_to_mtd(chip);
0137     int ret;
0138
0139     chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
0140     chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
0141     chip->legacy.cmd_ctrl = ndfc_hwcontrol;
0142     chip->legacy.dev_ready = ndfc_ready;
0143     chip->legacy.select_chip = ndfc_select_chip;
0144     chip->legacy.chip_delay = 50;
0145     chip->controller = &ndfc->ndfc_control;
0146     chip->legacy.read_buf = ndfc_read_buf;
0147     chip->legacy.write_buf = ndfc_write_buf;
0148     chip->ecc.correct = rawnand_sw_hamming_correct;
0149     chip->ecc.hwctl = ndfc_enable_hwecc;
0150     chip->ecc.calculate = ndfc_calculate_ecc;
0151     chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
0152     chip->ecc.size = 256;
0153     chip->ecc.bytes = 3;
0154     chip->ecc.strength = 1;
0155     nand_set_controller_data(chip, ndfc);
0156
0157     mtd->dev.parent = &ndfc->ofdev->dev;
0158
0159     flash_np = of_get_next_child(node, NULL);
0160     if (!flash_np)
0161         return -ENODEV;
0162     nand_set_flash_node(chip, flash_np);
0163
0164     mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev),
0165                   flash_np);
0166     if (!mtd->name) {
0167         ret = -ENOMEM;
0168         goto err;
0169     }
0170
0171     ret = nand_scan(chip, 1);
0172     if (ret)
0173         goto err;
0174
0175     ret = mtd_device_register(mtd, NULL, 0);
0176
0177 err:
0178     of_node_put(flash_np);
0179     if (ret)
0180         kfree(mtd->name);
0181     return ret;
0182 }
0183
0184 static int ndfc_probe(struct platform_device *ofdev)
0185 {
0186     struct ndfc_controller *ndfc;
0187     const __be32 *reg;
0188     u32 ccr;
0189     u32 cs;
0190     int err, len;
0191
0192     /* Read the reg property to get the chip select */
0193     reg = of_get_property(ofdev->dev.of_node, "reg", &len);
0194     if (reg == NULL || len != 12) {
0195         dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
0196         return -ENOENT;
0197     }
0198
0199     cs = be32_to_cpu(reg[0]);
0200     if (cs >= NDFC_MAX_CS) {
0201         dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
0202         return -EINVAL;
0203     }
0204
0205     ndfc = &ndfc_ctrl[cs];
0206     ndfc->chip_select = cs;
0207
0208     nand_controller_init(&ndfc->ndfc_control);
0209     ndfc->ofdev = ofdev;
0210     dev_set_drvdata(&ofdev->dev, ndfc);
0211
0212     ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
0213     if (!ndfc->ndfcbase) {
0214         dev_err(&ofdev->dev, "failed to get memory\n");
0215         return -EIO;
0216     }
0217
0218     ccr = NDFC_CCR_BS(ndfc->chip_select);
0219
0220     /* It is ok if ccr does not exist - just default to 0 */
0221     reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
0222     if (reg)
0223         ccr |= be32_to_cpup(reg);
0224
0225     out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
0226
0227     /* Set the bank settings if given */
0228     reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
0229     if (reg) {
0230         int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
0231         out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
0232     }
0233
0234     err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
0235     if (err) {
0236         iounmap(ndfc->ndfcbase);
0237         return err;
0238     }
0239
0240     return 0;
0241 }
0242
0243 static int ndfc_remove(struct platform_device *ofdev)
0244 {
0245     struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
0246     struct nand_chip *chip = &ndfc->chip;
0247     struct mtd_info *mtd = nand_to_mtd(chip);
0248     int ret;
0249
0250     ret = mtd_device_unregister(mtd);
0251     WARN_ON(ret);
0252     nand_cleanup(chip);
0253     kfree(mtd->name);
0254
0255     return 0;
0256 }
0257
0258 static const struct of_device_id ndfc_match[] = {
0259     { .compatible = "ibm,ndfc", },
0260     {}
0261 };
0262 MODULE_DEVICE_TABLE(of, ndfc_match);
0263
0264 static struct platform_driver ndfc_driver = {
0265     .driver = {
0266         .name = "ndfc",
0267         .of_match_table = ndfc_match,
0268     },
0269     .probe = ndfc_probe,
0270     .remove = ndfc_remove,
0271 };
0272
0273 module_platform_driver(ndfc_driver);
0274
0275 MODULE_LICENSE("GPL");
0276 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
0277 MODULE_DESCRIPTION("OF Platform driver for NDFC");