nand/raw/nand_macronix.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2017 Free Electrons
0004  * Copyright (C) 2017 NextThing Co
0005  *
0006  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
0007  */
0008
0009 #include "linux/delay.h"
0010 #include "internals.h"
0011
0012 #define MACRONIX_READ_RETRY_BIT BIT(0)
0013 #define MACRONIX_NUM_READ_RETRY_MODES 6
0014
0015 #define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
0016 #define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
0017 #define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
0018
0019 #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
0020 #define MACRONIX_RANDOMIZER_BIT BIT(1)
0021 #define MACRONIX_RANDOMIZER_ENPGM BIT(0)
0022 #define MACRONIX_RANDOMIZER_RANDEN BIT(1)
0023 #define MACRONIX_RANDOMIZER_RANDOPT BIT(2)
0024 #define MACRONIX_RANDOMIZER_MODE_ENTER  \
0025     (MACRONIX_RANDOMIZER_ENPGM |    \
0026      MACRONIX_RANDOMIZER_RANDEN |   \
0027      MACRONIX_RANDOMIZER_RANDOPT)
0028 #define MACRONIX_RANDOMIZER_MODE_EXIT   \
0029     (MACRONIX_RANDOMIZER_RANDEN |   \
0030      MACRONIX_RANDOMIZER_RANDOPT)
0031
0032 #define MXIC_CMD_POWER_DOWN 0xB9
0033
0034 struct nand_onfi_vendor_macronix {
0035     u8 reserved;
0036     u8 reliability_func;
0037 } __packed;
0038
0039 static int macronix_nand_setup_read_retry(struct nand_chip *chip, int mode)
0040 {
0041     u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
0042
0043     if (!chip->parameters.supports_set_get_features ||
0044         !test_bit(ONFI_FEATURE_ADDR_READ_RETRY,
0045               chip->parameters.set_feature_list))
0046         return -ENOTSUPP;
0047
0048     feature[0] = mode;
0049     return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature);
0050 }
0051
0052 static int macronix_nand_randomizer_check_enable(struct nand_chip *chip)
0053 {
0054     u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
0055     int ret;
0056
0057     ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0058                 feature);
0059     if (ret < 0)
0060         return ret;
0061
0062     if (feature[0])
0063         return feature[0];
0064
0065     feature[0] = MACRONIX_RANDOMIZER_MODE_ENTER;
0066     ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0067                 feature);
0068     if (ret < 0)
0069         return ret;
0070
0071     /* RANDEN and RANDOPT OTP bits are programmed */
0072     feature[0] = 0x0;
0073     ret = nand_prog_page_op(chip, 0, 0, feature, 1);
0074     if (ret < 0)
0075         return ret;
0076
0077     ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0078                 feature);
0079     if (ret < 0)
0080         return ret;
0081
0082     feature[0] &= MACRONIX_RANDOMIZER_MODE_EXIT;
0083     ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0084                 feature);
0085     if (ret < 0)
0086         return ret;
0087
0088     return 0;
0089 }
0090
0091 static void macronix_nand_onfi_init(struct nand_chip *chip)
0092 {
0093     struct nand_parameters *p = &chip->parameters;
0094     struct nand_onfi_vendor_macronix *mxic;
0095     struct device_node *dn = nand_get_flash_node(chip);
0096     int rand_otp = 0;
0097     int ret;
0098
0099     if (!p->onfi)
0100         return;
0101
0102     if (of_find_property(dn, "mxic,enable-randomizer-otp", NULL))
0103         rand_otp = 1;
0104
0105     mxic = (struct nand_onfi_vendor_macronix *)p->onfi->vendor;
0106     /* Subpage write is prohibited in randomizer operatoin */
0107     if (rand_otp && chip->options & NAND_NO_SUBPAGE_WRITE &&
0108         mxic->reliability_func & MACRONIX_RANDOMIZER_BIT) {
0109         if (p->supports_set_get_features) {
0110             bitmap_set(p->set_feature_list,
0111                    ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
0112             bitmap_set(p->get_feature_list,
0113                    ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
0114             ret = macronix_nand_randomizer_check_enable(chip);
0115             if (ret < 0) {
0116                 bitmap_clear(p->set_feature_list,
0117                          ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0118                          1);
0119                 bitmap_clear(p->get_feature_list,
0120                          ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
0121                          1);
0122                 pr_info("Macronix NAND randomizer failed\n");
0123             } else {
0124                 pr_info("Macronix NAND randomizer enabled\n");
0125             }
0126         }
0127     }
0128
0129     if ((mxic->reliability_func & MACRONIX_READ_RETRY_BIT) == 0)
0130         return;
0131
0132     chip->read_retries = MACRONIX_NUM_READ_RETRY_MODES;
0133     chip->ops.setup_read_retry = macronix_nand_setup_read_retry;
0134
0135     if (p->supports_set_get_features) {
0136         bitmap_set(p->set_feature_list,
0137                ONFI_FEATURE_ADDR_READ_RETRY, 1);
0138         bitmap_set(p->get_feature_list,
0139                ONFI_FEATURE_ADDR_READ_RETRY, 1);
0140     }
0141 }
0142
0143 /*
0144  * Macronix AC series does not support using SET/GET_FEATURES to change
0145  * the timings unlike what is declared in the parameter page. Unflag
0146  * this feature to avoid unnecessary downturns.
0147  */
0148 static void macronix_nand_fix_broken_get_timings(struct nand_chip *chip)
0149 {
0150     int i;
0151     static const char * const broken_get_timings[] = {
0152         "MX30LF1G18AC",
0153         "MX30LF1G28AC",
0154         "MX30LF2G18AC",
0155         "MX30LF2G28AC",
0156         "MX30LF4G18AC",
0157         "MX30LF4G28AC",
0158         "MX60LF8G18AC",
0159         "MX30UF1G18AC",
0160         "MX30UF1G16AC",
0161         "MX30UF2G18AC",
0162         "MX30UF2G16AC",
0163         "MX30UF4G18AC",
0164         "MX30UF4G16AC",
0165         "MX30UF4G28AC",
0166     };
0167
0168     if (!chip->parameters.supports_set_get_features)
0169         return;
0170
0171     i = match_string(broken_get_timings, ARRAY_SIZE(broken_get_timings),
0172              chip->parameters.model);
0173     if (i < 0)
0174         return;
0175
0176     bitmap_clear(chip->parameters.get_feature_list,
0177              ONFI_FEATURE_ADDR_TIMING_MODE, 1);
0178     bitmap_clear(chip->parameters.set_feature_list,
0179              ONFI_FEATURE_ADDR_TIMING_MODE, 1);
0180 }
0181
0182 /*
0183  * Macronix NAND supports Block Protection by Protectoin(PT) pin;
0184  * active high at power-on which protects the entire chip even the #WP is
0185  * disabled. Lock/unlock protection area can be partition according to
0186  * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
0187  */
0188 static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
0189 {
0190     u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
0191     int ret;
0192
0193     feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
0194     nand_select_target(chip, 0);
0195     ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
0196                 feature);
0197     nand_deselect_target(chip);
0198     if (ret)
0199         pr_err("%s all blocks failed\n", __func__);
0200
0201     return ret;
0202 }
0203
0204 static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
0205 {
0206     u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
0207     int ret;
0208
0209     feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
0210     nand_select_target(chip, 0);
0211     ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
0212                 feature);
0213     nand_deselect_target(chip);
0214     if (ret)
0215         pr_err("%s all blocks failed\n", __func__);
0216
0217     return ret;
0218 }
0219
0220 static void macronix_nand_block_protection_support(struct nand_chip *chip)
0221 {
0222     u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
0223     int ret;
0224
0225     bitmap_set(chip->parameters.get_feature_list,
0226            ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
0227
0228     feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
0229     nand_select_target(chip, 0);
0230     ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
0231                 feature);
0232     nand_deselect_target(chip);
0233     if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
0234         if (ret)
0235             pr_err("Block protection check failed\n");
0236
0237         bitmap_clear(chip->parameters.get_feature_list,
0238                  ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
0239         return;
0240     }
0241
0242     bitmap_set(chip->parameters.set_feature_list,
0243            ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
0244
0245     chip->ops.lock_area = mxic_nand_lock;
0246     chip->ops.unlock_area = mxic_nand_unlock;
0247 }
0248
0249 static int nand_power_down_op(struct nand_chip *chip)
0250 {
0251     int ret;
0252
0253     if (nand_has_exec_op(chip)) {
0254         struct nand_op_instr instrs[] = {
0255             NAND_OP_CMD(MXIC_CMD_POWER_DOWN, 0),
0256         };
0257
0258         struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
0259
0260         ret = nand_exec_op(chip, &op);
0261         if (ret)
0262             return ret;
0263
0264     } else {
0265         chip->legacy.cmdfunc(chip, MXIC_CMD_POWER_DOWN, -1, -1);
0266     }
0267
0268     return 0;
0269 }
0270
0271 static int mxic_nand_suspend(struct nand_chip *chip)
0272 {
0273     int ret;
0274
0275     nand_select_target(chip, 0);
0276     ret = nand_power_down_op(chip);
0277     if (ret < 0)
0278         pr_err("Suspending MXIC NAND chip failed (%d)\n", ret);
0279     nand_deselect_target(chip);
0280
0281     return ret;
0282 }
0283
0284 static void mxic_nand_resume(struct nand_chip *chip)
0285 {
0286     /*
0287      * Toggle #CS pin to resume NAND device and don't care
0288      * of the others CLE, #WE, #RE pins status.
0289      * A NAND controller ensure it is able to assert/de-assert #CS
0290      * by sending any byte over the NAND bus.
0291      * i.e.,
0292      * NAND power down command or reset command w/o R/B# status checking.
0293      */
0294     nand_select_target(chip, 0);
0295     nand_power_down_op(chip);
0296     /* The minimum of a recovery time tRDP is 35 us */
0297     usleep_range(35, 100);
0298     nand_deselect_target(chip);
0299 }
0300
0301 static void macronix_nand_deep_power_down_support(struct nand_chip *chip)
0302 {
0303     int i;
0304     static const char * const deep_power_down_dev[] = {
0305         "MX30UF1G28AD",
0306         "MX30UF2G28AD",
0307         "MX30UF4G28AD",
0308     };
0309
0310     i = match_string(deep_power_down_dev, ARRAY_SIZE(deep_power_down_dev),
0311              chip->parameters.model);
0312     if (i < 0)
0313         return;
0314
0315     chip->ops.suspend = mxic_nand_suspend;
0316     chip->ops.resume = mxic_nand_resume;
0317 }
0318
0319 static int macronix_nand_init(struct nand_chip *chip)
0320 {
0321     if (nand_is_slc(chip))
0322         chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
0323
0324     macronix_nand_fix_broken_get_timings(chip);
0325     macronix_nand_onfi_init(chip);
0326     macronix_nand_block_protection_support(chip);
0327     macronix_nand_deep_power_down_support(chip);
0328
0329     return 0;
0330 }
0331
0332 const struct nand_manufacturer_ops macronix_nand_manuf_ops = {
0333     .init = macronix_nand_init,
0334 };