nand/raw/nand_legacy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
0004  *        2002-2006 Thomas Gleixner (tglx@linutronix.de)
0005  *
0006  *  Credits:
0007  *  David Woodhouse for adding multichip support
0008  *
0009  *  Aleph One Ltd. and Toby Churchill Ltd. for supporting the
0010  *  rework for 2K page size chips
0011  *
0012  * This file contains all legacy helpers/code that should be removed
0013  * at some point.
0014  */
0015
0016 #include <linux/delay.h>
0017 #include <linux/io.h>
0018 #include <linux/nmi.h>
0019
0020 #include "internals.h"
0021
0022 /**
0023  * nand_read_byte - [DEFAULT] read one byte from the chip
0024  * @chip: NAND chip object
0025  *
0026  * Default read function for 8bit buswidth
0027  */
0028 static uint8_t nand_read_byte(struct nand_chip *chip)
0029 {
0030     return readb(chip->legacy.IO_ADDR_R);
0031 }
0032
0033 /**
0034  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
0035  * @chip: NAND chip object
0036  *
0037  * Default read function for 16bit buswidth with endianness conversion.
0038  *
0039  */
0040 static uint8_t nand_read_byte16(struct nand_chip *chip)
0041 {
0042     return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
0043 }
0044
0045 /**
0046  * nand_select_chip - [DEFAULT] control CE line
0047  * @chip: NAND chip object
0048  * @chipnr: chipnumber to select, -1 for deselect
0049  *
0050  * Default select function for 1 chip devices.
0051  */
0052 static void nand_select_chip(struct nand_chip *chip, int chipnr)
0053 {
0054     switch (chipnr) {
0055     case -1:
0056         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0057                       0 | NAND_CTRL_CHANGE);
0058         break;
0059     case 0:
0060         break;
0061
0062     default:
0063         BUG();
0064     }
0065 }
0066
0067 /**
0068  * nand_write_byte - [DEFAULT] write single byte to chip
0069  * @chip: NAND chip object
0070  * @byte: value to write
0071  *
0072  * Default function to write a byte to I/O[7:0]
0073  */
0074 static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
0075 {
0076     chip->legacy.write_buf(chip, &byte, 1);
0077 }
0078
0079 /**
0080  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
0081  * @chip: NAND chip object
0082  * @byte: value to write
0083  *
0084  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
0085  */
0086 static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
0087 {
0088     uint16_t word = byte;
0089
0090     /*
0091      * It's not entirely clear what should happen to I/O[15:8] when writing
0092      * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
0093      *
0094      *    When the host supports a 16-bit bus width, only data is
0095      *    transferred at the 16-bit width. All address and command line
0096      *    transfers shall use only the lower 8-bits of the data bus. During
0097      *    command transfers, the host may place any value on the upper
0098      *    8-bits of the data bus. During address transfers, the host shall
0099      *    set the upper 8-bits of the data bus to 00h.
0100      *
0101      * One user of the write_byte callback is nand_set_features. The
0102      * four parameters are specified to be written to I/O[7:0], but this is
0103      * neither an address nor a command transfer. Let's assume a 0 on the
0104      * upper I/O lines is OK.
0105      */
0106     chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
0107 }
0108
0109 /**
0110  * nand_write_buf - [DEFAULT] write buffer to chip
0111  * @chip: NAND chip object
0112  * @buf: data buffer
0113  * @len: number of bytes to write
0114  *
0115  * Default write function for 8bit buswidth.
0116  */
0117 static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
0118 {
0119     iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
0120 }
0121
0122 /**
0123  * nand_read_buf - [DEFAULT] read chip data into buffer
0124  * @chip: NAND chip object
0125  * @buf: buffer to store date
0126  * @len: number of bytes to read
0127  *
0128  * Default read function for 8bit buswidth.
0129  */
0130 static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0131 {
0132     ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
0133 }
0134
0135 /**
0136  * nand_write_buf16 - [DEFAULT] write buffer to chip
0137  * @chip: NAND chip object
0138  * @buf: data buffer
0139  * @len: number of bytes to write
0140  *
0141  * Default write function for 16bit buswidth.
0142  */
0143 static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
0144                  int len)
0145 {
0146     u16 *p = (u16 *) buf;
0147
0148     iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
0149 }
0150
0151 /**
0152  * nand_read_buf16 - [DEFAULT] read chip data into buffer
0153  * @chip: NAND chip object
0154  * @buf: buffer to store date
0155  * @len: number of bytes to read
0156  *
0157  * Default read function for 16bit buswidth.
0158  */
0159 static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
0160 {
0161     u16 *p = (u16 *) buf;
0162
0163     ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
0164 }
0165
0166 /**
0167  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
0168  * @chip: NAND chip object
0169  * @timeo: Timeout
0170  *
0171  * Helper function for nand_wait_ready used when needing to wait in interrupt
0172  * context.
0173  */
0174 static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
0175 {
0176     int i;
0177
0178     /* Wait for the device to get ready */
0179     for (i = 0; i < timeo; i++) {
0180         if (chip->legacy.dev_ready(chip))
0181             break;
0182         touch_softlockup_watchdog();
0183         mdelay(1);
0184     }
0185 }
0186
0187 /**
0188  * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
0189  * @chip: NAND chip object
0190  *
0191  * Wait for the ready pin after a command, and warn if a timeout occurs.
0192  */
0193 void nand_wait_ready(struct nand_chip *chip)
0194 {
0195     struct mtd_info *mtd = nand_to_mtd(chip);
0196     unsigned long timeo = 400;
0197
0198     if (mtd->oops_panic_write)
0199         return panic_nand_wait_ready(chip, timeo);
0200
0201     /* Wait until command is processed or timeout occurs */
0202     timeo = jiffies + msecs_to_jiffies(timeo);
0203     do {
0204         if (chip->legacy.dev_ready(chip))
0205             return;
0206         cond_resched();
0207     } while (time_before(jiffies, timeo));
0208
0209     if (!chip->legacy.dev_ready(chip))
0210         pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
0211 }
0212 EXPORT_SYMBOL_GPL(nand_wait_ready);
0213
0214 /**
0215  * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
0216  * @chip: NAND chip object
0217  * @timeo: Timeout in ms
0218  *
0219  * Wait for status ready (i.e. command done) or timeout.
0220  */
0221 static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
0222 {
0223     int ret;
0224
0225     timeo = jiffies + msecs_to_jiffies(timeo);
0226     do {
0227         u8 status;
0228
0229         ret = nand_read_data_op(chip, &status, sizeof(status), true,
0230                     false);
0231         if (ret)
0232             return;
0233
0234         if (status & NAND_STATUS_READY)
0235             break;
0236         touch_softlockup_watchdog();
0237     } while (time_before(jiffies, timeo));
0238 };
0239
0240 /**
0241  * nand_command - [DEFAULT] Send command to NAND device
0242  * @chip: NAND chip object
0243  * @command: the command to be sent
0244  * @column: the column address for this command, -1 if none
0245  * @page_addr: the page address for this command, -1 if none
0246  *
0247  * Send command to NAND device. This function is used for small page devices
0248  * (512 Bytes per page).
0249  */
0250 static void nand_command(struct nand_chip *chip, unsigned int command,
0251              int column, int page_addr)
0252 {
0253     struct mtd_info *mtd = nand_to_mtd(chip);
0254     int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
0255
0256     /* Write out the command to the device */
0257     if (command == NAND_CMD_SEQIN) {
0258         int readcmd;
0259
0260         if (column >= mtd->writesize) {
0261             /* OOB area */
0262             column -= mtd->writesize;
0263             readcmd = NAND_CMD_READOOB;
0264         } else if (column < 256) {
0265             /* First 256 bytes --> READ0 */
0266             readcmd = NAND_CMD_READ0;
0267         } else {
0268             column -= 256;
0269             readcmd = NAND_CMD_READ1;
0270         }
0271         chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
0272         ctrl &= ~NAND_CTRL_CHANGE;
0273     }
0274     if (command != NAND_CMD_NONE)
0275         chip->legacy.cmd_ctrl(chip, command, ctrl);
0276
0277     /* Address cycle, when necessary */
0278     ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
0279     /* Serially input address */
0280     if (column != -1) {
0281         /* Adjust columns for 16 bit buswidth */
0282         if (chip->options & NAND_BUSWIDTH_16 &&
0283                 !nand_opcode_8bits(command))
0284             column >>= 1;
0285         chip->legacy.cmd_ctrl(chip, column, ctrl);
0286         ctrl &= ~NAND_CTRL_CHANGE;
0287     }
0288     if (page_addr != -1) {
0289         chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
0290         ctrl &= ~NAND_CTRL_CHANGE;
0291         chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
0292         if (chip->options & NAND_ROW_ADDR_3)
0293             chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
0294     }
0295     chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0296                   NAND_NCE | NAND_CTRL_CHANGE);
0297
0298     /*
0299      * Program and erase have their own busy handlers status and sequential
0300      * in needs no delay
0301      */
0302     switch (command) {
0303
0304     case NAND_CMD_NONE:
0305     case NAND_CMD_PAGEPROG:
0306     case NAND_CMD_ERASE1:
0307     case NAND_CMD_ERASE2:
0308     case NAND_CMD_SEQIN:
0309     case NAND_CMD_STATUS:
0310     case NAND_CMD_READID:
0311     case NAND_CMD_SET_FEATURES:
0312         return;
0313
0314     case NAND_CMD_RESET:
0315         if (chip->legacy.dev_ready)
0316             break;
0317         udelay(chip->legacy.chip_delay);
0318         chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
0319                       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
0320         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0321                       NAND_NCE | NAND_CTRL_CHANGE);
0322         /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
0323         nand_wait_status_ready(chip, 250);
0324         return;
0325
0326         /* This applies to read commands */
0327     case NAND_CMD_READ0:
0328         /*
0329          * READ0 is sometimes used to exit GET STATUS mode. When this
0330          * is the case no address cycles are requested, and we can use
0331          * this information to detect that we should not wait for the
0332          * device to be ready.
0333          */
0334         if (column == -1 && page_addr == -1)
0335             return;
0336         fallthrough;
0337     default:
0338         /*
0339          * If we don't have access to the busy pin, we apply the given
0340          * command delay
0341          */
0342         if (!chip->legacy.dev_ready) {
0343             udelay(chip->legacy.chip_delay);
0344             return;
0345         }
0346     }
0347     /*
0348      * Apply this short delay always to ensure that we do wait tWB in
0349      * any case on any machine.
0350      */
0351     ndelay(100);
0352
0353     nand_wait_ready(chip);
0354 }
0355
0356 static void nand_ccs_delay(struct nand_chip *chip)
0357 {
0358     const struct nand_sdr_timings *sdr =
0359         nand_get_sdr_timings(nand_get_interface_config(chip));
0360
0361     /*
0362      * The controller already takes care of waiting for tCCS when the RNDIN
0363      * or RNDOUT command is sent, return directly.
0364      */
0365     if (!(chip->options & NAND_WAIT_TCCS))
0366         return;
0367
0368     /*
0369      * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
0370      * (which should be safe for all NANDs).
0371      */
0372     if (!IS_ERR(sdr) && nand_controller_can_setup_interface(chip))
0373         ndelay(sdr->tCCS_min / 1000);
0374     else
0375         ndelay(500);
0376 }
0377
0378 /**
0379  * nand_command_lp - [DEFAULT] Send command to NAND large page device
0380  * @chip: NAND chip object
0381  * @command: the command to be sent
0382  * @column: the column address for this command, -1 if none
0383  * @page_addr: the page address for this command, -1 if none
0384  *
0385  * Send command to NAND device. This is the version for the new large page
0386  * devices. We don't have the separate regions as we have in the small page
0387  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
0388  */
0389 static void nand_command_lp(struct nand_chip *chip, unsigned int command,
0390                 int column, int page_addr)
0391 {
0392     struct mtd_info *mtd = nand_to_mtd(chip);
0393
0394     /* Emulate NAND_CMD_READOOB */
0395     if (command == NAND_CMD_READOOB) {
0396         column += mtd->writesize;
0397         command = NAND_CMD_READ0;
0398     }
0399
0400     /* Command latch cycle */
0401     if (command != NAND_CMD_NONE)
0402         chip->legacy.cmd_ctrl(chip, command,
0403                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
0404
0405     if (column != -1 || page_addr != -1) {
0406         int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
0407
0408         /* Serially input address */
0409         if (column != -1) {
0410             /* Adjust columns for 16 bit buswidth */
0411             if (chip->options & NAND_BUSWIDTH_16 &&
0412                     !nand_opcode_8bits(command))
0413                 column >>= 1;
0414             chip->legacy.cmd_ctrl(chip, column, ctrl);
0415             ctrl &= ~NAND_CTRL_CHANGE;
0416
0417             /* Only output a single addr cycle for 8bits opcodes. */
0418             if (!nand_opcode_8bits(command))
0419                 chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
0420         }
0421         if (page_addr != -1) {
0422             chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
0423             chip->legacy.cmd_ctrl(chip, page_addr >> 8,
0424                          NAND_NCE | NAND_ALE);
0425             if (chip->options & NAND_ROW_ADDR_3)
0426                 chip->legacy.cmd_ctrl(chip, page_addr >> 16,
0427                               NAND_NCE | NAND_ALE);
0428         }
0429     }
0430     chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0431                   NAND_NCE | NAND_CTRL_CHANGE);
0432
0433     /*
0434      * Program and erase have their own busy handlers status, sequential
0435      * in and status need no delay.
0436      */
0437     switch (command) {
0438
0439     case NAND_CMD_NONE:
0440     case NAND_CMD_CACHEDPROG:
0441     case NAND_CMD_PAGEPROG:
0442     case NAND_CMD_ERASE1:
0443     case NAND_CMD_ERASE2:
0444     case NAND_CMD_SEQIN:
0445     case NAND_CMD_STATUS:
0446     case NAND_CMD_READID:
0447     case NAND_CMD_SET_FEATURES:
0448         return;
0449
0450     case NAND_CMD_RNDIN:
0451         nand_ccs_delay(chip);
0452         return;
0453
0454     case NAND_CMD_RESET:
0455         if (chip->legacy.dev_ready)
0456             break;
0457         udelay(chip->legacy.chip_delay);
0458         chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
0459                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
0460         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0461                       NAND_NCE | NAND_CTRL_CHANGE);
0462         /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
0463         nand_wait_status_ready(chip, 250);
0464         return;
0465
0466     case NAND_CMD_RNDOUT:
0467         /* No ready / busy check necessary */
0468         chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
0469                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
0470         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0471                       NAND_NCE | NAND_CTRL_CHANGE);
0472
0473         nand_ccs_delay(chip);
0474         return;
0475
0476     case NAND_CMD_READ0:
0477         /*
0478          * READ0 is sometimes used to exit GET STATUS mode. When this
0479          * is the case no address cycles are requested, and we can use
0480          * this information to detect that READSTART should not be
0481          * issued.
0482          */
0483         if (column == -1 && page_addr == -1)
0484             return;
0485
0486         chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
0487                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
0488         chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
0489                       NAND_NCE | NAND_CTRL_CHANGE);
0490         fallthrough;    /* This applies to read commands */
0491     default:
0492         /*
0493          * If we don't have access to the busy pin, we apply the given
0494          * command delay.
0495          */
0496         if (!chip->legacy.dev_ready) {
0497             udelay(chip->legacy.chip_delay);
0498             return;
0499         }
0500     }
0501
0502     /*
0503      * Apply this short delay always to ensure that we do wait tWB in
0504      * any case on any machine.
0505      */
0506     ndelay(100);
0507
0508     nand_wait_ready(chip);
0509 }
0510
0511 /**
0512  * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
0513  * @chip: nand chip info structure
0514  * @addr: feature address.
0515  * @subfeature_param: the subfeature parameters, a four bytes array.
0516  *
0517  * Should be used by NAND controller drivers that do not support the SET/GET
0518  * FEATURES operations.
0519  */
0520 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
0521                   u8 *subfeature_param)
0522 {
0523     return -ENOTSUPP;
0524 }
0525 EXPORT_SYMBOL(nand_get_set_features_notsupp);
0526
0527 /**
0528  * nand_wait - [DEFAULT] wait until the command is done
0529  * @chip: NAND chip structure
0530  *
0531  * Wait for command done. This applies to erase and program only.
0532  */
0533 static int nand_wait(struct nand_chip *chip)
0534 {
0535     struct mtd_info *mtd = nand_to_mtd(chip);
0536     unsigned long timeo = 400;
0537     u8 status;
0538     int ret;
0539
0540     /*
0541      * Apply this short delay always to ensure that we do wait tWB in any
0542      * case on any machine.
0543      */
0544     ndelay(100);
0545
0546     ret = nand_status_op(chip, NULL);
0547     if (ret)
0548         return ret;
0549
0550     if (mtd->oops_panic_write) {
0551         panic_nand_wait(chip, timeo);
0552     } else {
0553         timeo = jiffies + msecs_to_jiffies(timeo);
0554         do {
0555             if (chip->legacy.dev_ready) {
0556                 if (chip->legacy.dev_ready(chip))
0557                     break;
0558             } else {
0559                 ret = nand_read_data_op(chip, &status,
0560                             sizeof(status), true,
0561                             false);
0562                 if (ret)
0563                     return ret;
0564
0565                 if (status & NAND_STATUS_READY)
0566                     break;
0567             }
0568             cond_resched();
0569         } while (time_before(jiffies, timeo));
0570     }
0571
0572     ret = nand_read_data_op(chip, &status, sizeof(status), true, false);
0573     if (ret)
0574         return ret;
0575
0576     /* This can happen if in case of timeout or buggy dev_ready */
0577     WARN_ON(!(status & NAND_STATUS_READY));
0578     return status;
0579 }
0580
0581 void nand_legacy_set_defaults(struct nand_chip *chip)
0582 {
0583     unsigned int busw = chip->options & NAND_BUSWIDTH_16;
0584
0585     if (nand_has_exec_op(chip))
0586         return;
0587
0588     /* check for proper chip_delay setup, set 20us if not */
0589     if (!chip->legacy.chip_delay)
0590         chip->legacy.chip_delay = 20;
0591
0592     /* check, if a user supplied command function given */
0593     if (!chip->legacy.cmdfunc)
0594         chip->legacy.cmdfunc = nand_command;
0595
0596     /* check, if a user supplied wait function given */
0597     if (chip->legacy.waitfunc == NULL)
0598         chip->legacy.waitfunc = nand_wait;
0599
0600     if (!chip->legacy.select_chip)
0601         chip->legacy.select_chip = nand_select_chip;
0602
0603     /* If called twice, pointers that depend on busw may need to be reset */
0604     if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
0605         chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
0606     if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
0607         chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
0608     if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
0609         chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
0610     if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
0611         chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
0612 }
0613
0614 void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
0615 {
0616     struct mtd_info *mtd = nand_to_mtd(chip);
0617
0618     /* Do not replace user supplied command function! */
0619     if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
0620         chip->legacy.cmdfunc = nand_command_lp;
0621 }
0622
0623 int nand_legacy_check_hooks(struct nand_chip *chip)
0624 {
0625     /*
0626      * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
0627      * not populated.
0628      */
0629     if (nand_has_exec_op(chip))
0630         return 0;
0631
0632     /*
0633      * Default functions assigned for ->legacy.cmdfunc() and
0634      * ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
0635      *  populated.
0636      */
0637     if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
0638         !chip->legacy.cmd_ctrl) {
0639         pr_err("->legacy.cmd_ctrl() should be provided\n");
0640         return -EINVAL;
0641     }
0642
0643     return 0;
0644 }