nand/raw/nand_amd.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2017 Free Electrons
0004  * Copyright (C) 2017 NextThing Co
0005  *
0006  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
0007  */
0008
0009 #include "internals.h"
0010
0011 static void amd_nand_decode_id(struct nand_chip *chip)
0012 {
0013     struct mtd_info *mtd = nand_to_mtd(chip);
0014     struct nand_memory_organization *memorg;
0015
0016     memorg = nanddev_get_memorg(&chip->base);
0017
0018     nand_decode_ext_id(chip);
0019
0020     /*
0021      * Check for Spansion/AMD ID + repeating 5th, 6th byte since
0022      * some Spansion chips have erasesize that conflicts with size
0023      * listed in nand_ids table.
0024      * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
0025      */
0026     if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 &&
0027         chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 &&
0028         memorg->pagesize == 512) {
0029         memorg->pages_per_eraseblock = 256;
0030         memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1);
0031         mtd->erasesize = memorg->pages_per_eraseblock *
0032                  memorg->pagesize;
0033     }
0034 }
0035
0036 static int amd_nand_init(struct nand_chip *chip)
0037 {
0038     if (nand_is_slc(chip))
0039         /*
0040          * According to the datasheet of some Cypress SLC NANDs,
0041          * the bad block markers can be in the first, second or last
0042          * page of a block. So let's check all three locations.
0043          */
0044         chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE |
0045                  NAND_BBM_LASTPAGE;
0046
0047     return 0;
0048 }
0049
0050 const struct nand_manufacturer_ops amd_nand_manuf_ops = {
0051     .detect = amd_nand_decode_id,
0052     .init = amd_nand_init,
0053 };