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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2019 Macronix International Co., Ltd.
0004  *
0005  * Author:
0006  *  Mason Yang <masonccyang@mxic.com.tw>
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/module.h>
0014 #include <linux/mtd/mtd.h>
0015 #include <linux/mtd/nand-ecc-sw-hamming.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/platform_device.h>
0018 
0019 #include "internals.h"
0020 
0021 #define HC_CFG          0x0
0022 #define HC_CFG_IF_CFG(x)    ((x) << 27)
0023 #define HC_CFG_DUAL_SLAVE   BIT(31)
0024 #define HC_CFG_INDIVIDUAL   BIT(30)
0025 #define HC_CFG_NIO(x)       (((x) / 4) << 27)
0026 #define HC_CFG_TYPE(s, t)   ((t) << (23 + ((s) * 2)))
0027 #define HC_CFG_TYPE_SPI_NOR 0
0028 #define HC_CFG_TYPE_SPI_NAND    1
0029 #define HC_CFG_TYPE_SPI_RAM 2
0030 #define HC_CFG_TYPE_RAW_NAND    3
0031 #define HC_CFG_SLV_ACT(x)   ((x) << 21)
0032 #define HC_CFG_CLK_PH_EN    BIT(20)
0033 #define HC_CFG_CLK_POL_INV  BIT(19)
0034 #define HC_CFG_BIG_ENDIAN   BIT(18)
0035 #define HC_CFG_DATA_PASS    BIT(17)
0036 #define HC_CFG_IDLE_SIO_LVL(x)  ((x) << 16)
0037 #define HC_CFG_MAN_START_EN BIT(3)
0038 #define HC_CFG_MAN_START    BIT(2)
0039 #define HC_CFG_MAN_CS_EN    BIT(1)
0040 #define HC_CFG_MAN_CS_ASSERT    BIT(0)
0041 
0042 #define INT_STS         0x4
0043 #define INT_STS_EN      0x8
0044 #define INT_SIG_EN      0xc
0045 #define INT_STS_ALL     GENMASK(31, 0)
0046 #define INT_RDY_PIN     BIT(26)
0047 #define INT_RDY_SR      BIT(25)
0048 #define INT_LNR_SUSP        BIT(24)
0049 #define INT_ECC_ERR     BIT(17)
0050 #define INT_CRC_ERR     BIT(16)
0051 #define INT_LWR_DIS     BIT(12)
0052 #define INT_LRD_DIS     BIT(11)
0053 #define INT_SDMA_INT        BIT(10)
0054 #define INT_DMA_FINISH      BIT(9)
0055 #define INT_RX_NOT_FULL     BIT(3)
0056 #define INT_RX_NOT_EMPTY    BIT(2)
0057 #define INT_TX_NOT_FULL     BIT(1)
0058 #define INT_TX_EMPTY        BIT(0)
0059 
0060 #define HC_EN           0x10
0061 #define HC_EN_BIT       BIT(0)
0062 
0063 #define TXD(x)          (0x14 + ((x) * 4))
0064 #define RXD         0x24
0065 
0066 #define SS_CTRL(s)      (0x30 + ((s) * 4))
0067 #define LRD_CFG         0x44
0068 #define LWR_CFG         0x80
0069 #define RWW_CFG         0x70
0070 #define OP_READ         BIT(23)
0071 #define OP_DUMMY_CYC(x)     ((x) << 17)
0072 #define OP_ADDR_BYTES(x)    ((x) << 14)
0073 #define OP_CMD_BYTES(x)     (((x) - 1) << 13)
0074 #define OP_OCTA_CRC_EN      BIT(12)
0075 #define OP_DQS_EN       BIT(11)
0076 #define OP_ENHC_EN      BIT(10)
0077 #define OP_PREAMBLE_EN      BIT(9)
0078 #define OP_DATA_DDR     BIT(8)
0079 #define OP_DATA_BUSW(x)     ((x) << 6)
0080 #define OP_ADDR_DDR     BIT(5)
0081 #define OP_ADDR_BUSW(x)     ((x) << 3)
0082 #define OP_CMD_DDR      BIT(2)
0083 #define OP_CMD_BUSW(x)      (x)
0084 #define OP_BUSW_1       0
0085 #define OP_BUSW_2       1
0086 #define OP_BUSW_4       2
0087 #define OP_BUSW_8       3
0088 
0089 #define OCTA_CRC        0x38
0090 #define OCTA_CRC_IN_EN(s)   BIT(3 + ((s) * 16))
0091 #define OCTA_CRC_CHUNK(s, x)    ((fls((x) / 32)) << (1 + ((s) * 16)))
0092 #define OCTA_CRC_OUT_EN(s)  BIT(0 + ((s) * 16))
0093 
0094 #define ONFI_DIN_CNT(s)     (0x3c + (s))
0095 
0096 #define LRD_CTRL        0x48
0097 #define RWW_CTRL        0x74
0098 #define LWR_CTRL        0x84
0099 #define LMODE_EN        BIT(31)
0100 #define LMODE_SLV_ACT(x)    ((x) << 21)
0101 #define LMODE_CMD1(x)       ((x) << 8)
0102 #define LMODE_CMD0(x)       (x)
0103 
0104 #define LRD_ADDR        0x4c
0105 #define LWR_ADDR        0x88
0106 #define LRD_RANGE       0x50
0107 #define LWR_RANGE       0x8c
0108 
0109 #define AXI_SLV_ADDR        0x54
0110 
0111 #define DMAC_RD_CFG     0x58
0112 #define DMAC_WR_CFG     0x94
0113 #define DMAC_CFG_PERIPH_EN  BIT(31)
0114 #define DMAC_CFG_ALLFLUSH_EN    BIT(30)
0115 #define DMAC_CFG_LASTFLUSH_EN   BIT(29)
0116 #define DMAC_CFG_QE(x)      (((x) + 1) << 16)
0117 #define DMAC_CFG_BURST_LEN(x)   (((x) + 1) << 12)
0118 #define DMAC_CFG_BURST_SZ(x)    ((x) << 8)
0119 #define DMAC_CFG_DIR_READ   BIT(1)
0120 #define DMAC_CFG_START      BIT(0)
0121 
0122 #define DMAC_RD_CNT     0x5c
0123 #define DMAC_WR_CNT     0x98
0124 
0125 #define SDMA_ADDR       0x60
0126 
0127 #define DMAM_CFG        0x64
0128 #define DMAM_CFG_START      BIT(31)
0129 #define DMAM_CFG_CONT       BIT(30)
0130 #define DMAM_CFG_SDMA_GAP(x)    (fls((x) / 8192) << 2)
0131 #define DMAM_CFG_DIR_READ   BIT(1)
0132 #define DMAM_CFG_EN     BIT(0)
0133 
0134 #define DMAM_CNT        0x68
0135 
0136 #define LNR_TIMER_TH        0x6c
0137 
0138 #define RDM_CFG0        0x78
0139 #define RDM_CFG0_POLY(x)    (x)
0140 
0141 #define RDM_CFG1        0x7c
0142 #define RDM_CFG1_RDM_EN     BIT(31)
0143 #define RDM_CFG1_SEED(x)    (x)
0144 
0145 #define LWR_SUSP_CTRL       0x90
0146 #define LWR_SUSP_CTRL_EN    BIT(31)
0147 
0148 #define DMAS_CTRL       0x9c
0149 #define DMAS_CTRL_EN        BIT(31)
0150 #define DMAS_CTRL_DIR_READ  BIT(30)
0151 
0152 #define DATA_STROB      0xa0
0153 #define DATA_STROB_EDO_EN   BIT(2)
0154 #define DATA_STROB_INV_POL  BIT(1)
0155 #define DATA_STROB_DELAY_2CYC   BIT(0)
0156 
0157 #define IDLY_CODE(x)        (0xa4 + ((x) * 4))
0158 #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
0159 
0160 #define GPIO            0xc4
0161 #define GPIO_PT(x)      BIT(3 + ((x) * 16))
0162 #define GPIO_RESET(x)       BIT(2 + ((x) * 16))
0163 #define GPIO_HOLDB(x)       BIT(1 + ((x) * 16))
0164 #define GPIO_WPB(x)     BIT((x) * 16)
0165 
0166 #define HC_VER          0xd0
0167 
0168 #define HW_TEST(x)      (0xe0 + ((x) * 4))
0169 
0170 #define MXIC_NFC_MAX_CLK_HZ 50000000
0171 #define IRQ_TIMEOUT     1000
0172 
0173 struct mxic_nand_ctlr {
0174     struct clk *ps_clk;
0175     struct clk *send_clk;
0176     struct clk *send_dly_clk;
0177     struct completion complete;
0178     void __iomem *regs;
0179     struct nand_controller controller;
0180     struct device *dev;
0181     struct nand_chip chip;
0182 };
0183 
0184 static int mxic_nfc_clk_enable(struct mxic_nand_ctlr *nfc)
0185 {
0186     int ret;
0187 
0188     ret = clk_prepare_enable(nfc->ps_clk);
0189     if (ret)
0190         return ret;
0191 
0192     ret = clk_prepare_enable(nfc->send_clk);
0193     if (ret)
0194         goto err_ps_clk;
0195 
0196     ret = clk_prepare_enable(nfc->send_dly_clk);
0197     if (ret)
0198         goto err_send_dly_clk;
0199 
0200     return ret;
0201 
0202 err_send_dly_clk:
0203     clk_disable_unprepare(nfc->send_clk);
0204 err_ps_clk:
0205     clk_disable_unprepare(nfc->ps_clk);
0206 
0207     return ret;
0208 }
0209 
0210 static void mxic_nfc_clk_disable(struct mxic_nand_ctlr *nfc)
0211 {
0212     clk_disable_unprepare(nfc->send_clk);
0213     clk_disable_unprepare(nfc->send_dly_clk);
0214     clk_disable_unprepare(nfc->ps_clk);
0215 }
0216 
0217 static void mxic_nfc_set_input_delay(struct mxic_nand_ctlr *nfc, u8 idly_code)
0218 {
0219     writel(IDLY_CODE_VAL(0, idly_code) |
0220            IDLY_CODE_VAL(1, idly_code) |
0221            IDLY_CODE_VAL(2, idly_code) |
0222            IDLY_CODE_VAL(3, idly_code),
0223            nfc->regs + IDLY_CODE(0));
0224     writel(IDLY_CODE_VAL(4, idly_code) |
0225            IDLY_CODE_VAL(5, idly_code) |
0226            IDLY_CODE_VAL(6, idly_code) |
0227            IDLY_CODE_VAL(7, idly_code),
0228            nfc->regs + IDLY_CODE(1));
0229 }
0230 
0231 static int mxic_nfc_clk_setup(struct mxic_nand_ctlr *nfc, unsigned long freq)
0232 {
0233     int ret;
0234 
0235     ret = clk_set_rate(nfc->send_clk, freq);
0236     if (ret)
0237         return ret;
0238 
0239     ret = clk_set_rate(nfc->send_dly_clk, freq);
0240     if (ret)
0241         return ret;
0242 
0243     /*
0244      * A constant delay range from 0x0 ~ 0x1F for input delay,
0245      * the unit is 78 ps, the max input delay is 2.418 ns.
0246      */
0247     mxic_nfc_set_input_delay(nfc, 0xf);
0248 
0249     /*
0250      * Phase degree = 360 * freq * output-delay
0251      * where output-delay is a constant value 1 ns in FPGA.
0252      *
0253      * Get Phase degree = 360 * freq * 1 ns
0254      *                  = 360 * freq * 1 sec / 1000000000
0255      *                  = 9 * freq / 25000000
0256      */
0257     ret = clk_set_phase(nfc->send_dly_clk, 9 * freq / 25000000);
0258     if (ret)
0259         return ret;
0260 
0261     return 0;
0262 }
0263 
0264 static int mxic_nfc_set_freq(struct mxic_nand_ctlr *nfc, unsigned long freq)
0265 {
0266     int ret;
0267 
0268     if (freq > MXIC_NFC_MAX_CLK_HZ)
0269         freq = MXIC_NFC_MAX_CLK_HZ;
0270 
0271     mxic_nfc_clk_disable(nfc);
0272     ret = mxic_nfc_clk_setup(nfc, freq);
0273     if (ret)
0274         return ret;
0275 
0276     ret = mxic_nfc_clk_enable(nfc);
0277     if (ret)
0278         return ret;
0279 
0280     return 0;
0281 }
0282 
0283 static irqreturn_t mxic_nfc_isr(int irq, void *dev_id)
0284 {
0285     struct mxic_nand_ctlr *nfc = dev_id;
0286     u32 sts;
0287 
0288     sts = readl(nfc->regs + INT_STS);
0289     if (sts & INT_RDY_PIN)
0290         complete(&nfc->complete);
0291     else
0292         return IRQ_NONE;
0293 
0294     return IRQ_HANDLED;
0295 }
0296 
0297 static void mxic_nfc_hw_init(struct mxic_nand_ctlr *nfc)
0298 {
0299     writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
0300            HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
0301            HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
0302     writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
0303     writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
0304     writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
0305     writel(0, nfc->regs + LRD_CFG);
0306     writel(0, nfc->regs + LRD_CTRL);
0307     writel(0x0, nfc->regs + HC_EN);
0308 }
0309 
0310 static void mxic_nfc_cs_enable(struct mxic_nand_ctlr *nfc)
0311 {
0312     writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
0313            nfc->regs + HC_CFG);
0314     writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
0315            nfc->regs + HC_CFG);
0316 }
0317 
0318 static void mxic_nfc_cs_disable(struct mxic_nand_ctlr *nfc)
0319 {
0320     writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
0321            nfc->regs + HC_CFG);
0322 }
0323 
0324 static int  mxic_nfc_wait_ready(struct nand_chip *chip)
0325 {
0326     struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
0327     int ret;
0328 
0329     ret = wait_for_completion_timeout(&nfc->complete,
0330                       msecs_to_jiffies(IRQ_TIMEOUT));
0331     if (!ret) {
0332         dev_err(nfc->dev, "nand device timeout\n");
0333         return -ETIMEDOUT;
0334     }
0335 
0336     return 0;
0337 }
0338 
0339 static int mxic_nfc_data_xfer(struct mxic_nand_ctlr *nfc, const void *txbuf,
0340                   void *rxbuf, unsigned int len)
0341 {
0342     unsigned int pos = 0;
0343 
0344     while (pos < len) {
0345         unsigned int nbytes = len - pos;
0346         u32 data = 0xffffffff;
0347         u32 sts;
0348         int ret;
0349 
0350         if (nbytes > 4)
0351             nbytes = 4;
0352 
0353         if (txbuf)
0354             memcpy(&data, txbuf + pos, nbytes);
0355 
0356         ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
0357                      sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
0358         if (ret)
0359             return ret;
0360 
0361         writel(data, nfc->regs + TXD(nbytes % 4));
0362 
0363         ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
0364                      sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
0365         if (ret)
0366             return ret;
0367 
0368         ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
0369                      sts & INT_RX_NOT_EMPTY, 0,
0370                      USEC_PER_SEC);
0371         if (ret)
0372             return ret;
0373 
0374         data = readl(nfc->regs + RXD);
0375         if (rxbuf) {
0376             data >>= (8 * (4 - nbytes));
0377             memcpy(rxbuf + pos, &data, nbytes);
0378         }
0379         if (readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY)
0380             dev_warn(nfc->dev, "RX FIFO not empty\n");
0381 
0382         pos += nbytes;
0383     }
0384 
0385     return 0;
0386 }
0387 
0388 static int mxic_nfc_exec_op(struct nand_chip *chip,
0389                 const struct nand_operation *op, bool check_only)
0390 {
0391     struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
0392     const struct nand_op_instr *instr = NULL;
0393     int ret = 0;
0394     unsigned int op_id;
0395 
0396     if (check_only)
0397         return 0;
0398 
0399     mxic_nfc_cs_enable(nfc);
0400     init_completion(&nfc->complete);
0401     for (op_id = 0; op_id < op->ninstrs; op_id++) {
0402         instr = &op->instrs[op_id];
0403 
0404         switch (instr->type) {
0405         case NAND_OP_CMD_INSTR:
0406             writel(0, nfc->regs + HC_EN);
0407             writel(HC_EN_BIT, nfc->regs + HC_EN);
0408             writel(OP_CMD_BUSW(OP_BUSW_8) |  OP_DUMMY_CYC(0x3F) |
0409                    OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
0410 
0411             ret = mxic_nfc_data_xfer(nfc,
0412                          &instr->ctx.cmd.opcode,
0413                          NULL, 1);
0414             break;
0415 
0416         case NAND_OP_ADDR_INSTR:
0417             writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
0418                    OP_ADDR_BYTES(instr->ctx.addr.naddrs),
0419                    nfc->regs + SS_CTRL(0));
0420             ret = mxic_nfc_data_xfer(nfc,
0421                          instr->ctx.addr.addrs, NULL,
0422                          instr->ctx.addr.naddrs);
0423             break;
0424 
0425         case NAND_OP_DATA_IN_INSTR:
0426             writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
0427             writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
0428                    OP_READ, nfc->regs + SS_CTRL(0));
0429             ret = mxic_nfc_data_xfer(nfc, NULL,
0430                          instr->ctx.data.buf.in,
0431                          instr->ctx.data.len);
0432             break;
0433 
0434         case NAND_OP_DATA_OUT_INSTR:
0435             writel(instr->ctx.data.len,
0436                    nfc->regs + ONFI_DIN_CNT(0));
0437             writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
0438                    nfc->regs + SS_CTRL(0));
0439             ret = mxic_nfc_data_xfer(nfc,
0440                          instr->ctx.data.buf.out, NULL,
0441                          instr->ctx.data.len);
0442             break;
0443 
0444         case NAND_OP_WAITRDY_INSTR:
0445             ret = mxic_nfc_wait_ready(chip);
0446             break;
0447         }
0448     }
0449     mxic_nfc_cs_disable(nfc);
0450 
0451     return ret;
0452 }
0453 
0454 static int mxic_nfc_setup_interface(struct nand_chip *chip, int chipnr,
0455                     const struct nand_interface_config *conf)
0456 {
0457     struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
0458     const struct nand_sdr_timings *sdr;
0459     unsigned long freq;
0460     int ret;
0461 
0462     sdr = nand_get_sdr_timings(conf);
0463     if (IS_ERR(sdr))
0464         return PTR_ERR(sdr);
0465 
0466     if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
0467         return 0;
0468 
0469     freq = NSEC_PER_SEC / (sdr->tRC_min / 1000);
0470 
0471     ret =  mxic_nfc_set_freq(nfc, freq);
0472     if (ret)
0473         dev_err(nfc->dev, "set freq:%ld failed\n", freq);
0474 
0475     if (sdr->tRC_min < 30000)
0476         writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
0477 
0478     return 0;
0479 }
0480 
0481 static const struct nand_controller_ops mxic_nand_controller_ops = {
0482     .exec_op = mxic_nfc_exec_op,
0483     .setup_interface = mxic_nfc_setup_interface,
0484 };
0485 
0486 static int mxic_nfc_probe(struct platform_device *pdev)
0487 {
0488     struct device_node *nand_np, *np = pdev->dev.of_node;
0489     struct mtd_info *mtd;
0490     struct mxic_nand_ctlr *nfc;
0491     struct nand_chip *nand_chip;
0492     int err;
0493     int irq;
0494 
0495     nfc = devm_kzalloc(&pdev->dev, sizeof(struct mxic_nand_ctlr),
0496                GFP_KERNEL);
0497     if (!nfc)
0498         return -ENOMEM;
0499 
0500     nfc->ps_clk = devm_clk_get(&pdev->dev, "ps");
0501     if (IS_ERR(nfc->ps_clk))
0502         return PTR_ERR(nfc->ps_clk);
0503 
0504     nfc->send_clk = devm_clk_get(&pdev->dev, "send");
0505     if (IS_ERR(nfc->send_clk))
0506         return PTR_ERR(nfc->send_clk);
0507 
0508     nfc->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly");
0509     if (IS_ERR(nfc->send_dly_clk))
0510         return PTR_ERR(nfc->send_dly_clk);
0511 
0512     nfc->regs = devm_platform_ioremap_resource(pdev, 0);
0513     if (IS_ERR(nfc->regs))
0514         return PTR_ERR(nfc->regs);
0515 
0516     nand_chip = &nfc->chip;
0517     mtd = nand_to_mtd(nand_chip);
0518     mtd->dev.parent = &pdev->dev;
0519 
0520     for_each_child_of_node(np, nand_np)
0521         nand_set_flash_node(nand_chip, nand_np);
0522 
0523     nand_chip->priv = nfc;
0524     nfc->dev = &pdev->dev;
0525     nfc->controller.ops = &mxic_nand_controller_ops;
0526     nand_controller_init(&nfc->controller);
0527     nand_chip->controller = &nfc->controller;
0528 
0529     irq = platform_get_irq(pdev, 0);
0530     if (irq < 0)
0531         return irq;
0532 
0533     mxic_nfc_hw_init(nfc);
0534 
0535     err = devm_request_irq(&pdev->dev, irq, mxic_nfc_isr,
0536                    0, "mxic-nfc", nfc);
0537     if (err)
0538         goto fail;
0539 
0540     err = nand_scan(nand_chip, 1);
0541     if (err)
0542         goto fail;
0543 
0544     err = mtd_device_register(mtd, NULL, 0);
0545     if (err)
0546         goto fail;
0547 
0548     platform_set_drvdata(pdev, nfc);
0549     return 0;
0550 
0551 fail:
0552     mxic_nfc_clk_disable(nfc);
0553     return err;
0554 }
0555 
0556 static int mxic_nfc_remove(struct platform_device *pdev)
0557 {
0558     struct mxic_nand_ctlr *nfc = platform_get_drvdata(pdev);
0559     struct nand_chip *chip = &nfc->chip;
0560     int ret;
0561 
0562     ret = mtd_device_unregister(nand_to_mtd(chip));
0563     WARN_ON(ret);
0564     nand_cleanup(chip);
0565 
0566     mxic_nfc_clk_disable(nfc);
0567     return 0;
0568 }
0569 
0570 static const struct of_device_id mxic_nfc_of_ids[] = {
0571     { .compatible = "mxic,multi-itfc-v009-nand-controller", },
0572     {},
0573 };
0574 MODULE_DEVICE_TABLE(of, mxic_nfc_of_ids);
0575 
0576 static struct platform_driver mxic_nfc_driver = {
0577     .probe = mxic_nfc_probe,
0578     .remove = mxic_nfc_remove,
0579     .driver = {
0580         .name = "mxic-nfc",
0581         .of_match_table = mxic_nfc_of_ids,
0582     },
0583 };
0584 module_platform_driver(mxic_nfc_driver);
0585 
0586 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
0587 MODULE_DESCRIPTION("Macronix raw NAND controller driver");
0588 MODULE_LICENSE("GPL v2");
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