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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0004  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
0005  */
0006 
0007 #include <linux/delay.h>
0008 #include <linux/slab.h>
0009 #include <linux/init.h>
0010 #include <linux/module.h>
0011 #include <linux/mtd/mtd.h>
0012 #include <linux/mtd/rawnand.h>
0013 #include <linux/mtd/partitions.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/clk.h>
0018 #include <linux/err.h>
0019 #include <linux/io.h>
0020 #include <linux/irq.h>
0021 #include <linux/completion.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 
0025 #define DRIVER_NAME "mxc_nand"
0026 
0027 /* Addresses for NFC registers */
0028 #define NFC_V1_V2_BUF_SIZE      (host->regs + 0x00)
0029 #define NFC_V1_V2_BUF_ADDR      (host->regs + 0x04)
0030 #define NFC_V1_V2_FLASH_ADDR        (host->regs + 0x06)
0031 #define NFC_V1_V2_FLASH_CMD     (host->regs + 0x08)
0032 #define NFC_V1_V2_CONFIG        (host->regs + 0x0a)
0033 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
0034 #define NFC_V1_V2_RSLTMAIN_AREA     (host->regs + 0x0e)
0035 #define NFC_V21_RSLTSPARE_AREA      (host->regs + 0x10)
0036 #define NFC_V1_V2_WRPROT        (host->regs + 0x12)
0037 #define NFC_V1_UNLOCKSTART_BLKADDR  (host->regs + 0x14)
0038 #define NFC_V1_UNLOCKEND_BLKADDR    (host->regs + 0x16)
0039 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
0040 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
0041 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
0042 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
0043 #define NFC_V21_UNLOCKEND_BLKADDR0  (host->regs + 0x22)
0044 #define NFC_V21_UNLOCKEND_BLKADDR1  (host->regs + 0x26)
0045 #define NFC_V21_UNLOCKEND_BLKADDR2  (host->regs + 0x2a)
0046 #define NFC_V21_UNLOCKEND_BLKADDR3  (host->regs + 0x2e)
0047 #define NFC_V1_V2_NF_WRPRST     (host->regs + 0x18)
0048 #define NFC_V1_V2_CONFIG1       (host->regs + 0x1a)
0049 #define NFC_V1_V2_CONFIG2       (host->regs + 0x1c)
0050 
0051 #define NFC_V2_CONFIG1_ECC_MODE_4   (1 << 0)
0052 #define NFC_V1_V2_CONFIG1_SP_EN     (1 << 2)
0053 #define NFC_V1_V2_CONFIG1_ECC_EN    (1 << 3)
0054 #define NFC_V1_V2_CONFIG1_INT_MSK   (1 << 4)
0055 #define NFC_V1_V2_CONFIG1_BIG       (1 << 5)
0056 #define NFC_V1_V2_CONFIG1_RST       (1 << 6)
0057 #define NFC_V1_V2_CONFIG1_CE        (1 << 7)
0058 #define NFC_V2_CONFIG1_ONE_CYCLE    (1 << 8)
0059 #define NFC_V2_CONFIG1_PPB(x)       (((x) & 0x3) << 9)
0060 #define NFC_V2_CONFIG1_FP_INT       (1 << 11)
0061 
0062 #define NFC_V1_V2_CONFIG2_INT       (1 << 15)
0063 
0064 /*
0065  * Operation modes for the NFC. Valid for v1, v2 and v3
0066  * type controllers.
0067  */
0068 #define NFC_CMD             (1 << 0)
0069 #define NFC_ADDR            (1 << 1)
0070 #define NFC_INPUT           (1 << 2)
0071 #define NFC_OUTPUT          (1 << 3)
0072 #define NFC_ID              (1 << 4)
0073 #define NFC_STATUS          (1 << 5)
0074 
0075 #define NFC_V3_FLASH_CMD        (host->regs_axi + 0x00)
0076 #define NFC_V3_FLASH_ADDR0      (host->regs_axi + 0x04)
0077 
0078 #define NFC_V3_CONFIG1          (host->regs_axi + 0x34)
0079 #define NFC_V3_CONFIG1_SP_EN        (1 << 0)
0080 #define NFC_V3_CONFIG1_RBA(x)       (((x) & 0x7 ) << 4)
0081 
0082 #define NFC_V3_ECC_STATUS_RESULT    (host->regs_axi + 0x38)
0083 
0084 #define NFC_V3_LAUNCH           (host->regs_axi + 0x40)
0085 
0086 #define NFC_V3_WRPROT           (host->regs_ip + 0x0)
0087 #define NFC_V3_WRPROT_LOCK_TIGHT    (1 << 0)
0088 #define NFC_V3_WRPROT_LOCK      (1 << 1)
0089 #define NFC_V3_WRPROT_UNLOCK        (1 << 2)
0090 #define NFC_V3_WRPROT_BLS_UNLOCK    (2 << 6)
0091 
0092 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
0093 
0094 #define NFC_V3_CONFIG2          (host->regs_ip + 0x24)
0095 #define NFC_V3_CONFIG2_PS_512           (0 << 0)
0096 #define NFC_V3_CONFIG2_PS_2048          (1 << 0)
0097 #define NFC_V3_CONFIG2_PS_4096          (2 << 0)
0098 #define NFC_V3_CONFIG2_ONE_CYCLE        (1 << 2)
0099 #define NFC_V3_CONFIG2_ECC_EN           (1 << 3)
0100 #define NFC_V3_CONFIG2_2CMD_PHASES      (1 << 4)
0101 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0      (1 << 5)
0102 #define NFC_V3_CONFIG2_ECC_MODE_8       (1 << 6)
0103 #define NFC_V3_CONFIG2_PPB(x, shift)        (((x) & 0x3) << shift)
0104 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)   (((x) & 0x3) << 12)
0105 #define NFC_V3_CONFIG2_INT_MSK          (1 << 15)
0106 #define NFC_V3_CONFIG2_ST_CMD(x)        (((x) & 0xff) << 24)
0107 #define NFC_V3_CONFIG2_SPAS(x)          (((x) & 0xff) << 16)
0108 
0109 #define NFC_V3_CONFIG3              (host->regs_ip + 0x28)
0110 #define NFC_V3_CONFIG3_ADD_OP(x)        (((x) & 0x3) << 0)
0111 #define NFC_V3_CONFIG3_FW8          (1 << 3)
0112 #define NFC_V3_CONFIG3_SBB(x)           (((x) & 0x7) << 8)
0113 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)    (((x) & 0x7) << 12)
0114 #define NFC_V3_CONFIG3_RBB_MODE         (1 << 15)
0115 #define NFC_V3_CONFIG3_NO_SDMA          (1 << 20)
0116 
0117 #define NFC_V3_IPC          (host->regs_ip + 0x2C)
0118 #define NFC_V3_IPC_CREQ         (1 << 0)
0119 #define NFC_V3_IPC_INT          (1 << 31)
0120 
0121 #define NFC_V3_DELAY_LINE       (host->regs_ip + 0x34)
0122 
0123 struct mxc_nand_host;
0124 
0125 struct mxc_nand_devtype_data {
0126     void (*preset)(struct mtd_info *);
0127     int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
0128              int page);
0129     void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
0130     void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
0131     void (*send_page)(struct mtd_info *, unsigned int);
0132     void (*send_read_id)(struct mxc_nand_host *);
0133     uint16_t (*get_dev_status)(struct mxc_nand_host *);
0134     int (*check_int)(struct mxc_nand_host *);
0135     void (*irq_control)(struct mxc_nand_host *, int);
0136     u32 (*get_ecc_status)(struct mxc_nand_host *);
0137     const struct mtd_ooblayout_ops *ooblayout;
0138     void (*select_chip)(struct nand_chip *chip, int cs);
0139     int (*setup_interface)(struct nand_chip *chip, int csline,
0140                    const struct nand_interface_config *conf);
0141     void (*enable_hwecc)(struct nand_chip *chip, bool enable);
0142 
0143     /*
0144      * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
0145      * (CONFIG1:INT_MSK is set). To handle this the driver uses
0146      * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
0147      */
0148     int irqpending_quirk;
0149     int needs_ip;
0150 
0151     size_t regs_offset;
0152     size_t spare0_offset;
0153     size_t axi_offset;
0154 
0155     int spare_len;
0156     int eccbytes;
0157     int eccsize;
0158     int ppb_shift;
0159 };
0160 
0161 struct mxc_nand_host {
0162     struct nand_chip    nand;
0163     struct device       *dev;
0164 
0165     void __iomem        *spare0;
0166     void __iomem        *main_area0;
0167 
0168     void __iomem        *base;
0169     void __iomem        *regs;
0170     void __iomem        *regs_axi;
0171     void __iomem        *regs_ip;
0172     int         status_request;
0173     struct clk      *clk;
0174     int         clk_act;
0175     int         irq;
0176     int         eccsize;
0177     int         used_oobsize;
0178     int         active_cs;
0179 
0180     struct completion   op_completion;
0181 
0182     uint8_t         *data_buf;
0183     unsigned int        buf_start;
0184 
0185     const struct mxc_nand_devtype_data *devtype_data;
0186 };
0187 
0188 static const char * const part_probes[] = {
0189     "cmdlinepart", "RedBoot", "ofpart", NULL };
0190 
0191 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
0192 {
0193     int i;
0194     u32 *t = trg;
0195     const __iomem u32 *s = src;
0196 
0197     for (i = 0; i < (size >> 2); i++)
0198         *t++ = __raw_readl(s++);
0199 }
0200 
0201 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
0202 {
0203     int i;
0204     u16 *t = trg;
0205     const __iomem u16 *s = src;
0206 
0207     /* We assume that src (IO) is always 32bit aligned */
0208     if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
0209         memcpy32_fromio(trg, src, size);
0210         return;
0211     }
0212 
0213     for (i = 0; i < (size >> 1); i++)
0214         *t++ = __raw_readw(s++);
0215 }
0216 
0217 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
0218 {
0219     /* __iowrite32_copy use 32bit size values so divide by 4 */
0220     __iowrite32_copy(trg, src, size / 4);
0221 }
0222 
0223 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
0224 {
0225     int i;
0226     __iomem u16 *t = trg;
0227     const u16 *s = src;
0228 
0229     /* We assume that trg (IO) is always 32bit aligned */
0230     if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
0231         memcpy32_toio(trg, src, size);
0232         return;
0233     }
0234 
0235     for (i = 0; i < (size >> 1); i++)
0236         __raw_writew(*s++, t++);
0237 }
0238 
0239 /*
0240  * The controller splits a page into data chunks of 512 bytes + partial oob.
0241  * There are writesize / 512 such chunks, the size of the partial oob parts is
0242  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
0243  * contains additionally the byte lost by rounding (if any).
0244  * This function handles the needed shuffling between host->data_buf (which
0245  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
0246  * spare) and the NFC buffer.
0247  */
0248 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
0249 {
0250     struct nand_chip *this = mtd_to_nand(mtd);
0251     struct mxc_nand_host *host = nand_get_controller_data(this);
0252     u16 i, oob_chunk_size;
0253     u16 num_chunks = mtd->writesize / 512;
0254 
0255     u8 *d = buf;
0256     u8 __iomem *s = host->spare0;
0257     u16 sparebuf_size = host->devtype_data->spare_len;
0258 
0259     /* size of oob chunk for all but possibly the last one */
0260     oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
0261 
0262     if (bfrom) {
0263         for (i = 0; i < num_chunks - 1; i++)
0264             memcpy16_fromio(d + i * oob_chunk_size,
0265                     s + i * sparebuf_size,
0266                     oob_chunk_size);
0267 
0268         /* the last chunk */
0269         memcpy16_fromio(d + i * oob_chunk_size,
0270                 s + i * sparebuf_size,
0271                 host->used_oobsize - i * oob_chunk_size);
0272     } else {
0273         for (i = 0; i < num_chunks - 1; i++)
0274             memcpy16_toio(&s[i * sparebuf_size],
0275                       &d[i * oob_chunk_size],
0276                       oob_chunk_size);
0277 
0278         /* the last chunk */
0279         memcpy16_toio(&s[i * sparebuf_size],
0280                   &d[i * oob_chunk_size],
0281                   host->used_oobsize - i * oob_chunk_size);
0282     }
0283 }
0284 
0285 /*
0286  * MXC NANDFC can only perform full page+spare or spare-only read/write.  When
0287  * the upper layers perform a read/write buf operation, the saved column address
0288  * is used to index into the full page. So usually this function is called with
0289  * column == 0 (unless no column cycle is needed indicated by column == -1)
0290  */
0291 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
0292 {
0293     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0294     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0295 
0296     /* Write out column address, if necessary */
0297     if (column != -1) {
0298         host->devtype_data->send_addr(host, column & 0xff,
0299                           page_addr == -1);
0300         if (mtd->writesize > 512)
0301             /* another col addr cycle for 2k page */
0302             host->devtype_data->send_addr(host,
0303                               (column >> 8) & 0xff,
0304                               false);
0305     }
0306 
0307     /* Write out page address, if necessary */
0308     if (page_addr != -1) {
0309         /* paddr_0 - p_addr_7 */
0310         host->devtype_data->send_addr(host, (page_addr & 0xff), false);
0311 
0312         if (mtd->writesize > 512) {
0313             if (mtd->size >= 0x10000000) {
0314                 /* paddr_8 - paddr_15 */
0315                 host->devtype_data->send_addr(host,
0316                         (page_addr >> 8) & 0xff,
0317                         false);
0318                 host->devtype_data->send_addr(host,
0319                         (page_addr >> 16) & 0xff,
0320                         true);
0321             } else
0322                 /* paddr_8 - paddr_15 */
0323                 host->devtype_data->send_addr(host,
0324                         (page_addr >> 8) & 0xff, true);
0325         } else {
0326             if (nand_chip->options & NAND_ROW_ADDR_3) {
0327                 /* paddr_8 - paddr_15 */
0328                 host->devtype_data->send_addr(host,
0329                         (page_addr >> 8) & 0xff,
0330                         false);
0331                 host->devtype_data->send_addr(host,
0332                         (page_addr >> 16) & 0xff,
0333                         true);
0334             } else
0335                 /* paddr_8 - paddr_15 */
0336                 host->devtype_data->send_addr(host,
0337                         (page_addr >> 8) & 0xff, true);
0338         }
0339     }
0340 }
0341 
0342 static int check_int_v3(struct mxc_nand_host *host)
0343 {
0344     uint32_t tmp;
0345 
0346     tmp = readl(NFC_V3_IPC);
0347     if (!(tmp & NFC_V3_IPC_INT))
0348         return 0;
0349 
0350     tmp &= ~NFC_V3_IPC_INT;
0351     writel(tmp, NFC_V3_IPC);
0352 
0353     return 1;
0354 }
0355 
0356 static int check_int_v1_v2(struct mxc_nand_host *host)
0357 {
0358     uint32_t tmp;
0359 
0360     tmp = readw(NFC_V1_V2_CONFIG2);
0361     if (!(tmp & NFC_V1_V2_CONFIG2_INT))
0362         return 0;
0363 
0364     if (!host->devtype_data->irqpending_quirk)
0365         writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
0366 
0367     return 1;
0368 }
0369 
0370 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
0371 {
0372     uint16_t tmp;
0373 
0374     tmp = readw(NFC_V1_V2_CONFIG1);
0375 
0376     if (activate)
0377         tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
0378     else
0379         tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
0380 
0381     writew(tmp, NFC_V1_V2_CONFIG1);
0382 }
0383 
0384 static void irq_control_v3(struct mxc_nand_host *host, int activate)
0385 {
0386     uint32_t tmp;
0387 
0388     tmp = readl(NFC_V3_CONFIG2);
0389 
0390     if (activate)
0391         tmp &= ~NFC_V3_CONFIG2_INT_MSK;
0392     else
0393         tmp |= NFC_V3_CONFIG2_INT_MSK;
0394 
0395     writel(tmp, NFC_V3_CONFIG2);
0396 }
0397 
0398 static void irq_control(struct mxc_nand_host *host, int activate)
0399 {
0400     if (host->devtype_data->irqpending_quirk) {
0401         if (activate)
0402             enable_irq(host->irq);
0403         else
0404             disable_irq_nosync(host->irq);
0405     } else {
0406         host->devtype_data->irq_control(host, activate);
0407     }
0408 }
0409 
0410 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
0411 {
0412     return readw(NFC_V1_V2_ECC_STATUS_RESULT);
0413 }
0414 
0415 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
0416 {
0417     return readl(NFC_V1_V2_ECC_STATUS_RESULT);
0418 }
0419 
0420 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
0421 {
0422     return readl(NFC_V3_ECC_STATUS_RESULT);
0423 }
0424 
0425 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
0426 {
0427     struct mxc_nand_host *host = dev_id;
0428 
0429     if (!host->devtype_data->check_int(host))
0430         return IRQ_NONE;
0431 
0432     irq_control(host, 0);
0433 
0434     complete(&host->op_completion);
0435 
0436     return IRQ_HANDLED;
0437 }
0438 
0439 /* This function polls the NANDFC to wait for the basic operation to
0440  * complete by checking the INT bit of config2 register.
0441  */
0442 static int wait_op_done(struct mxc_nand_host *host, int useirq)
0443 {
0444     int ret = 0;
0445 
0446     /*
0447      * If operation is already complete, don't bother to setup an irq or a
0448      * loop.
0449      */
0450     if (host->devtype_data->check_int(host))
0451         return 0;
0452 
0453     if (useirq) {
0454         unsigned long timeout;
0455 
0456         reinit_completion(&host->op_completion);
0457 
0458         irq_control(host, 1);
0459 
0460         timeout = wait_for_completion_timeout(&host->op_completion, HZ);
0461         if (!timeout && !host->devtype_data->check_int(host)) {
0462             dev_dbg(host->dev, "timeout waiting for irq\n");
0463             ret = -ETIMEDOUT;
0464         }
0465     } else {
0466         int max_retries = 8000;
0467         int done;
0468 
0469         do {
0470             udelay(1);
0471 
0472             done = host->devtype_data->check_int(host);
0473             if (done)
0474                 break;
0475 
0476         } while (--max_retries);
0477 
0478         if (!done) {
0479             dev_dbg(host->dev, "timeout polling for completion\n");
0480             ret = -ETIMEDOUT;
0481         }
0482     }
0483 
0484     WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
0485 
0486     return ret;
0487 }
0488 
0489 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
0490 {
0491     /* fill command */
0492     writel(cmd, NFC_V3_FLASH_CMD);
0493 
0494     /* send out command */
0495     writel(NFC_CMD, NFC_V3_LAUNCH);
0496 
0497     /* Wait for operation to complete */
0498     wait_op_done(host, useirq);
0499 }
0500 
0501 /* This function issues the specified command to the NAND device and
0502  * waits for completion. */
0503 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
0504 {
0505     dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
0506 
0507     writew(cmd, NFC_V1_V2_FLASH_CMD);
0508     writew(NFC_CMD, NFC_V1_V2_CONFIG2);
0509 
0510     if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
0511         int max_retries = 100;
0512         /* Reset completion is indicated by NFC_CONFIG2 */
0513         /* being set to 0 */
0514         while (max_retries-- > 0) {
0515             if (readw(NFC_V1_V2_CONFIG2) == 0) {
0516                 break;
0517             }
0518             udelay(1);
0519         }
0520         if (max_retries < 0)
0521             dev_dbg(host->dev, "%s: RESET failed\n", __func__);
0522     } else {
0523         /* Wait for operation to complete */
0524         wait_op_done(host, useirq);
0525     }
0526 }
0527 
0528 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
0529 {
0530     /* fill address */
0531     writel(addr, NFC_V3_FLASH_ADDR0);
0532 
0533     /* send out address */
0534     writel(NFC_ADDR, NFC_V3_LAUNCH);
0535 
0536     wait_op_done(host, 0);
0537 }
0538 
0539 /* This function sends an address (or partial address) to the
0540  * NAND device. The address is used to select the source/destination for
0541  * a NAND command. */
0542 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
0543 {
0544     dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
0545 
0546     writew(addr, NFC_V1_V2_FLASH_ADDR);
0547     writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
0548 
0549     /* Wait for operation to complete */
0550     wait_op_done(host, islast);
0551 }
0552 
0553 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
0554 {
0555     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0556     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0557     uint32_t tmp;
0558 
0559     tmp = readl(NFC_V3_CONFIG1);
0560     tmp &= ~(7 << 4);
0561     writel(tmp, NFC_V3_CONFIG1);
0562 
0563     /* transfer data from NFC ram to nand */
0564     writel(ops, NFC_V3_LAUNCH);
0565 
0566     wait_op_done(host, false);
0567 }
0568 
0569 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
0570 {
0571     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0572     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0573 
0574     /* NANDFC buffer 0 is used for page read/write */
0575     writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
0576 
0577     writew(ops, NFC_V1_V2_CONFIG2);
0578 
0579     /* Wait for operation to complete */
0580     wait_op_done(host, true);
0581 }
0582 
0583 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
0584 {
0585     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0586     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0587     int bufs, i;
0588 
0589     if (mtd->writesize > 512)
0590         bufs = 4;
0591     else
0592         bufs = 1;
0593 
0594     for (i = 0; i < bufs; i++) {
0595 
0596         /* NANDFC buffer 0 is used for page read/write */
0597         writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
0598 
0599         writew(ops, NFC_V1_V2_CONFIG2);
0600 
0601         /* Wait for operation to complete */
0602         wait_op_done(host, true);
0603     }
0604 }
0605 
0606 static void send_read_id_v3(struct mxc_nand_host *host)
0607 {
0608     /* Read ID into main buffer */
0609     writel(NFC_ID, NFC_V3_LAUNCH);
0610 
0611     wait_op_done(host, true);
0612 
0613     memcpy32_fromio(host->data_buf, host->main_area0, 16);
0614 }
0615 
0616 /* Request the NANDFC to perform a read of the NAND device ID. */
0617 static void send_read_id_v1_v2(struct mxc_nand_host *host)
0618 {
0619     /* NANDFC buffer 0 is used for device ID output */
0620     writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
0621 
0622     writew(NFC_ID, NFC_V1_V2_CONFIG2);
0623 
0624     /* Wait for operation to complete */
0625     wait_op_done(host, true);
0626 
0627     memcpy32_fromio(host->data_buf, host->main_area0, 16);
0628 }
0629 
0630 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
0631 {
0632     writew(NFC_STATUS, NFC_V3_LAUNCH);
0633     wait_op_done(host, true);
0634 
0635     return readl(NFC_V3_CONFIG1) >> 16;
0636 }
0637 
0638 /* This function requests the NANDFC to perform a read of the
0639  * NAND device status and returns the current status. */
0640 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
0641 {
0642     void __iomem *main_buf = host->main_area0;
0643     uint32_t store;
0644     uint16_t ret;
0645 
0646     writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
0647 
0648     /*
0649      * The device status is stored in main_area0. To
0650      * prevent corruption of the buffer save the value
0651      * and restore it afterwards.
0652      */
0653     store = readl(main_buf);
0654 
0655     writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
0656     wait_op_done(host, true);
0657 
0658     ret = readw(main_buf);
0659 
0660     writel(store, main_buf);
0661 
0662     return ret;
0663 }
0664 
0665 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
0666 {
0667     struct mxc_nand_host *host = nand_get_controller_data(chip);
0668     uint16_t config1;
0669 
0670     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0671         return;
0672 
0673     config1 = readw(NFC_V1_V2_CONFIG1);
0674 
0675     if (enable)
0676         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
0677     else
0678         config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
0679 
0680     writew(config1, NFC_V1_V2_CONFIG1);
0681 }
0682 
0683 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
0684 {
0685     struct mxc_nand_host *host = nand_get_controller_data(chip);
0686     uint32_t config2;
0687 
0688     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0689         return;
0690 
0691     config2 = readl(NFC_V3_CONFIG2);
0692 
0693     if (enable)
0694         config2 |= NFC_V3_CONFIG2_ECC_EN;
0695     else
0696         config2 &= ~NFC_V3_CONFIG2_ECC_EN;
0697 
0698     writel(config2, NFC_V3_CONFIG2);
0699 }
0700 
0701 /* This functions is used by upper layer to checks if device is ready */
0702 static int mxc_nand_dev_ready(struct nand_chip *chip)
0703 {
0704     /*
0705      * NFC handles R/B internally. Therefore, this function
0706      * always returns status as ready.
0707      */
0708     return 1;
0709 }
0710 
0711 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
0712                  bool ecc, int page)
0713 {
0714     struct mtd_info *mtd = nand_to_mtd(chip);
0715     struct mxc_nand_host *host = nand_get_controller_data(chip);
0716     unsigned int bitflips_corrected = 0;
0717     int no_subpages;
0718     int i;
0719 
0720     host->devtype_data->enable_hwecc(chip, ecc);
0721 
0722     host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
0723     mxc_do_addr_cycle(mtd, 0, page);
0724 
0725     if (mtd->writesize > 512)
0726         host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
0727 
0728     no_subpages = mtd->writesize >> 9;
0729 
0730     for (i = 0; i < no_subpages; i++) {
0731         uint16_t ecc_stats;
0732 
0733         /* NANDFC buffer 0 is used for page read/write */
0734         writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
0735 
0736         writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
0737 
0738         /* Wait for operation to complete */
0739         wait_op_done(host, true);
0740 
0741         ecc_stats = get_ecc_status_v1(host);
0742 
0743         ecc_stats >>= 2;
0744 
0745         if (buf && ecc) {
0746             switch (ecc_stats & 0x3) {
0747             case 0:
0748             default:
0749                 break;
0750             case 1:
0751                 mtd->ecc_stats.corrected++;
0752                 bitflips_corrected = 1;
0753                 break;
0754             case 2:
0755                 mtd->ecc_stats.failed++;
0756                 break;
0757             }
0758         }
0759     }
0760 
0761     if (buf)
0762         memcpy32_fromio(buf, host->main_area0, mtd->writesize);
0763     if (oob)
0764         copy_spare(mtd, true, oob);
0765 
0766     return bitflips_corrected;
0767 }
0768 
0769 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
0770                     void *oob, bool ecc, int page)
0771 {
0772     struct mtd_info *mtd = nand_to_mtd(chip);
0773     struct mxc_nand_host *host = nand_get_controller_data(chip);
0774     unsigned int max_bitflips = 0;
0775     u32 ecc_stat, err;
0776     int no_subpages;
0777     u8 ecc_bit_mask, err_limit;
0778 
0779     host->devtype_data->enable_hwecc(chip, ecc);
0780 
0781     host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
0782     mxc_do_addr_cycle(mtd, 0, page);
0783 
0784     if (mtd->writesize > 512)
0785         host->devtype_data->send_cmd(host,
0786                 NAND_CMD_READSTART, true);
0787 
0788     host->devtype_data->send_page(mtd, NFC_OUTPUT);
0789 
0790     if (buf)
0791         memcpy32_fromio(buf, host->main_area0, mtd->writesize);
0792     if (oob)
0793         copy_spare(mtd, true, oob);
0794 
0795     ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
0796     err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
0797 
0798     no_subpages = mtd->writesize >> 9;
0799 
0800     ecc_stat = host->devtype_data->get_ecc_status(host);
0801 
0802     do {
0803         err = ecc_stat & ecc_bit_mask;
0804         if (err > err_limit) {
0805             mtd->ecc_stats.failed++;
0806         } else {
0807             mtd->ecc_stats.corrected += err;
0808             max_bitflips = max_t(unsigned int, max_bitflips, err);
0809         }
0810 
0811         ecc_stat >>= 4;
0812     } while (--no_subpages);
0813 
0814     return max_bitflips;
0815 }
0816 
0817 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf,
0818                   int oob_required, int page)
0819 {
0820     struct mxc_nand_host *host = nand_get_controller_data(chip);
0821     void *oob_buf;
0822 
0823     if (oob_required)
0824         oob_buf = chip->oob_poi;
0825     else
0826         oob_buf = NULL;
0827 
0828     return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
0829 }
0830 
0831 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
0832                   int oob_required, int page)
0833 {
0834     struct mxc_nand_host *host = nand_get_controller_data(chip);
0835     void *oob_buf;
0836 
0837     if (oob_required)
0838         oob_buf = chip->oob_poi;
0839     else
0840         oob_buf = NULL;
0841 
0842     return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
0843 }
0844 
0845 static int mxc_nand_read_oob(struct nand_chip *chip, int page)
0846 {
0847     struct mxc_nand_host *host = nand_get_controller_data(chip);
0848 
0849     return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
0850                          page);
0851 }
0852 
0853 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
0854                    bool ecc, int page)
0855 {
0856     struct mtd_info *mtd = nand_to_mtd(chip);
0857     struct mxc_nand_host *host = nand_get_controller_data(chip);
0858 
0859     host->devtype_data->enable_hwecc(chip, ecc);
0860 
0861     host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
0862     mxc_do_addr_cycle(mtd, 0, page);
0863 
0864     memcpy32_toio(host->main_area0, buf, mtd->writesize);
0865     copy_spare(mtd, false, chip->oob_poi);
0866 
0867     host->devtype_data->send_page(mtd, NFC_INPUT);
0868     host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
0869     mxc_do_addr_cycle(mtd, 0, page);
0870 
0871     return 0;
0872 }
0873 
0874 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf,
0875                    int oob_required, int page)
0876 {
0877     return mxc_nand_write_page(chip, buf, true, page);
0878 }
0879 
0880 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
0881                    int oob_required, int page)
0882 {
0883     return mxc_nand_write_page(chip, buf, false, page);
0884 }
0885 
0886 static int mxc_nand_write_oob(struct nand_chip *chip, int page)
0887 {
0888     struct mtd_info *mtd = nand_to_mtd(chip);
0889     struct mxc_nand_host *host = nand_get_controller_data(chip);
0890 
0891     memset(host->data_buf, 0xff, mtd->writesize);
0892 
0893     return mxc_nand_write_page(chip, host->data_buf, false, page);
0894 }
0895 
0896 static u_char mxc_nand_read_byte(struct nand_chip *nand_chip)
0897 {
0898     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0899     uint8_t ret;
0900 
0901     /* Check for status request */
0902     if (host->status_request)
0903         return host->devtype_data->get_dev_status(host) & 0xFF;
0904 
0905     if (nand_chip->options & NAND_BUSWIDTH_16) {
0906         /* only take the lower byte of each word */
0907         ret = *(uint16_t *)(host->data_buf + host->buf_start);
0908 
0909         host->buf_start += 2;
0910     } else {
0911         ret = *(uint8_t *)(host->data_buf + host->buf_start);
0912         host->buf_start++;
0913     }
0914 
0915     dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
0916     return ret;
0917 }
0918 
0919 /* Write data of length len to buffer buf. The data to be
0920  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
0921  * Operation by the NFC, the data is written to NAND Flash */
0922 static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *buf,
0923                    int len)
0924 {
0925     struct mtd_info *mtd = nand_to_mtd(nand_chip);
0926     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0927     u16 col = host->buf_start;
0928     int n = mtd->oobsize + mtd->writesize - col;
0929 
0930     n = min(n, len);
0931 
0932     memcpy(host->data_buf + col, buf, n);
0933 
0934     host->buf_start += n;
0935 }
0936 
0937 /* Read the data buffer from the NAND Flash. To read the data from NAND
0938  * Flash first the data output cycle is initiated by the NFC, which copies
0939  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
0940  */
0941 static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf,
0942                   int len)
0943 {
0944     struct mtd_info *mtd = nand_to_mtd(nand_chip);
0945     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0946     u16 col = host->buf_start;
0947     int n = mtd->oobsize + mtd->writesize - col;
0948 
0949     n = min(n, len);
0950 
0951     memcpy(buf, host->data_buf + col, n);
0952 
0953     host->buf_start += n;
0954 }
0955 
0956 /* This function is used by upper layer for select and
0957  * deselect of the NAND chip */
0958 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip)
0959 {
0960     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0961 
0962     if (chip == -1) {
0963         /* Disable the NFC clock */
0964         if (host->clk_act) {
0965             clk_disable_unprepare(host->clk);
0966             host->clk_act = 0;
0967         }
0968         return;
0969     }
0970 
0971     if (!host->clk_act) {
0972         /* Enable the NFC clock */
0973         clk_prepare_enable(host->clk);
0974         host->clk_act = 1;
0975     }
0976 }
0977 
0978 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip)
0979 {
0980     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
0981 
0982     if (chip == -1) {
0983         /* Disable the NFC clock */
0984         if (host->clk_act) {
0985             clk_disable_unprepare(host->clk);
0986             host->clk_act = 0;
0987         }
0988         return;
0989     }
0990 
0991     if (!host->clk_act) {
0992         /* Enable the NFC clock */
0993         clk_prepare_enable(host->clk);
0994         host->clk_act = 1;
0995     }
0996 
0997     host->active_cs = chip;
0998     writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
0999 }
1000 
1001 #define MXC_V1_ECCBYTES     5
1002 
1003 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1004                 struct mtd_oob_region *oobregion)
1005 {
1006     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1007 
1008     if (section >= nand_chip->ecc.steps)
1009         return -ERANGE;
1010 
1011     oobregion->offset = (section * 16) + 6;
1012     oobregion->length = MXC_V1_ECCBYTES;
1013 
1014     return 0;
1015 }
1016 
1017 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1018                  struct mtd_oob_region *oobregion)
1019 {
1020     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1021 
1022     if (section > nand_chip->ecc.steps)
1023         return -ERANGE;
1024 
1025     if (!section) {
1026         if (mtd->writesize <= 512) {
1027             oobregion->offset = 0;
1028             oobregion->length = 5;
1029         } else {
1030             oobregion->offset = 2;
1031             oobregion->length = 4;
1032         }
1033     } else {
1034         oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1035         if (section < nand_chip->ecc.steps)
1036             oobregion->length = (section * 16) + 6 -
1037                         oobregion->offset;
1038         else
1039             oobregion->length = mtd->oobsize - oobregion->offset;
1040     }
1041 
1042     return 0;
1043 }
1044 
1045 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1046     .ecc = mxc_v1_ooblayout_ecc,
1047     .free = mxc_v1_ooblayout_free,
1048 };
1049 
1050 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1051                 struct mtd_oob_region *oobregion)
1052 {
1053     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1054     int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1055 
1056     if (section >= nand_chip->ecc.steps)
1057         return -ERANGE;
1058 
1059     oobregion->offset = (section * stepsize) + 7;
1060     oobregion->length = nand_chip->ecc.bytes;
1061 
1062     return 0;
1063 }
1064 
1065 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1066                  struct mtd_oob_region *oobregion)
1067 {
1068     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1069     int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1070 
1071     if (section >= nand_chip->ecc.steps)
1072         return -ERANGE;
1073 
1074     if (!section) {
1075         if (mtd->writesize <= 512) {
1076             oobregion->offset = 0;
1077             oobregion->length = 5;
1078         } else {
1079             oobregion->offset = 2;
1080             oobregion->length = 4;
1081         }
1082     } else {
1083         oobregion->offset = section * stepsize;
1084         oobregion->length = 7;
1085     }
1086 
1087     return 0;
1088 }
1089 
1090 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1091     .ecc = mxc_v2_ooblayout_ecc,
1092     .free = mxc_v2_ooblayout_free,
1093 };
1094 
1095 /*
1096  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1097  * on how much oob the nand chip has. For 8bit ecc we need at least
1098  * 26 bytes of oob data per 512 byte block.
1099  */
1100 static int get_eccsize(struct mtd_info *mtd)
1101 {
1102     int oobbytes_per_512 = 0;
1103 
1104     oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1105 
1106     if (oobbytes_per_512 < 26)
1107         return 4;
1108     else
1109         return 8;
1110 }
1111 
1112 static void preset_v1(struct mtd_info *mtd)
1113 {
1114     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1115     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1116     uint16_t config1 = 0;
1117 
1118     if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
1119         mtd->writesize)
1120         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1121 
1122     if (!host->devtype_data->irqpending_quirk)
1123         config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1124 
1125     host->eccsize = 1;
1126 
1127     writew(config1, NFC_V1_V2_CONFIG1);
1128     /* preset operation */
1129 
1130     /* Unlock the internal RAM Buffer */
1131     writew(0x2, NFC_V1_V2_CONFIG);
1132 
1133     /* Blocks to be unlocked */
1134     writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1135     writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1136 
1137     /* Unlock Block Command for given address range */
1138     writew(0x4, NFC_V1_V2_WRPROT);
1139 }
1140 
1141 static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline,
1142                        const struct nand_interface_config *conf)
1143 {
1144     struct mxc_nand_host *host = nand_get_controller_data(chip);
1145     int tRC_min_ns, tRC_ps, ret;
1146     unsigned long rate, rate_round;
1147     const struct nand_sdr_timings *timings;
1148     u16 config1;
1149 
1150     timings = nand_get_sdr_timings(conf);
1151     if (IS_ERR(timings))
1152         return -ENOTSUPP;
1153 
1154     config1 = readw(NFC_V1_V2_CONFIG1);
1155 
1156     tRC_min_ns = timings->tRC_min / 1000;
1157     rate = 1000000000 / tRC_min_ns;
1158 
1159     /*
1160      * For tRC < 30ns we have to use EDO mode. In this case the controller
1161      * does one access per clock cycle. Otherwise the controller does one
1162      * access in two clock cycles, thus we have to double the rate to the
1163      * controller.
1164      */
1165     if (tRC_min_ns < 30) {
1166         rate_round = clk_round_rate(host->clk, rate);
1167         config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1168         tRC_ps = 1000000000 / (rate_round / 1000);
1169     } else {
1170         rate *= 2;
1171         rate_round = clk_round_rate(host->clk, rate);
1172         config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1173         tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1174     }
1175 
1176     /*
1177      * The timing values compared against are from the i.MX25 Automotive
1178      * datasheet, Table 50. NFC Timing Parameters
1179      */
1180     if (timings->tCLS_min > tRC_ps - 1000 ||
1181         timings->tCLH_min > tRC_ps - 2000 ||
1182         timings->tCS_min > tRC_ps - 1000 ||
1183         timings->tCH_min > tRC_ps - 2000 ||
1184         timings->tWP_min > tRC_ps - 1500 ||
1185         timings->tALS_min > tRC_ps ||
1186         timings->tALH_min > tRC_ps - 3000 ||
1187         timings->tDS_min > tRC_ps ||
1188         timings->tDH_min > tRC_ps - 5000 ||
1189         timings->tWC_min > 2 * tRC_ps ||
1190         timings->tWH_min > tRC_ps - 2500 ||
1191         timings->tRR_min > 6 * tRC_ps ||
1192         timings->tRP_min > 3 * tRC_ps / 2 ||
1193         timings->tRC_min > 2 * tRC_ps ||
1194         timings->tREH_min > (tRC_ps / 2) - 2500) {
1195         dev_dbg(host->dev, "Timing out of bounds\n");
1196         return -EINVAL;
1197     }
1198 
1199     if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1200         return 0;
1201 
1202     ret = clk_set_rate(host->clk, rate);
1203     if (ret)
1204         return ret;
1205 
1206     writew(config1, NFC_V1_V2_CONFIG1);
1207 
1208     dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1209         config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1210         "normal");
1211 
1212     return 0;
1213 }
1214 
1215 static void preset_v2(struct mtd_info *mtd)
1216 {
1217     struct nand_chip *nand_chip = mtd_to_nand(mtd);
1218     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1219     uint16_t config1 = 0;
1220 
1221     config1 |= NFC_V2_CONFIG1_FP_INT;
1222 
1223     if (!host->devtype_data->irqpending_quirk)
1224         config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1225 
1226     if (mtd->writesize) {
1227         uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1228 
1229         if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1230             config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1231 
1232         host->eccsize = get_eccsize(mtd);
1233         if (host->eccsize == 4)
1234             config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1235 
1236         config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1237     } else {
1238         host->eccsize = 1;
1239     }
1240 
1241     writew(config1, NFC_V1_V2_CONFIG1);
1242     /* preset operation */
1243 
1244     /* spare area size in 16-bit half-words */
1245     writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1246 
1247     /* Unlock the internal RAM Buffer */
1248     writew(0x2, NFC_V1_V2_CONFIG);
1249 
1250     /* Blocks to be unlocked */
1251     writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1252     writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1253     writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1254     writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1255     writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1256     writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1257     writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1258     writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1259 
1260     /* Unlock Block Command for given address range */
1261     writew(0x4, NFC_V1_V2_WRPROT);
1262 }
1263 
1264 static void preset_v3(struct mtd_info *mtd)
1265 {
1266     struct nand_chip *chip = mtd_to_nand(mtd);
1267     struct mxc_nand_host *host = nand_get_controller_data(chip);
1268     uint32_t config2, config3;
1269     int i, addr_phases;
1270 
1271     writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1272     writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1273 
1274     /* Unlock the internal RAM Buffer */
1275     writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1276             NFC_V3_WRPROT);
1277 
1278     /* Blocks to be unlocked */
1279     for (i = 0; i < NAND_MAX_CHIPS; i++)
1280         writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1281 
1282     writel(0, NFC_V3_IPC);
1283 
1284     config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1285         NFC_V3_CONFIG2_2CMD_PHASES |
1286         NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1287         NFC_V3_CONFIG2_ST_CMD(0x70) |
1288         NFC_V3_CONFIG2_INT_MSK |
1289         NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1290 
1291     addr_phases = fls(chip->pagemask) >> 3;
1292 
1293     if (mtd->writesize == 2048) {
1294         config2 |= NFC_V3_CONFIG2_PS_2048;
1295         config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1296     } else if (mtd->writesize == 4096) {
1297         config2 |= NFC_V3_CONFIG2_PS_4096;
1298         config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1299     } else {
1300         config2 |= NFC_V3_CONFIG2_PS_512;
1301         config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1302     }
1303 
1304     if (mtd->writesize) {
1305         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1306             config2 |= NFC_V3_CONFIG2_ECC_EN;
1307 
1308         config2 |= NFC_V3_CONFIG2_PPB(
1309                 ffs(mtd->erasesize / mtd->writesize) - 6,
1310                 host->devtype_data->ppb_shift);
1311         host->eccsize = get_eccsize(mtd);
1312         if (host->eccsize == 8)
1313             config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1314     }
1315 
1316     writel(config2, NFC_V3_CONFIG2);
1317 
1318     config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1319             NFC_V3_CONFIG3_NO_SDMA |
1320             NFC_V3_CONFIG3_RBB_MODE |
1321             NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1322             NFC_V3_CONFIG3_ADD_OP(0);
1323 
1324     if (!(chip->options & NAND_BUSWIDTH_16))
1325         config3 |= NFC_V3_CONFIG3_FW8;
1326 
1327     writel(config3, NFC_V3_CONFIG3);
1328 
1329     writel(0, NFC_V3_DELAY_LINE);
1330 }
1331 
1332 /* Used by the upper layer to write command to NAND Flash for
1333  * different operations to be carried out on NAND Flash */
1334 static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command,
1335                  int column, int page_addr)
1336 {
1337     struct mtd_info *mtd = nand_to_mtd(nand_chip);
1338     struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1339 
1340     dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1341           command, column, page_addr);
1342 
1343     /* Reset command state information */
1344     host->status_request = false;
1345 
1346     /* Command pre-processing step */
1347     switch (command) {
1348     case NAND_CMD_RESET:
1349         host->devtype_data->preset(mtd);
1350         host->devtype_data->send_cmd(host, command, false);
1351         break;
1352 
1353     case NAND_CMD_STATUS:
1354         host->buf_start = 0;
1355         host->status_request = true;
1356 
1357         host->devtype_data->send_cmd(host, command, true);
1358         WARN_ONCE(column != -1 || page_addr != -1,
1359               "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1360               command, column, page_addr);
1361         mxc_do_addr_cycle(mtd, column, page_addr);
1362         break;
1363 
1364     case NAND_CMD_READID:
1365         host->devtype_data->send_cmd(host, command, true);
1366         mxc_do_addr_cycle(mtd, column, page_addr);
1367         host->devtype_data->send_read_id(host);
1368         host->buf_start = 0;
1369         break;
1370 
1371     case NAND_CMD_ERASE1:
1372     case NAND_CMD_ERASE2:
1373         host->devtype_data->send_cmd(host, command, false);
1374         WARN_ONCE(column != -1,
1375               "Unexpected column value (cmd=%u, col=%d)\n",
1376               command, column);
1377         mxc_do_addr_cycle(mtd, column, page_addr);
1378 
1379         break;
1380     case NAND_CMD_PARAM:
1381         host->devtype_data->send_cmd(host, command, false);
1382         mxc_do_addr_cycle(mtd, column, page_addr);
1383         host->devtype_data->send_page(mtd, NFC_OUTPUT);
1384         memcpy32_fromio(host->data_buf, host->main_area0, 512);
1385         host->buf_start = 0;
1386         break;
1387     default:
1388         WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1389               command);
1390         break;
1391     }
1392 }
1393 
1394 static int mxc_nand_set_features(struct nand_chip *chip, int addr,
1395                  u8 *subfeature_param)
1396 {
1397     struct mtd_info *mtd = nand_to_mtd(chip);
1398     struct mxc_nand_host *host = nand_get_controller_data(chip);
1399     int i;
1400 
1401     host->buf_start = 0;
1402 
1403     for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1404         chip->legacy.write_byte(chip, subfeature_param[i]);
1405 
1406     memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1407     host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1408     mxc_do_addr_cycle(mtd, addr, -1);
1409     host->devtype_data->send_page(mtd, NFC_INPUT);
1410 
1411     return 0;
1412 }
1413 
1414 static int mxc_nand_get_features(struct nand_chip *chip, int addr,
1415                  u8 *subfeature_param)
1416 {
1417     struct mtd_info *mtd = nand_to_mtd(chip);
1418     struct mxc_nand_host *host = nand_get_controller_data(chip);
1419     int i;
1420 
1421     host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1422     mxc_do_addr_cycle(mtd, addr, -1);
1423     host->devtype_data->send_page(mtd, NFC_OUTPUT);
1424     memcpy32_fromio(host->data_buf, host->main_area0, 512);
1425     host->buf_start = 0;
1426 
1427     for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1428         *subfeature_param++ = chip->legacy.read_byte(chip);
1429 
1430     return 0;
1431 }
1432 
1433 /*
1434  * The generic flash bbt descriptors overlap with our ecc
1435  * hardware, so define some i.MX specific ones.
1436  */
1437 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1438 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1439 
1440 static struct nand_bbt_descr bbt_main_descr = {
1441     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1442         | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1443     .offs = 0,
1444     .len = 4,
1445     .veroffs = 4,
1446     .maxblocks = 4,
1447     .pattern = bbt_pattern,
1448 };
1449 
1450 static struct nand_bbt_descr bbt_mirror_descr = {
1451     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1452         | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1453     .offs = 0,
1454     .len = 4,
1455     .veroffs = 4,
1456     .maxblocks = 4,
1457     .pattern = mirror_pattern,
1458 };
1459 
1460 /* v1 + irqpending_quirk: i.MX21 */
1461 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1462     .preset = preset_v1,
1463     .read_page = mxc_nand_read_page_v1,
1464     .send_cmd = send_cmd_v1_v2,
1465     .send_addr = send_addr_v1_v2,
1466     .send_page = send_page_v1,
1467     .send_read_id = send_read_id_v1_v2,
1468     .get_dev_status = get_dev_status_v1_v2,
1469     .check_int = check_int_v1_v2,
1470     .irq_control = irq_control_v1_v2,
1471     .get_ecc_status = get_ecc_status_v1,
1472     .ooblayout = &mxc_v1_ooblayout_ops,
1473     .select_chip = mxc_nand_select_chip_v1_v3,
1474     .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1475     .irqpending_quirk = 1,
1476     .needs_ip = 0,
1477     .regs_offset = 0xe00,
1478     .spare0_offset = 0x800,
1479     .spare_len = 16,
1480     .eccbytes = 3,
1481     .eccsize = 1,
1482 };
1483 
1484 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1485 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1486     .preset = preset_v1,
1487     .read_page = mxc_nand_read_page_v1,
1488     .send_cmd = send_cmd_v1_v2,
1489     .send_addr = send_addr_v1_v2,
1490     .send_page = send_page_v1,
1491     .send_read_id = send_read_id_v1_v2,
1492     .get_dev_status = get_dev_status_v1_v2,
1493     .check_int = check_int_v1_v2,
1494     .irq_control = irq_control_v1_v2,
1495     .get_ecc_status = get_ecc_status_v1,
1496     .ooblayout = &mxc_v1_ooblayout_ops,
1497     .select_chip = mxc_nand_select_chip_v1_v3,
1498     .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1499     .irqpending_quirk = 0,
1500     .needs_ip = 0,
1501     .regs_offset = 0xe00,
1502     .spare0_offset = 0x800,
1503     .axi_offset = 0,
1504     .spare_len = 16,
1505     .eccbytes = 3,
1506     .eccsize = 1,
1507 };
1508 
1509 /* v21: i.MX25, i.MX35 */
1510 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1511     .preset = preset_v2,
1512     .read_page = mxc_nand_read_page_v2_v3,
1513     .send_cmd = send_cmd_v1_v2,
1514     .send_addr = send_addr_v1_v2,
1515     .send_page = send_page_v2,
1516     .send_read_id = send_read_id_v1_v2,
1517     .get_dev_status = get_dev_status_v1_v2,
1518     .check_int = check_int_v1_v2,
1519     .irq_control = irq_control_v1_v2,
1520     .get_ecc_status = get_ecc_status_v2,
1521     .ooblayout = &mxc_v2_ooblayout_ops,
1522     .select_chip = mxc_nand_select_chip_v2,
1523     .setup_interface = mxc_nand_v2_setup_interface,
1524     .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1525     .irqpending_quirk = 0,
1526     .needs_ip = 0,
1527     .regs_offset = 0x1e00,
1528     .spare0_offset = 0x1000,
1529     .axi_offset = 0,
1530     .spare_len = 64,
1531     .eccbytes = 9,
1532     .eccsize = 0,
1533 };
1534 
1535 /* v3.2a: i.MX51 */
1536 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1537     .preset = preset_v3,
1538     .read_page = mxc_nand_read_page_v2_v3,
1539     .send_cmd = send_cmd_v3,
1540     .send_addr = send_addr_v3,
1541     .send_page = send_page_v3,
1542     .send_read_id = send_read_id_v3,
1543     .get_dev_status = get_dev_status_v3,
1544     .check_int = check_int_v3,
1545     .irq_control = irq_control_v3,
1546     .get_ecc_status = get_ecc_status_v3,
1547     .ooblayout = &mxc_v2_ooblayout_ops,
1548     .select_chip = mxc_nand_select_chip_v1_v3,
1549     .enable_hwecc = mxc_nand_enable_hwecc_v3,
1550     .irqpending_quirk = 0,
1551     .needs_ip = 1,
1552     .regs_offset = 0,
1553     .spare0_offset = 0x1000,
1554     .axi_offset = 0x1e00,
1555     .spare_len = 64,
1556     .eccbytes = 0,
1557     .eccsize = 0,
1558     .ppb_shift = 7,
1559 };
1560 
1561 /* v3.2b: i.MX53 */
1562 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1563     .preset = preset_v3,
1564     .read_page = mxc_nand_read_page_v2_v3,
1565     .send_cmd = send_cmd_v3,
1566     .send_addr = send_addr_v3,
1567     .send_page = send_page_v3,
1568     .send_read_id = send_read_id_v3,
1569     .get_dev_status = get_dev_status_v3,
1570     .check_int = check_int_v3,
1571     .irq_control = irq_control_v3,
1572     .get_ecc_status = get_ecc_status_v3,
1573     .ooblayout = &mxc_v2_ooblayout_ops,
1574     .select_chip = mxc_nand_select_chip_v1_v3,
1575     .enable_hwecc = mxc_nand_enable_hwecc_v3,
1576     .irqpending_quirk = 0,
1577     .needs_ip = 1,
1578     .regs_offset = 0,
1579     .spare0_offset = 0x1000,
1580     .axi_offset = 0x1e00,
1581     .spare_len = 64,
1582     .eccbytes = 0,
1583     .eccsize = 0,
1584     .ppb_shift = 8,
1585 };
1586 
1587 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1588 {
1589     return host->devtype_data == &imx21_nand_devtype_data;
1590 }
1591 
1592 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1593 {
1594     return host->devtype_data == &imx27_nand_devtype_data;
1595 }
1596 
1597 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1598 {
1599     return host->devtype_data == &imx25_nand_devtype_data;
1600 }
1601 
1602 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1603 {
1604     return host->devtype_data == &imx51_nand_devtype_data;
1605 }
1606 
1607 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1608 {
1609     return host->devtype_data == &imx53_nand_devtype_data;
1610 }
1611 
1612 static const struct of_device_id mxcnd_dt_ids[] = {
1613     { .compatible = "fsl,imx21-nand", .data = &imx21_nand_devtype_data, },
1614     { .compatible = "fsl,imx27-nand", .data = &imx27_nand_devtype_data, },
1615     { .compatible = "fsl,imx25-nand", .data = &imx25_nand_devtype_data, },
1616     { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, },
1617     { .compatible = "fsl,imx53-nand", .data = &imx53_nand_devtype_data, },
1618     { /* sentinel */ }
1619 };
1620 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1621 
1622 static int mxcnd_attach_chip(struct nand_chip *chip)
1623 {
1624     struct mtd_info *mtd = nand_to_mtd(chip);
1625     struct mxc_nand_host *host = nand_get_controller_data(chip);
1626     struct device *dev = mtd->dev.parent;
1627 
1628     chip->ecc.bytes = host->devtype_data->eccbytes;
1629     host->eccsize = host->devtype_data->eccsize;
1630     chip->ecc.size = 512;
1631     mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1632 
1633     switch (chip->ecc.engine_type) {
1634     case NAND_ECC_ENGINE_TYPE_ON_HOST:
1635         chip->ecc.read_page = mxc_nand_read_page;
1636         chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1637         chip->ecc.read_oob = mxc_nand_read_oob;
1638         chip->ecc.write_page = mxc_nand_write_page_ecc;
1639         chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1640         chip->ecc.write_oob = mxc_nand_write_oob;
1641         break;
1642 
1643     case NAND_ECC_ENGINE_TYPE_SOFT:
1644         break;
1645 
1646     default:
1647         return -EINVAL;
1648     }
1649 
1650     if (chip->bbt_options & NAND_BBT_USE_FLASH) {
1651         chip->bbt_td = &bbt_main_descr;
1652         chip->bbt_md = &bbt_mirror_descr;
1653     }
1654 
1655     /* Allocate the right size buffer now */
1656     devm_kfree(dev, (void *)host->data_buf);
1657     host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize,
1658                       GFP_KERNEL);
1659     if (!host->data_buf)
1660         return -ENOMEM;
1661 
1662     /* Call preset again, with correct writesize chip time */
1663     host->devtype_data->preset(mtd);
1664 
1665     if (!chip->ecc.bytes) {
1666         if (host->eccsize == 8)
1667             chip->ecc.bytes = 18;
1668         else if (host->eccsize == 4)
1669             chip->ecc.bytes = 9;
1670     }
1671 
1672     /*
1673      * Experimentation shows that i.MX NFC can only handle up to 218 oob
1674      * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1675      * into copying invalid data to/from the spare IO buffer, as this
1676      * might cause ECC data corruption when doing sub-page write to a
1677      * partially written page.
1678      */
1679     host->used_oobsize = min(mtd->oobsize, 218U);
1680 
1681     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1682         if (is_imx21_nfc(host) || is_imx27_nfc(host))
1683             chip->ecc.strength = 1;
1684         else
1685             chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1686     }
1687 
1688     return 0;
1689 }
1690 
1691 static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr,
1692                  const struct nand_interface_config *conf)
1693 {
1694     struct mxc_nand_host *host = nand_get_controller_data(chip);
1695 
1696     return host->devtype_data->setup_interface(chip, chipnr, conf);
1697 }
1698 
1699 static const struct nand_controller_ops mxcnd_controller_ops = {
1700     .attach_chip = mxcnd_attach_chip,
1701     .setup_interface = mxcnd_setup_interface,
1702 };
1703 
1704 static int mxcnd_probe(struct platform_device *pdev)
1705 {
1706     struct nand_chip *this;
1707     struct mtd_info *mtd;
1708     struct mxc_nand_host *host;
1709     struct resource *res;
1710     int err = 0;
1711 
1712     /* Allocate memory for MTD device structure and private data */
1713     host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1714             GFP_KERNEL);
1715     if (!host)
1716         return -ENOMEM;
1717 
1718     /* allocate a temporary buffer for the nand_scan_ident() */
1719     host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1720     if (!host->data_buf)
1721         return -ENOMEM;
1722 
1723     host->dev = &pdev->dev;
1724     /* structures must be linked */
1725     this = &host->nand;
1726     mtd = nand_to_mtd(this);
1727     mtd->dev.parent = &pdev->dev;
1728     mtd->name = DRIVER_NAME;
1729 
1730     /* 50 us command delay time */
1731     this->legacy.chip_delay = 5;
1732 
1733     nand_set_controller_data(this, host);
1734     nand_set_flash_node(this, pdev->dev.of_node);
1735     this->legacy.dev_ready = mxc_nand_dev_ready;
1736     this->legacy.cmdfunc = mxc_nand_command;
1737     this->legacy.read_byte = mxc_nand_read_byte;
1738     this->legacy.write_buf = mxc_nand_write_buf;
1739     this->legacy.read_buf = mxc_nand_read_buf;
1740     this->legacy.set_features = mxc_nand_set_features;
1741     this->legacy.get_features = mxc_nand_get_features;
1742 
1743     host->clk = devm_clk_get(&pdev->dev, NULL);
1744     if (IS_ERR(host->clk))
1745         return PTR_ERR(host->clk);
1746 
1747     host->devtype_data = device_get_match_data(&pdev->dev);
1748 
1749     if (!host->devtype_data->setup_interface)
1750         this->options |= NAND_KEEP_TIMINGS;
1751 
1752     if (host->devtype_data->needs_ip) {
1753         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1754         host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1755         if (IS_ERR(host->regs_ip))
1756             return PTR_ERR(host->regs_ip);
1757 
1758         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1759     } else {
1760         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1761     }
1762 
1763     host->base = devm_ioremap_resource(&pdev->dev, res);
1764     if (IS_ERR(host->base))
1765         return PTR_ERR(host->base);
1766 
1767     host->main_area0 = host->base;
1768 
1769     if (host->devtype_data->regs_offset)
1770         host->regs = host->base + host->devtype_data->regs_offset;
1771     host->spare0 = host->base + host->devtype_data->spare0_offset;
1772     if (host->devtype_data->axi_offset)
1773         host->regs_axi = host->base + host->devtype_data->axi_offset;
1774 
1775     this->legacy.select_chip = host->devtype_data->select_chip;
1776 
1777     init_completion(&host->op_completion);
1778 
1779     host->irq = platform_get_irq(pdev, 0);
1780     if (host->irq < 0)
1781         return host->irq;
1782 
1783     /*
1784      * Use host->devtype_data->irq_control() here instead of irq_control()
1785      * because we must not disable_irq_nosync without having requested the
1786      * irq.
1787      */
1788     host->devtype_data->irq_control(host, 0);
1789 
1790     err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1791             0, DRIVER_NAME, host);
1792     if (err)
1793         return err;
1794 
1795     err = clk_prepare_enable(host->clk);
1796     if (err)
1797         return err;
1798     host->clk_act = 1;
1799 
1800     /*
1801      * Now that we "own" the interrupt make sure the interrupt mask bit is
1802      * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1803      * on this machine.
1804      */
1805     if (host->devtype_data->irqpending_quirk) {
1806         disable_irq_nosync(host->irq);
1807         host->devtype_data->irq_control(host, 1);
1808     }
1809 
1810     /* Scan the NAND device */
1811     this->legacy.dummy_controller.ops = &mxcnd_controller_ops;
1812     err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1);
1813     if (err)
1814         goto escan;
1815 
1816     /* Register the partitions */
1817     err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1818     if (err)
1819         goto cleanup_nand;
1820 
1821     platform_set_drvdata(pdev, host);
1822 
1823     return 0;
1824 
1825 cleanup_nand:
1826     nand_cleanup(this);
1827 escan:
1828     if (host->clk_act)
1829         clk_disable_unprepare(host->clk);
1830 
1831     return err;
1832 }
1833 
1834 static int mxcnd_remove(struct platform_device *pdev)
1835 {
1836     struct mxc_nand_host *host = platform_get_drvdata(pdev);
1837     struct nand_chip *chip = &host->nand;
1838     int ret;
1839 
1840     ret = mtd_device_unregister(nand_to_mtd(chip));
1841     WARN_ON(ret);
1842     nand_cleanup(chip);
1843     if (host->clk_act)
1844         clk_disable_unprepare(host->clk);
1845 
1846     return 0;
1847 }
1848 
1849 static struct platform_driver mxcnd_driver = {
1850     .driver = {
1851            .name = DRIVER_NAME,
1852            .of_match_table = mxcnd_dt_ids,
1853     },
1854     .probe = mxcnd_probe,
1855     .remove = mxcnd_remove,
1856 };
1857 module_platform_driver(mxcnd_driver);
1858 
1859 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1860 MODULE_DESCRIPTION("MXC NAND MTD driver");
1861 MODULE_LICENSE("GPL");
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