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0001 // SPDX-License-Identifier: GPL-2.0 OR MIT
0002 /*
0003  * MTK NAND Flash controller driver.
0004  * Copyright (C) 2016 MediaTek Inc.
0005  * Authors: Xiaolei Li      <xiaolei.li@mediatek.com>
0006  *      Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
0007  */
0008 
0009 #include <linux/platform_device.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/delay.h>
0013 #include <linux/clk.h>
0014 #include <linux/mtd/rawnand.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/module.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/of.h>
0019 #include <linux/of_device.h>
0020 #include <linux/mtd/nand-ecc-mtk.h>
0021 
0022 /* NAND controller register definition */
0023 #define NFI_CNFG        (0x00)
0024 #define     CNFG_AHB        BIT(0)
0025 #define     CNFG_READ_EN        BIT(1)
0026 #define     CNFG_DMA_BURST_EN   BIT(2)
0027 #define     CNFG_BYTE_RW        BIT(6)
0028 #define     CNFG_HW_ECC_EN      BIT(8)
0029 #define     CNFG_AUTO_FMT_EN    BIT(9)
0030 #define     CNFG_OP_CUST        (6 << 12)
0031 #define NFI_PAGEFMT     (0x04)
0032 #define     PAGEFMT_FDM_ECC_SHIFT   (12)
0033 #define     PAGEFMT_FDM_SHIFT   (8)
0034 #define     PAGEFMT_SEC_SEL_512 BIT(2)
0035 #define     PAGEFMT_512_2K      (0)
0036 #define     PAGEFMT_2K_4K       (1)
0037 #define     PAGEFMT_4K_8K       (2)
0038 #define     PAGEFMT_8K_16K      (3)
0039 /* NFI control */
0040 #define NFI_CON         (0x08)
0041 #define     CON_FIFO_FLUSH      BIT(0)
0042 #define     CON_NFI_RST     BIT(1)
0043 #define     CON_BRD         BIT(8)  /* burst  read */
0044 #define     CON_BWR         BIT(9)  /* burst  write */
0045 #define     CON_SEC_SHIFT       (12)
0046 /* Timming control register */
0047 #define NFI_ACCCON      (0x0C)
0048 #define NFI_INTR_EN     (0x10)
0049 #define     INTR_AHB_DONE_EN    BIT(6)
0050 #define NFI_INTR_STA        (0x14)
0051 #define NFI_CMD         (0x20)
0052 #define NFI_ADDRNOB     (0x30)
0053 #define NFI_COLADDR     (0x34)
0054 #define NFI_ROWADDR     (0x38)
0055 #define NFI_STRDATA     (0x40)
0056 #define     STAR_EN         (1)
0057 #define     STAR_DE         (0)
0058 #define NFI_CNRNB       (0x44)
0059 #define NFI_DATAW       (0x50)
0060 #define NFI_DATAR       (0x54)
0061 #define NFI_PIO_DIRDY       (0x58)
0062 #define     PIO_DI_RDY      (0x01)
0063 #define NFI_STA         (0x60)
0064 #define     STA_CMD         BIT(0)
0065 #define     STA_ADDR        BIT(1)
0066 #define     STA_BUSY        BIT(8)
0067 #define     STA_EMP_PAGE        BIT(12)
0068 #define     NFI_FSM_CUSTDATA    (0xe << 16)
0069 #define     NFI_FSM_MASK        (0xf << 16)
0070 #define NFI_ADDRCNTR        (0x70)
0071 #define     CNTR_MASK       GENMASK(16, 12)
0072 #define     ADDRCNTR_SEC_SHIFT  (12)
0073 #define     ADDRCNTR_SEC(val) \
0074         (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
0075 #define NFI_STRADDR     (0x80)
0076 #define NFI_BYTELEN     (0x84)
0077 #define NFI_CSEL        (0x90)
0078 #define NFI_FDML(x)     (0xA0 + (x) * sizeof(u32) * 2)
0079 #define NFI_FDMM(x)     (0xA4 + (x) * sizeof(u32) * 2)
0080 #define NFI_FDM_MAX_SIZE    (8)
0081 #define NFI_FDM_MIN_SIZE    (1)
0082 #define NFI_DEBUG_CON1      (0x220)
0083 #define     STROBE_MASK     GENMASK(4, 3)
0084 #define     STROBE_SHIFT        (3)
0085 #define     MAX_STROBE_DLY      (3)
0086 #define NFI_MASTER_STA      (0x224)
0087 #define     MASTER_STA_MASK     (0x0FFF)
0088 #define NFI_EMPTY_THRESH    (0x23C)
0089 
0090 #define MTK_NAME        "mtk-nand"
0091 #define KB(x)           ((x) * 1024UL)
0092 #define MB(x)           (KB(x) * 1024UL)
0093 
0094 #define MTK_TIMEOUT     (500000)
0095 #define MTK_RESET_TIMEOUT   (1000000)
0096 #define MTK_NAND_MAX_NSELS  (2)
0097 #define MTK_NFC_MIN_SPARE   (16)
0098 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
0099     ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \
0100     (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt))
0101 
0102 struct mtk_nfc_caps {
0103     const u8 *spare_size;
0104     u8 num_spare_size;
0105     u8 pageformat_spare_shift;
0106     u8 nfi_clk_div;
0107     u8 max_sector;
0108     u32 max_sector_size;
0109 };
0110 
0111 struct mtk_nfc_bad_mark_ctl {
0112     void (*bm_swap)(struct mtd_info *, u8 *buf, int raw);
0113     u32 sec;
0114     u32 pos;
0115 };
0116 
0117 /*
0118  * FDM: region used to store free OOB data
0119  */
0120 struct mtk_nfc_fdm {
0121     u32 reg_size;
0122     u32 ecc_size;
0123 };
0124 
0125 struct mtk_nfc_nand_chip {
0126     struct list_head node;
0127     struct nand_chip nand;
0128 
0129     struct mtk_nfc_bad_mark_ctl bad_mark;
0130     struct mtk_nfc_fdm fdm;
0131     u32 spare_per_sector;
0132 
0133     int nsels;
0134     u8 sels[];
0135     /* nothing after this field */
0136 };
0137 
0138 struct mtk_nfc_clk {
0139     struct clk *nfi_clk;
0140     struct clk *pad_clk;
0141 };
0142 
0143 struct mtk_nfc {
0144     struct nand_controller controller;
0145     struct mtk_ecc_config ecc_cfg;
0146     struct mtk_nfc_clk clk;
0147     struct mtk_ecc *ecc;
0148 
0149     struct device *dev;
0150     const struct mtk_nfc_caps *caps;
0151     void __iomem *regs;
0152 
0153     struct completion done;
0154     struct list_head chips;
0155 
0156     u8 *buffer;
0157 
0158     unsigned long assigned_cs;
0159 };
0160 
0161 /*
0162  * supported spare size of each IP.
0163  * order should be the same with the spare size bitfiled defination of
0164  * register NFI_PAGEFMT.
0165  */
0166 static const u8 spare_size_mt2701[] = {
0167     16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64
0168 };
0169 
0170 static const u8 spare_size_mt2712[] = {
0171     16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67,
0172     74
0173 };
0174 
0175 static const u8 spare_size_mt7622[] = {
0176     16, 26, 27, 28
0177 };
0178 
0179 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
0180 {
0181     return container_of(nand, struct mtk_nfc_nand_chip, nand);
0182 }
0183 
0184 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i)
0185 {
0186     return (u8 *)p + i * chip->ecc.size;
0187 }
0188 
0189 static inline u8 *oob_ptr(struct nand_chip *chip, int i)
0190 {
0191     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0192     u8 *poi;
0193 
0194     /* map the sector's FDM data to free oob:
0195      * the beginning of the oob area stores the FDM data of bad mark sectors
0196      */
0197 
0198     if (i < mtk_nand->bad_mark.sec)
0199         poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
0200     else if (i == mtk_nand->bad_mark.sec)
0201         poi = chip->oob_poi;
0202     else
0203         poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
0204 
0205     return poi;
0206 }
0207 
0208 static inline int mtk_data_len(struct nand_chip *chip)
0209 {
0210     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0211 
0212     return chip->ecc.size + mtk_nand->spare_per_sector;
0213 }
0214 
0215 static inline u8 *mtk_data_ptr(struct nand_chip *chip,  int i)
0216 {
0217     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0218 
0219     return nfc->buffer + i * mtk_data_len(chip);
0220 }
0221 
0222 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i)
0223 {
0224     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0225 
0226     return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
0227 }
0228 
0229 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
0230 {
0231     writel(val, nfc->regs + reg);
0232 }
0233 
0234 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
0235 {
0236     writew(val, nfc->regs + reg);
0237 }
0238 
0239 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
0240 {
0241     writeb(val, nfc->regs + reg);
0242 }
0243 
0244 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
0245 {
0246     return readl_relaxed(nfc->regs + reg);
0247 }
0248 
0249 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
0250 {
0251     return readw_relaxed(nfc->regs + reg);
0252 }
0253 
0254 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
0255 {
0256     return readb_relaxed(nfc->regs + reg);
0257 }
0258 
0259 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
0260 {
0261     struct device *dev = nfc->dev;
0262     u32 val;
0263     int ret;
0264 
0265     /* reset all registers and force the NFI master to terminate */
0266     nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
0267 
0268     /* wait for the master to finish the last transaction */
0269     ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
0270                  !(val & MASTER_STA_MASK), 50,
0271                  MTK_RESET_TIMEOUT);
0272     if (ret)
0273         dev_warn(dev, "master active in reset [0x%x] = 0x%x\n",
0274              NFI_MASTER_STA, val);
0275 
0276     /* ensure any status register affected by the NFI master is reset */
0277     nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
0278     nfi_writew(nfc, STAR_DE, NFI_STRDATA);
0279 }
0280 
0281 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
0282 {
0283     struct device *dev = nfc->dev;
0284     u32 val;
0285     int ret;
0286 
0287     nfi_writel(nfc, command, NFI_CMD);
0288 
0289     ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
0290                     !(val & STA_CMD), 10,  MTK_TIMEOUT);
0291     if (ret) {
0292         dev_warn(dev, "nfi core timed out entering command mode\n");
0293         return -EIO;
0294     }
0295 
0296     return 0;
0297 }
0298 
0299 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
0300 {
0301     struct device *dev = nfc->dev;
0302     u32 val;
0303     int ret;
0304 
0305     nfi_writel(nfc, addr, NFI_COLADDR);
0306     nfi_writel(nfc, 0, NFI_ROWADDR);
0307     nfi_writew(nfc, 1, NFI_ADDRNOB);
0308 
0309     ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
0310                     !(val & STA_ADDR), 10, MTK_TIMEOUT);
0311     if (ret) {
0312         dev_warn(dev, "nfi core timed out entering address mode\n");
0313         return -EIO;
0314     }
0315 
0316     return 0;
0317 }
0318 
0319 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
0320 {
0321     struct nand_chip *chip = mtd_to_nand(mtd);
0322     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0323     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0324     u32 fmt, spare, i;
0325 
0326     if (!mtd->writesize)
0327         return 0;
0328 
0329     spare = mtk_nand->spare_per_sector;
0330 
0331     switch (mtd->writesize) {
0332     case 512:
0333         fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
0334         break;
0335     case KB(2):
0336         if (chip->ecc.size == 512)
0337             fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
0338         else
0339             fmt = PAGEFMT_512_2K;
0340         break;
0341     case KB(4):
0342         if (chip->ecc.size == 512)
0343             fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
0344         else
0345             fmt = PAGEFMT_2K_4K;
0346         break;
0347     case KB(8):
0348         if (chip->ecc.size == 512)
0349             fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
0350         else
0351             fmt = PAGEFMT_4K_8K;
0352         break;
0353     case KB(16):
0354         fmt = PAGEFMT_8K_16K;
0355         break;
0356     default:
0357         dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
0358         return -EINVAL;
0359     }
0360 
0361     /*
0362      * the hardware will double the value for this eccsize, so we need to
0363      * halve it
0364      */
0365     if (chip->ecc.size == 1024)
0366         spare >>= 1;
0367 
0368     for (i = 0; i < nfc->caps->num_spare_size; i++) {
0369         if (nfc->caps->spare_size[i] == spare)
0370             break;
0371     }
0372 
0373     if (i == nfc->caps->num_spare_size) {
0374         dev_err(nfc->dev, "invalid spare size %d\n", spare);
0375         return -EINVAL;
0376     }
0377 
0378     fmt |= i << nfc->caps->pageformat_spare_shift;
0379 
0380     fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
0381     fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
0382     nfi_writel(nfc, fmt, NFI_PAGEFMT);
0383 
0384     nfc->ecc_cfg.strength = chip->ecc.strength;
0385     nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
0386 
0387     return 0;
0388 }
0389 
0390 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
0391 {
0392     int rc;
0393     u8 val;
0394 
0395     rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
0396                        val & PIO_DI_RDY, 10, MTK_TIMEOUT);
0397     if (rc < 0)
0398         dev_err(nfc->dev, "data not ready\n");
0399 }
0400 
0401 static inline u8 mtk_nfc_read_byte(struct nand_chip *chip)
0402 {
0403     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0404     u32 reg;
0405 
0406     /* after each byte read, the NFI_STA reg is reset by the hardware */
0407     reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
0408     if (reg != NFI_FSM_CUSTDATA) {
0409         reg = nfi_readw(nfc, NFI_CNFG);
0410         reg |= CNFG_BYTE_RW | CNFG_READ_EN;
0411         nfi_writew(nfc, reg, NFI_CNFG);
0412 
0413         /*
0414          * set to max sector to allow the HW to continue reading over
0415          * unaligned accesses
0416          */
0417         reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
0418         nfi_writel(nfc, reg, NFI_CON);
0419 
0420         /* trigger to fetch data */
0421         nfi_writew(nfc, STAR_EN, NFI_STRDATA);
0422     }
0423 
0424     mtk_nfc_wait_ioready(nfc);
0425 
0426     return nfi_readb(nfc, NFI_DATAR);
0427 }
0428 
0429 static void mtk_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
0430 {
0431     int i;
0432 
0433     for (i = 0; i < len; i++)
0434         buf[i] = mtk_nfc_read_byte(chip);
0435 }
0436 
0437 static void mtk_nfc_write_byte(struct nand_chip *chip, u8 byte)
0438 {
0439     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0440     u32 reg;
0441 
0442     reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
0443 
0444     if (reg != NFI_FSM_CUSTDATA) {
0445         reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
0446         nfi_writew(nfc, reg, NFI_CNFG);
0447 
0448         reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
0449         nfi_writel(nfc, reg, NFI_CON);
0450 
0451         nfi_writew(nfc, STAR_EN, NFI_STRDATA);
0452     }
0453 
0454     mtk_nfc_wait_ioready(nfc);
0455     nfi_writeb(nfc, byte, NFI_DATAW);
0456 }
0457 
0458 static void mtk_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
0459 {
0460     int i;
0461 
0462     for (i = 0; i < len; i++)
0463         mtk_nfc_write_byte(chip, buf[i]);
0464 }
0465 
0466 static int mtk_nfc_exec_instr(struct nand_chip *chip,
0467                   const struct nand_op_instr *instr)
0468 {
0469     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0470     unsigned int i;
0471     u32 status;
0472 
0473     switch (instr->type) {
0474     case NAND_OP_CMD_INSTR:
0475         mtk_nfc_send_command(nfc, instr->ctx.cmd.opcode);
0476         return 0;
0477     case NAND_OP_ADDR_INSTR:
0478         for (i = 0; i < instr->ctx.addr.naddrs; i++)
0479             mtk_nfc_send_address(nfc, instr->ctx.addr.addrs[i]);
0480         return 0;
0481     case NAND_OP_DATA_IN_INSTR:
0482         mtk_nfc_read_buf(chip, instr->ctx.data.buf.in,
0483                  instr->ctx.data.len);
0484         return 0;
0485     case NAND_OP_DATA_OUT_INSTR:
0486         mtk_nfc_write_buf(chip, instr->ctx.data.buf.out,
0487                   instr->ctx.data.len);
0488         return 0;
0489     case NAND_OP_WAITRDY_INSTR:
0490         return readl_poll_timeout(nfc->regs + NFI_STA, status,
0491                       !(status & STA_BUSY), 20,
0492                       instr->ctx.waitrdy.timeout_ms * 1000);
0493     default:
0494         break;
0495     }
0496 
0497     return -EINVAL;
0498 }
0499 
0500 static void mtk_nfc_select_target(struct nand_chip *nand, unsigned int cs)
0501 {
0502     struct mtk_nfc *nfc = nand_get_controller_data(nand);
0503     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
0504 
0505     mtk_nfc_hw_runtime_config(nand_to_mtd(nand));
0506 
0507     nfi_writel(nfc, mtk_nand->sels[cs], NFI_CSEL);
0508 }
0509 
0510 static int mtk_nfc_exec_op(struct nand_chip *chip,
0511                const struct nand_operation *op,
0512                bool check_only)
0513 {
0514     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0515     unsigned int i;
0516     int ret = 0;
0517 
0518     if (check_only)
0519         return 0;
0520 
0521     mtk_nfc_hw_reset(nfc);
0522     nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
0523     mtk_nfc_select_target(chip, op->cs);
0524 
0525     for (i = 0; i < op->ninstrs; i++) {
0526         ret = mtk_nfc_exec_instr(chip, &op->instrs[i]);
0527         if (ret)
0528             break;
0529     }
0530 
0531     return ret;
0532 }
0533 
0534 static int mtk_nfc_setup_interface(struct nand_chip *chip, int csline,
0535                    const struct nand_interface_config *conf)
0536 {
0537     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0538     const struct nand_sdr_timings *timings;
0539     u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
0540     u32 temp, tsel = 0;
0541 
0542     timings = nand_get_sdr_timings(conf);
0543     if (IS_ERR(timings))
0544         return -ENOTSUPP;
0545 
0546     if (csline == NAND_DATA_IFACE_CHECK_ONLY)
0547         return 0;
0548 
0549     rate = clk_get_rate(nfc->clk.nfi_clk);
0550     /* There is a frequency divider in some IPs */
0551     rate /= nfc->caps->nfi_clk_div;
0552 
0553     /* turn clock rate into KHZ */
0554     rate /= 1000;
0555 
0556     tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000;
0557     tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000);
0558     tpoecs &= 0xf;
0559 
0560     tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000;
0561     tprecs = DIV_ROUND_UP(tprecs * rate, 1000000);
0562     tprecs &= 0x3f;
0563 
0564     /* sdr interface has no tCR which means CE# low to RE# low */
0565     tc2r = 0;
0566 
0567     tw2r = timings->tWHR_min / 1000;
0568     tw2r = DIV_ROUND_UP(tw2r * rate, 1000000);
0569     tw2r = DIV_ROUND_UP(tw2r - 1, 2);
0570     tw2r &= 0xf;
0571 
0572     twh = max(timings->tREH_min, timings->tWH_min) / 1000;
0573     twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
0574     twh &= 0xf;
0575 
0576     /* Calculate real WE#/RE# hold time in nanosecond */
0577     temp = (twh + 1) * 1000000 / rate;
0578     /* nanosecond to picosecond */
0579     temp *= 1000;
0580 
0581     /*
0582      * WE# low level time should be expaned to meet WE# pulse time
0583      * and WE# cycle time at the same time.
0584      */
0585     if (temp < timings->tWC_min)
0586         twst = timings->tWC_min - temp;
0587     twst = max(timings->tWP_min, twst) / 1000;
0588     twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
0589     twst &= 0xf;
0590 
0591     /*
0592      * RE# low level time should be expaned to meet RE# pulse time
0593      * and RE# cycle time at the same time.
0594      */
0595     if (temp < timings->tRC_min)
0596         trlt = timings->tRC_min - temp;
0597     trlt = max(trlt, timings->tRP_min) / 1000;
0598     trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
0599     trlt &= 0xf;
0600 
0601     /* Calculate RE# pulse time in nanosecond. */
0602     temp = (trlt + 1) * 1000000 / rate;
0603     /* nanosecond to picosecond */
0604     temp *= 1000;
0605     /*
0606      * If RE# access time is bigger than RE# pulse time,
0607      * delay sampling data timing.
0608      */
0609     if (temp < timings->tREA_max) {
0610         tsel = timings->tREA_max / 1000;
0611         tsel = DIV_ROUND_UP(tsel * rate, 1000000);
0612         tsel -= (trlt + 1);
0613         if (tsel > MAX_STROBE_DLY) {
0614             trlt += tsel - MAX_STROBE_DLY;
0615             tsel = MAX_STROBE_DLY;
0616         }
0617     }
0618     temp = nfi_readl(nfc, NFI_DEBUG_CON1);
0619     temp &= ~STROBE_MASK;
0620     temp |= tsel << STROBE_SHIFT;
0621     nfi_writel(nfc, temp, NFI_DEBUG_CON1);
0622 
0623     /*
0624      * ACCON: access timing control register
0625      * -------------------------------------
0626      * 31:28: tpoecs, minimum required time for CS post pulling down after
0627      *        accessing the device
0628      * 27:22: tprecs, minimum required time for CS pre pulling down before
0629      *        accessing the device
0630      * 21:16: tc2r, minimum required time from NCEB low to NREB low
0631      * 15:12: tw2r, minimum required time from NWEB high to NREB low.
0632      * 11:08: twh, write enable hold time
0633      * 07:04: twst, write wait states
0634      * 03:00: trlt, read wait states
0635      */
0636     trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt);
0637     nfi_writel(nfc, trlt, NFI_ACCCON);
0638 
0639     return 0;
0640 }
0641 
0642 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
0643 {
0644     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0645     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0646     int size = chip->ecc.size + mtk_nand->fdm.reg_size;
0647 
0648     nfc->ecc_cfg.mode = ECC_DMA_MODE;
0649     nfc->ecc_cfg.op = ECC_ENCODE;
0650 
0651     return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
0652 }
0653 
0654 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c)
0655 {
0656     /* nop */
0657 }
0658 
0659 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw)
0660 {
0661     struct nand_chip *chip = mtd_to_nand(mtd);
0662     struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
0663     u32 bad_pos = nand->bad_mark.pos;
0664 
0665     if (raw)
0666         bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
0667     else
0668         bad_pos += nand->bad_mark.sec * chip->ecc.size;
0669 
0670     swap(chip->oob_poi[0], buf[bad_pos]);
0671 }
0672 
0673 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset,
0674                   u32 len, const u8 *buf)
0675 {
0676     struct nand_chip *chip = mtd_to_nand(mtd);
0677     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0678     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0679     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
0680     u32 start, end;
0681     int i, ret;
0682 
0683     start = offset / chip->ecc.size;
0684     end = DIV_ROUND_UP(offset + len, chip->ecc.size);
0685 
0686     memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
0687     for (i = 0; i < chip->ecc.steps; i++) {
0688         memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
0689                chip->ecc.size);
0690 
0691         if (start > i || i >= end)
0692             continue;
0693 
0694         if (i == mtk_nand->bad_mark.sec)
0695             mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
0696 
0697         memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
0698 
0699         /* program the CRC back to the OOB */
0700         ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i));
0701         if (ret < 0)
0702             return ret;
0703     }
0704 
0705     return 0;
0706 }
0707 
0708 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf)
0709 {
0710     struct nand_chip *chip = mtd_to_nand(mtd);
0711     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0712     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0713     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
0714     u32 i;
0715 
0716     memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
0717     for (i = 0; i < chip->ecc.steps; i++) {
0718         if (buf)
0719             memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
0720                    chip->ecc.size);
0721 
0722         if (i == mtk_nand->bad_mark.sec)
0723             mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
0724 
0725         memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
0726     }
0727 }
0728 
0729 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start,
0730                     u32 sectors)
0731 {
0732     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0733     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0734     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
0735     u32 vall, valm;
0736     u8 *oobptr;
0737     int i, j;
0738 
0739     for (i = 0; i < sectors; i++) {
0740         oobptr = oob_ptr(chip, start + i);
0741         vall = nfi_readl(nfc, NFI_FDML(i));
0742         valm = nfi_readl(nfc, NFI_FDMM(i));
0743 
0744         for (j = 0; j < fdm->reg_size; j++)
0745             oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
0746     }
0747 }
0748 
0749 static inline void mtk_nfc_write_fdm(struct nand_chip *chip)
0750 {
0751     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0752     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0753     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
0754     u32 vall, valm;
0755     u8 *oobptr;
0756     int i, j;
0757 
0758     for (i = 0; i < chip->ecc.steps; i++) {
0759         oobptr = oob_ptr(chip, i);
0760         vall = 0;
0761         valm = 0;
0762         for (j = 0; j < 8; j++) {
0763             if (j < 4)
0764                 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff)
0765                         << (j * 8);
0766             else
0767                 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff)
0768                         << ((j - 4) * 8);
0769         }
0770         nfi_writel(nfc, vall, NFI_FDML(i));
0771         nfi_writel(nfc, valm, NFI_FDMM(i));
0772     }
0773 }
0774 
0775 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip,
0776                  const u8 *buf, int page, int len)
0777 {
0778     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0779     struct device *dev = nfc->dev;
0780     dma_addr_t addr;
0781     u32 reg;
0782     int ret;
0783 
0784     addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE);
0785     ret = dma_mapping_error(nfc->dev, addr);
0786     if (ret) {
0787         dev_err(nfc->dev, "dma mapping error\n");
0788         return -EINVAL;
0789     }
0790 
0791     reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
0792     nfi_writew(nfc, reg, NFI_CNFG);
0793 
0794     nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
0795     nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
0796     nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
0797 
0798     init_completion(&nfc->done);
0799 
0800     reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
0801     nfi_writel(nfc, reg, NFI_CON);
0802     nfi_writew(nfc, STAR_EN, NFI_STRDATA);
0803 
0804     ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
0805     if (!ret) {
0806         dev_err(dev, "program ahb done timeout\n");
0807         nfi_writew(nfc, 0, NFI_INTR_EN);
0808         ret = -ETIMEDOUT;
0809         goto timeout;
0810     }
0811 
0812     ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
0813                     ADDRCNTR_SEC(reg) >= chip->ecc.steps,
0814                     10, MTK_TIMEOUT);
0815     if (ret)
0816         dev_err(dev, "hwecc write timeout\n");
0817 
0818 timeout:
0819 
0820     dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
0821     nfi_writel(nfc, 0, NFI_CON);
0822 
0823     return ret;
0824 }
0825 
0826 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
0827                   const u8 *buf, int page, int raw)
0828 {
0829     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0830     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0831     size_t len;
0832     const u8 *bufpoi;
0833     u32 reg;
0834     int ret;
0835 
0836     mtk_nfc_select_target(chip, chip->cur_cs);
0837     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0838 
0839     if (!raw) {
0840         /* OOB => FDM: from register,  ECC: from HW */
0841         reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
0842         nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
0843 
0844         nfc->ecc_cfg.op = ECC_ENCODE;
0845         nfc->ecc_cfg.mode = ECC_NFI_MODE;
0846         ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
0847         if (ret) {
0848             /* clear NFI config */
0849             reg = nfi_readw(nfc, NFI_CNFG);
0850             reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
0851             nfi_writew(nfc, reg, NFI_CNFG);
0852 
0853             return ret;
0854         }
0855 
0856         memcpy(nfc->buffer, buf, mtd->writesize);
0857         mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
0858         bufpoi = nfc->buffer;
0859 
0860         /* write OOB into the FDM registers (OOB area in MTK NAND) */
0861         mtk_nfc_write_fdm(chip);
0862     } else {
0863         bufpoi = buf;
0864     }
0865 
0866     len = mtd->writesize + (raw ? mtd->oobsize : 0);
0867     ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len);
0868 
0869     if (!raw)
0870         mtk_ecc_disable(nfc->ecc);
0871 
0872     if (ret)
0873         return ret;
0874 
0875     return nand_prog_page_end_op(chip);
0876 }
0877 
0878 static int mtk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
0879                     int oob_on, int page)
0880 {
0881     return mtk_nfc_write_page(nand_to_mtd(chip), chip, buf, page, 0);
0882 }
0883 
0884 static int mtk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf,
0885                   int oob_on, int pg)
0886 {
0887     struct mtd_info *mtd = nand_to_mtd(chip);
0888     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0889 
0890     mtk_nfc_format_page(mtd, buf);
0891     return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
0892 }
0893 
0894 static int mtk_nfc_write_subpage_hwecc(struct nand_chip *chip, u32 offset,
0895                        u32 data_len, const u8 *buf,
0896                        int oob_on, int page)
0897 {
0898     struct mtd_info *mtd = nand_to_mtd(chip);
0899     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0900     int ret;
0901 
0902     ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf);
0903     if (ret < 0)
0904         return ret;
0905 
0906     /* use the data in the private buffer (now with FDM and CRC) */
0907     return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
0908 }
0909 
0910 static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page)
0911 {
0912     return mtk_nfc_write_page_raw(chip, NULL, 1, page);
0913 }
0914 
0915 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
0916                     u32 sectors)
0917 {
0918     struct nand_chip *chip = mtd_to_nand(mtd);
0919     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0920     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0921     struct mtk_ecc_stats stats;
0922     u32 reg_size = mtk_nand->fdm.reg_size;
0923     int rc, i;
0924 
0925     rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
0926     if (rc) {
0927         memset(buf, 0xff, sectors * chip->ecc.size);
0928         for (i = 0; i < sectors; i++)
0929             memset(oob_ptr(chip, start + i), 0xff, reg_size);
0930         return 0;
0931     }
0932 
0933     mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
0934     mtd->ecc_stats.corrected += stats.corrected;
0935     mtd->ecc_stats.failed += stats.failed;
0936 
0937     return stats.bitflips;
0938 }
0939 
0940 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
0941                 u32 data_offs, u32 readlen,
0942                 u8 *bufpoi, int page, int raw)
0943 {
0944     struct mtk_nfc *nfc = nand_get_controller_data(chip);
0945     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
0946     u32 spare = mtk_nand->spare_per_sector;
0947     u32 column, sectors, start, end, reg;
0948     dma_addr_t addr;
0949     int bitflips = 0;
0950     size_t len;
0951     u8 *buf;
0952     int rc;
0953 
0954     mtk_nfc_select_target(chip, chip->cur_cs);
0955     start = data_offs / chip->ecc.size;
0956     end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
0957 
0958     sectors = end - start;
0959     column = start * (chip->ecc.size + spare);
0960 
0961     len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
0962     buf = bufpoi + start * chip->ecc.size;
0963 
0964     nand_read_page_op(chip, page, column, NULL, 0);
0965 
0966     addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
0967     rc = dma_mapping_error(nfc->dev, addr);
0968     if (rc) {
0969         dev_err(nfc->dev, "dma mapping error\n");
0970 
0971         return -EINVAL;
0972     }
0973 
0974     reg = nfi_readw(nfc, NFI_CNFG);
0975     reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
0976     if (!raw) {
0977         reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
0978         nfi_writew(nfc, reg, NFI_CNFG);
0979 
0980         nfc->ecc_cfg.mode = ECC_NFI_MODE;
0981         nfc->ecc_cfg.sectors = sectors;
0982         nfc->ecc_cfg.op = ECC_DECODE;
0983         rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
0984         if (rc) {
0985             dev_err(nfc->dev, "ecc enable\n");
0986             /* clear NFI_CNFG */
0987             reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
0988                 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
0989             nfi_writew(nfc, reg, NFI_CNFG);
0990             dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
0991 
0992             return rc;
0993         }
0994     } else {
0995         nfi_writew(nfc, reg, NFI_CNFG);
0996     }
0997 
0998     nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
0999     nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
1000     nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
1001 
1002     init_completion(&nfc->done);
1003     reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
1004     nfi_writel(nfc, reg, NFI_CON);
1005     nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1006 
1007     rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
1008     if (!rc)
1009         dev_warn(nfc->dev, "read ahb/dma done timeout\n");
1010 
1011     rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
1012                        ADDRCNTR_SEC(reg) >= sectors, 10,
1013                        MTK_TIMEOUT);
1014     if (rc < 0) {
1015         dev_err(nfc->dev, "subpage done timeout\n");
1016         bitflips = -EIO;
1017     } else if (!raw) {
1018         rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
1019         bitflips = rc < 0 ? -ETIMEDOUT :
1020             mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
1021         mtk_nfc_read_fdm(chip, start, sectors);
1022     }
1023 
1024     dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
1025 
1026     if (raw)
1027         goto done;
1028 
1029     mtk_ecc_disable(nfc->ecc);
1030 
1031     if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
1032         mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw);
1033 done:
1034     nfi_writel(nfc, 0, NFI_CON);
1035 
1036     return bitflips;
1037 }
1038 
1039 static int mtk_nfc_read_subpage_hwecc(struct nand_chip *chip, u32 off,
1040                       u32 len, u8 *p, int pg)
1041 {
1042     return mtk_nfc_read_subpage(nand_to_mtd(chip), chip, off, len, p, pg,
1043                     0);
1044 }
1045 
1046 static int mtk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *p, int oob_on,
1047                    int pg)
1048 {
1049     struct mtd_info *mtd = nand_to_mtd(chip);
1050 
1051     return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0);
1052 }
1053 
1054 static int mtk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on,
1055                  int page)
1056 {
1057     struct mtd_info *mtd = nand_to_mtd(chip);
1058     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1059     struct mtk_nfc *nfc = nand_get_controller_data(chip);
1060     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1061     int i, ret;
1062 
1063     memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1064     ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
1065                    page, 1);
1066     if (ret < 0)
1067         return ret;
1068 
1069     for (i = 0; i < chip->ecc.steps; i++) {
1070         memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
1071 
1072         if (i == mtk_nand->bad_mark.sec)
1073             mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1074 
1075         if (buf)
1076             memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
1077                    chip->ecc.size);
1078     }
1079 
1080     return ret;
1081 }
1082 
1083 static int mtk_nfc_read_oob_std(struct nand_chip *chip, int page)
1084 {
1085     return mtk_nfc_read_page_raw(chip, NULL, 1, page);
1086 }
1087 
1088 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1089 {
1090     /*
1091      * CNRNB: nand ready/busy register
1092      * -------------------------------
1093      * 7:4: timeout register for polling the NAND busy/ready signal
1094      * 0  : poll the status of the busy/ready signal after [7:4]*16 cycles.
1095      */
1096     nfi_writew(nfc, 0xf1, NFI_CNRNB);
1097     nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1098 
1099     mtk_nfc_hw_reset(nfc);
1100 
1101     nfi_readl(nfc, NFI_INTR_STA);
1102     nfi_writel(nfc, 0, NFI_INTR_EN);
1103 }
1104 
1105 static irqreturn_t mtk_nfc_irq(int irq, void *id)
1106 {
1107     struct mtk_nfc *nfc = id;
1108     u16 sta, ien;
1109 
1110     sta = nfi_readw(nfc, NFI_INTR_STA);
1111     ien = nfi_readw(nfc, NFI_INTR_EN);
1112 
1113     if (!(sta & ien))
1114         return IRQ_NONE;
1115 
1116     nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1117     complete(&nfc->done);
1118 
1119     return IRQ_HANDLED;
1120 }
1121 
1122 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1123 {
1124     int ret;
1125 
1126     ret = clk_prepare_enable(clk->nfi_clk);
1127     if (ret) {
1128         dev_err(dev, "failed to enable nfi clk\n");
1129         return ret;
1130     }
1131 
1132     ret = clk_prepare_enable(clk->pad_clk);
1133     if (ret) {
1134         dev_err(dev, "failed to enable pad clk\n");
1135         clk_disable_unprepare(clk->nfi_clk);
1136         return ret;
1137     }
1138 
1139     return 0;
1140 }
1141 
1142 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1143 {
1144     clk_disable_unprepare(clk->nfi_clk);
1145     clk_disable_unprepare(clk->pad_clk);
1146 }
1147 
1148 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1149                   struct mtd_oob_region *oob_region)
1150 {
1151     struct nand_chip *chip = mtd_to_nand(mtd);
1152     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1153     struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1154     u32 eccsteps;
1155 
1156     eccsteps = mtd->writesize / chip->ecc.size;
1157 
1158     if (section >= eccsteps)
1159         return -ERANGE;
1160 
1161     oob_region->length = fdm->reg_size - fdm->ecc_size;
1162     oob_region->offset = section * fdm->reg_size + fdm->ecc_size;
1163 
1164     return 0;
1165 }
1166 
1167 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1168                  struct mtd_oob_region *oob_region)
1169 {
1170     struct nand_chip *chip = mtd_to_nand(mtd);
1171     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1172     u32 eccsteps;
1173 
1174     if (section)
1175         return -ERANGE;
1176 
1177     eccsteps = mtd->writesize / chip->ecc.size;
1178     oob_region->offset = mtk_nand->fdm.reg_size * eccsteps;
1179     oob_region->length = mtd->oobsize - oob_region->offset;
1180 
1181     return 0;
1182 }
1183 
1184 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = {
1185     .free = mtk_nfc_ooblayout_free,
1186     .ecc = mtk_nfc_ooblayout_ecc,
1187 };
1188 
1189 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
1190 {
1191     struct nand_chip *nand = mtd_to_nand(mtd);
1192     struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
1193     struct mtk_nfc *nfc = nand_get_controller_data(nand);
1194     u32 ecc_bytes;
1195 
1196     ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
1197                  mtk_ecc_get_parity_bits(nfc->ecc), 8);
1198 
1199     fdm->reg_size = chip->spare_per_sector - ecc_bytes;
1200     if (fdm->reg_size > NFI_FDM_MAX_SIZE)
1201         fdm->reg_size = NFI_FDM_MAX_SIZE;
1202 
1203     /* bad block mark storage */
1204     fdm->ecc_size = 1;
1205 }
1206 
1207 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
1208                      struct mtd_info *mtd)
1209 {
1210     struct nand_chip *nand = mtd_to_nand(mtd);
1211 
1212     if (mtd->writesize == 512) {
1213         bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
1214     } else {
1215         bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
1216         bm_ctl->sec = mtd->writesize / mtk_data_len(nand);
1217         bm_ctl->pos = mtd->writesize % mtk_data_len(nand);
1218     }
1219 }
1220 
1221 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
1222 {
1223     struct nand_chip *nand = mtd_to_nand(mtd);
1224     struct mtk_nfc *nfc = nand_get_controller_data(nand);
1225     const u8 *spare = nfc->caps->spare_size;
1226     u32 eccsteps, i, closest_spare = 0;
1227 
1228     eccsteps = mtd->writesize / nand->ecc.size;
1229     *sps = mtd->oobsize / eccsteps;
1230 
1231     if (nand->ecc.size == 1024)
1232         *sps >>= 1;
1233 
1234     if (*sps < MTK_NFC_MIN_SPARE)
1235         return -EINVAL;
1236 
1237     for (i = 0; i < nfc->caps->num_spare_size; i++) {
1238         if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) {
1239             closest_spare = i;
1240             if (*sps == spare[i])
1241                 break;
1242         }
1243     }
1244 
1245     *sps = spare[closest_spare];
1246 
1247     if (nand->ecc.size == 1024)
1248         *sps <<= 1;
1249 
1250     return 0;
1251 }
1252 
1253 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
1254 {
1255     struct nand_chip *nand = mtd_to_nand(mtd);
1256     const struct nand_ecc_props *requirements =
1257         nanddev_get_ecc_requirements(&nand->base);
1258     struct mtk_nfc *nfc = nand_get_controller_data(nand);
1259     u32 spare;
1260     int free, ret;
1261 
1262     /* support only ecc hw mode */
1263     if (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
1264         dev_err(dev, "ecc.engine_type not supported\n");
1265         return -EINVAL;
1266     }
1267 
1268     /* if optional dt settings not present */
1269     if (!nand->ecc.size || !nand->ecc.strength) {
1270         /* use datasheet requirements */
1271         nand->ecc.strength = requirements->strength;
1272         nand->ecc.size = requirements->step_size;
1273 
1274         /*
1275          * align eccstrength and eccsize
1276          * this controller only supports 512 and 1024 sizes
1277          */
1278         if (nand->ecc.size < 1024) {
1279             if (mtd->writesize > 512 &&
1280                 nfc->caps->max_sector_size > 512) {
1281                 nand->ecc.size = 1024;
1282                 nand->ecc.strength <<= 1;
1283             } else {
1284                 nand->ecc.size = 512;
1285             }
1286         } else {
1287             nand->ecc.size = 1024;
1288         }
1289 
1290         ret = mtk_nfc_set_spare_per_sector(&spare, mtd);
1291         if (ret)
1292             return ret;
1293 
1294         /* calculate oob bytes except ecc parity data */
1295         free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
1296             + 7) >> 3;
1297         free = spare - free;
1298 
1299         /*
1300          * enhance ecc strength if oob left is bigger than max FDM size
1301          * or reduce ecc strength if oob size is not enough for ecc
1302          * parity data.
1303          */
1304         if (free > NFI_FDM_MAX_SIZE) {
1305             spare -= NFI_FDM_MAX_SIZE;
1306             nand->ecc.strength = (spare << 3) /
1307                          mtk_ecc_get_parity_bits(nfc->ecc);
1308         } else if (free < 0) {
1309             spare -= NFI_FDM_MIN_SIZE;
1310             nand->ecc.strength = (spare << 3) /
1311                          mtk_ecc_get_parity_bits(nfc->ecc);
1312         }
1313     }
1314 
1315     mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
1316 
1317     dev_info(dev, "eccsize %d eccstrength %d\n",
1318          nand->ecc.size, nand->ecc.strength);
1319 
1320     return 0;
1321 }
1322 
1323 static int mtk_nfc_attach_chip(struct nand_chip *chip)
1324 {
1325     struct mtd_info *mtd = nand_to_mtd(chip);
1326     struct device *dev = mtd->dev.parent;
1327     struct mtk_nfc *nfc = nand_get_controller_data(chip);
1328     struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1329     int len;
1330     int ret;
1331 
1332     if (chip->options & NAND_BUSWIDTH_16) {
1333         dev_err(dev, "16bits buswidth not supported");
1334         return -EINVAL;
1335     }
1336 
1337     /* store bbt magic in page, cause OOB is not protected */
1338     if (chip->bbt_options & NAND_BBT_USE_FLASH)
1339         chip->bbt_options |= NAND_BBT_NO_OOB;
1340 
1341     ret = mtk_nfc_ecc_init(dev, mtd);
1342     if (ret)
1343         return ret;
1344 
1345     ret = mtk_nfc_set_spare_per_sector(&mtk_nand->spare_per_sector, mtd);
1346     if (ret)
1347         return ret;
1348 
1349     mtk_nfc_set_fdm(&mtk_nand->fdm, mtd);
1350     mtk_nfc_set_bad_mark_ctl(&mtk_nand->bad_mark, mtd);
1351 
1352     len = mtd->writesize + mtd->oobsize;
1353     nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1354     if (!nfc->buffer)
1355         return  -ENOMEM;
1356 
1357     return 0;
1358 }
1359 
1360 static const struct nand_controller_ops mtk_nfc_controller_ops = {
1361     .attach_chip = mtk_nfc_attach_chip,
1362     .setup_interface = mtk_nfc_setup_interface,
1363     .exec_op = mtk_nfc_exec_op,
1364 };
1365 
1366 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1367                   struct device_node *np)
1368 {
1369     struct mtk_nfc_nand_chip *chip;
1370     struct nand_chip *nand;
1371     struct mtd_info *mtd;
1372     int nsels;
1373     u32 tmp;
1374     int ret;
1375     int i;
1376 
1377     if (!of_get_property(np, "reg", &nsels))
1378         return -ENODEV;
1379 
1380     nsels /= sizeof(u32);
1381     if (!nsels || nsels > MTK_NAND_MAX_NSELS) {
1382         dev_err(dev, "invalid reg property size %d\n", nsels);
1383         return -EINVAL;
1384     }
1385 
1386     chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8),
1387                 GFP_KERNEL);
1388     if (!chip)
1389         return -ENOMEM;
1390 
1391     chip->nsels = nsels;
1392     for (i = 0; i < nsels; i++) {
1393         ret = of_property_read_u32_index(np, "reg", i, &tmp);
1394         if (ret) {
1395             dev_err(dev, "reg property failure : %d\n", ret);
1396             return ret;
1397         }
1398 
1399         if (tmp >= MTK_NAND_MAX_NSELS) {
1400             dev_err(dev, "invalid CS: %u\n", tmp);
1401             return -EINVAL;
1402         }
1403 
1404         if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1405             dev_err(dev, "CS %u already assigned\n", tmp);
1406             return -EINVAL;
1407         }
1408 
1409         chip->sels[i] = tmp;
1410     }
1411 
1412     nand = &chip->nand;
1413     nand->controller = &nfc->controller;
1414 
1415     nand_set_flash_node(nand, np);
1416     nand_set_controller_data(nand, nfc);
1417 
1418     nand->options |= NAND_USES_DMA | NAND_SUBPAGE_READ;
1419 
1420     /* set default mode in case dt entry is missing */
1421     nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1422 
1423     nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1424     nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
1425     nand->ecc.write_page = mtk_nfc_write_page_hwecc;
1426     nand->ecc.write_oob_raw = mtk_nfc_write_oob_std;
1427     nand->ecc.write_oob = mtk_nfc_write_oob_std;
1428 
1429     nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1430     nand->ecc.read_page_raw = mtk_nfc_read_page_raw;
1431     nand->ecc.read_page = mtk_nfc_read_page_hwecc;
1432     nand->ecc.read_oob_raw = mtk_nfc_read_oob_std;
1433     nand->ecc.read_oob = mtk_nfc_read_oob_std;
1434 
1435     mtd = nand_to_mtd(nand);
1436     mtd->owner = THIS_MODULE;
1437     mtd->dev.parent = dev;
1438     mtd->name = MTK_NAME;
1439     mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops);
1440 
1441     mtk_nfc_hw_init(nfc);
1442 
1443     ret = nand_scan(nand, nsels);
1444     if (ret)
1445         return ret;
1446 
1447     ret = mtd_device_register(mtd, NULL, 0);
1448     if (ret) {
1449         dev_err(dev, "mtd parse partition error\n");
1450         nand_cleanup(nand);
1451         return ret;
1452     }
1453 
1454     list_add_tail(&chip->node, &nfc->chips);
1455 
1456     return 0;
1457 }
1458 
1459 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1460 {
1461     struct device_node *np = dev->of_node;
1462     struct device_node *nand_np;
1463     int ret;
1464 
1465     for_each_child_of_node(np, nand_np) {
1466         ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1467         if (ret) {
1468             of_node_put(nand_np);
1469             return ret;
1470         }
1471     }
1472 
1473     return 0;
1474 }
1475 
1476 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = {
1477     .spare_size = spare_size_mt2701,
1478     .num_spare_size = 16,
1479     .pageformat_spare_shift = 4,
1480     .nfi_clk_div = 1,
1481     .max_sector = 16,
1482     .max_sector_size = 1024,
1483 };
1484 
1485 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
1486     .spare_size = spare_size_mt2712,
1487     .num_spare_size = 19,
1488     .pageformat_spare_shift = 16,
1489     .nfi_clk_div = 2,
1490     .max_sector = 16,
1491     .max_sector_size = 1024,
1492 };
1493 
1494 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
1495     .spare_size = spare_size_mt7622,
1496     .num_spare_size = 4,
1497     .pageformat_spare_shift = 4,
1498     .nfi_clk_div = 1,
1499     .max_sector = 8,
1500     .max_sector_size = 512,
1501 };
1502 
1503 static const struct of_device_id mtk_nfc_id_table[] = {
1504     {
1505         .compatible = "mediatek,mt2701-nfc",
1506         .data = &mtk_nfc_caps_mt2701,
1507     }, {
1508         .compatible = "mediatek,mt2712-nfc",
1509         .data = &mtk_nfc_caps_mt2712,
1510     }, {
1511         .compatible = "mediatek,mt7622-nfc",
1512         .data = &mtk_nfc_caps_mt7622,
1513     },
1514     {}
1515 };
1516 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1517 
1518 static int mtk_nfc_probe(struct platform_device *pdev)
1519 {
1520     struct device *dev = &pdev->dev;
1521     struct device_node *np = dev->of_node;
1522     struct mtk_nfc *nfc;
1523     int ret, irq;
1524 
1525     nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1526     if (!nfc)
1527         return -ENOMEM;
1528 
1529     nand_controller_init(&nfc->controller);
1530     INIT_LIST_HEAD(&nfc->chips);
1531     nfc->controller.ops = &mtk_nfc_controller_ops;
1532 
1533     /* probe defer if not ready */
1534     nfc->ecc = of_mtk_ecc_get(np);
1535     if (IS_ERR(nfc->ecc))
1536         return PTR_ERR(nfc->ecc);
1537     else if (!nfc->ecc)
1538         return -ENODEV;
1539 
1540     nfc->caps = of_device_get_match_data(dev);
1541     nfc->dev = dev;
1542 
1543     nfc->regs = devm_platform_ioremap_resource(pdev, 0);
1544     if (IS_ERR(nfc->regs)) {
1545         ret = PTR_ERR(nfc->regs);
1546         goto release_ecc;
1547     }
1548 
1549     nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1550     if (IS_ERR(nfc->clk.nfi_clk)) {
1551         dev_err(dev, "no clk\n");
1552         ret = PTR_ERR(nfc->clk.nfi_clk);
1553         goto release_ecc;
1554     }
1555 
1556     nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1557     if (IS_ERR(nfc->clk.pad_clk)) {
1558         dev_err(dev, "no pad clk\n");
1559         ret = PTR_ERR(nfc->clk.pad_clk);
1560         goto release_ecc;
1561     }
1562 
1563     ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1564     if (ret)
1565         goto release_ecc;
1566 
1567     irq = platform_get_irq(pdev, 0);
1568     if (irq < 0) {
1569         ret = -EINVAL;
1570         goto clk_disable;
1571     }
1572 
1573     ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1574     if (ret) {
1575         dev_err(dev, "failed to request nfi irq\n");
1576         goto clk_disable;
1577     }
1578 
1579     ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1580     if (ret) {
1581         dev_err(dev, "failed to set dma mask\n");
1582         goto clk_disable;
1583     }
1584 
1585     platform_set_drvdata(pdev, nfc);
1586 
1587     ret = mtk_nfc_nand_chips_init(dev, nfc);
1588     if (ret) {
1589         dev_err(dev, "failed to init nand chips\n");
1590         goto clk_disable;
1591     }
1592 
1593     return 0;
1594 
1595 clk_disable:
1596     mtk_nfc_disable_clk(&nfc->clk);
1597 
1598 release_ecc:
1599     mtk_ecc_release(nfc->ecc);
1600 
1601     return ret;
1602 }
1603 
1604 static int mtk_nfc_remove(struct platform_device *pdev)
1605 {
1606     struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1607     struct mtk_nfc_nand_chip *mtk_chip;
1608     struct nand_chip *chip;
1609     int ret;
1610 
1611     while (!list_empty(&nfc->chips)) {
1612         mtk_chip = list_first_entry(&nfc->chips,
1613                         struct mtk_nfc_nand_chip, node);
1614         chip = &mtk_chip->nand;
1615         ret = mtd_device_unregister(nand_to_mtd(chip));
1616         WARN_ON(ret);
1617         nand_cleanup(chip);
1618         list_del(&mtk_chip->node);
1619     }
1620 
1621     mtk_ecc_release(nfc->ecc);
1622     mtk_nfc_disable_clk(&nfc->clk);
1623 
1624     return 0;
1625 }
1626 
1627 #ifdef CONFIG_PM_SLEEP
1628 static int mtk_nfc_suspend(struct device *dev)
1629 {
1630     struct mtk_nfc *nfc = dev_get_drvdata(dev);
1631 
1632     mtk_nfc_disable_clk(&nfc->clk);
1633 
1634     return 0;
1635 }
1636 
1637 static int mtk_nfc_resume(struct device *dev)
1638 {
1639     struct mtk_nfc *nfc = dev_get_drvdata(dev);
1640     struct mtk_nfc_nand_chip *chip;
1641     struct nand_chip *nand;
1642     int ret;
1643     u32 i;
1644 
1645     udelay(200);
1646 
1647     ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1648     if (ret)
1649         return ret;
1650 
1651     /* reset NAND chip if VCC was powered off */
1652     list_for_each_entry(chip, &nfc->chips, node) {
1653         nand = &chip->nand;
1654         for (i = 0; i < chip->nsels; i++)
1655             nand_reset(nand, i);
1656     }
1657 
1658     return 0;
1659 }
1660 
1661 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1662 #endif
1663 
1664 static struct platform_driver mtk_nfc_driver = {
1665     .probe  = mtk_nfc_probe,
1666     .remove = mtk_nfc_remove,
1667     .driver = {
1668         .name  = MTK_NAME,
1669         .of_match_table = mtk_nfc_id_table,
1670 #ifdef CONFIG_PM_SLEEP
1671         .pm = &mtk_nfc_pm_ops,
1672 #endif
1673     },
1674 };
1675 
1676 module_platform_driver(mtk_nfc_driver);
1677 
1678 MODULE_LICENSE("Dual MIT/GPL");
1679 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1680 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");
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