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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * Amlogic Meson Nand Flash Controller Driver
0004  *
0005  * Copyright (c) 2018 Amlogic, inc.
0006  * Author: Liang Yang <liang.yang@amlogic.com>
0007  */
0008 
0009 #include <linux/platform_device.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/clk.h>
0013 #include <linux/mtd/rawnand.h>
0014 #include <linux/mtd/mtd.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/regmap.h>
0017 #include <linux/slab.h>
0018 #include <linux/module.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/of.h>
0021 #include <linux/of_device.h>
0022 #include <linux/sched/task_stack.h>
0023 
0024 #define NFC_REG_CMD     0x00
0025 #define NFC_CMD_IDLE        (0xc << 14)
0026 #define NFC_CMD_CLE     (0x5 << 14)
0027 #define NFC_CMD_ALE     (0x6 << 14)
0028 #define NFC_CMD_ADL     ((0 << 16) | (3 << 20))
0029 #define NFC_CMD_ADH     ((1 << 16) | (3 << 20))
0030 #define NFC_CMD_AIL     ((2 << 16) | (3 << 20))
0031 #define NFC_CMD_AIH     ((3 << 16) | (3 << 20))
0032 #define NFC_CMD_SEED        ((8 << 16) | (3 << 20))
0033 #define NFC_CMD_M2N     ((0 << 17) | (2 << 20))
0034 #define NFC_CMD_N2M     ((1 << 17) | (2 << 20))
0035 #define NFC_CMD_RB      BIT(20)
0036 #define NFC_CMD_SCRAMBLER_ENABLE    BIT(19)
0037 #define NFC_CMD_SCRAMBLER_DISABLE   0
0038 #define NFC_CMD_SHORTMODE_DISABLE   0
0039 #define NFC_CMD_RB_INT      BIT(14)
0040 
0041 #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))
0042 
0043 #define NFC_REG_CFG     0x04
0044 #define NFC_REG_DADR        0x08
0045 #define NFC_REG_IADR        0x0c
0046 #define NFC_REG_BUF     0x10
0047 #define NFC_REG_INFO        0x14
0048 #define NFC_REG_DC      0x18
0049 #define NFC_REG_ADR     0x1c
0050 #define NFC_REG_DL      0x20
0051 #define NFC_REG_DH      0x24
0052 #define NFC_REG_CADR        0x28
0053 #define NFC_REG_SADR        0x2c
0054 #define NFC_REG_PINS        0x30
0055 #define NFC_REG_VER     0x38
0056 
0057 #define NFC_RB_IRQ_EN       BIT(21)
0058 
0059 #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages)   \
0060     (                               \
0061         (cmd_dir)           |           \
0062         ((ran) << 19)           |           \
0063         ((bch) << 14)           |           \
0064         ((short_mode) << 13)        |           \
0065         (((page_size) & 0x7f) << 6) |           \
0066         ((pages) & 0x3f)                    \
0067     )
0068 
0069 #define GENCMDDADDRL(adl, addr)     ((adl) | ((addr) & 0xffff))
0070 #define GENCMDDADDRH(adh, addr)     ((adh) | (((addr) >> 16) & 0xffff))
0071 #define GENCMDIADDRL(ail, addr)     ((ail) | ((addr) & 0xffff))
0072 #define GENCMDIADDRH(aih, addr)     ((aih) | (((addr) >> 16) & 0xffff))
0073 
0074 #define DMA_DIR(dir)        ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
0075 
0076 #define ECC_CHECK_RETURN_FF (-1)
0077 
0078 #define NAND_CE0        (0xe << 10)
0079 #define NAND_CE1        (0xd << 10)
0080 
0081 #define DMA_BUSY_TIMEOUT    0x100000
0082 #define CMD_FIFO_EMPTY_TIMEOUT  1000
0083 
0084 #define MAX_CE_NUM      2
0085 
0086 /* eMMC clock register, misc control */
0087 #define CLK_SELECT_NAND     BIT(31)
0088 
0089 #define NFC_CLK_CYCLE       6
0090 
0091 /* nand flash controller delay 3 ns */
0092 #define NFC_DEFAULT_DELAY   3000
0093 
0094 #define ROW_ADDER(page, index)  (((page) >> (8 * (index))) & 0xff)
0095 #define MAX_CYCLE_ADDRS     5
0096 #define DIRREAD         1
0097 #define DIRWRITE        0
0098 
0099 #define ECC_PARITY_BCH8_512B    14
0100 #define ECC_COMPLETE            BIT(31)
0101 #define ECC_ERR_CNT(x)      (((x) >> 24) & GENMASK(5, 0))
0102 #define ECC_ZERO_CNT(x)     (((x) >> 16) & GENMASK(5, 0))
0103 #define ECC_UNCORRECTABLE   0x3f
0104 
0105 #define PER_INFO_BYTE       8
0106 
0107 struct meson_nfc_nand_chip {
0108     struct list_head node;
0109     struct nand_chip nand;
0110     unsigned long clk_rate;
0111     unsigned long level1_divider;
0112     u32 bus_timing;
0113     u32 twb;
0114     u32 tadl;
0115     u32 tbers_max;
0116 
0117     u32 bch_mode;
0118     u8 *data_buf;
0119     __le64 *info_buf;
0120     u32 nsels;
0121     u8 sels[];
0122 };
0123 
0124 struct meson_nand_ecc {
0125     u32 bch;
0126     u32 strength;
0127 };
0128 
0129 struct meson_nfc_data {
0130     const struct nand_ecc_caps *ecc_caps;
0131 };
0132 
0133 struct meson_nfc_param {
0134     u32 chip_select;
0135     u32 rb_select;
0136 };
0137 
0138 struct nand_rw_cmd {
0139     u32 cmd0;
0140     u32 addrs[MAX_CYCLE_ADDRS];
0141     u32 cmd1;
0142 };
0143 
0144 struct nand_timing {
0145     u32 twb;
0146     u32 tadl;
0147     u32 tbers_max;
0148 };
0149 
0150 struct meson_nfc {
0151     struct nand_controller controller;
0152     struct clk *core_clk;
0153     struct clk *device_clk;
0154     struct clk *phase_tx;
0155     struct clk *phase_rx;
0156 
0157     unsigned long clk_rate;
0158     u32 bus_timing;
0159 
0160     struct device *dev;
0161     void __iomem *reg_base;
0162     struct regmap *reg_clk;
0163     struct completion completion;
0164     struct list_head chips;
0165     const struct meson_nfc_data *data;
0166     struct meson_nfc_param param;
0167     struct nand_timing timing;
0168     union {
0169         int cmd[32];
0170         struct nand_rw_cmd rw;
0171     } cmdfifo;
0172 
0173     dma_addr_t daddr;
0174     dma_addr_t iaddr;
0175 
0176     unsigned long assigned_cs;
0177 };
0178 
0179 enum {
0180     NFC_ECC_BCH8_1K     = 2,
0181     NFC_ECC_BCH24_1K,
0182     NFC_ECC_BCH30_1K,
0183     NFC_ECC_BCH40_1K,
0184     NFC_ECC_BCH50_1K,
0185     NFC_ECC_BCH60_1K,
0186 };
0187 
0188 #define MESON_ECC_DATA(b, s)    { .bch = (b),   .strength = (s)}
0189 
0190 static struct meson_nand_ecc meson_ecc[] = {
0191     MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8),
0192     MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24),
0193     MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30),
0194     MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40),
0195     MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50),
0196     MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60),
0197 };
0198 
0199 static int meson_nand_calc_ecc_bytes(int step_size, int strength)
0200 {
0201     int ecc_bytes;
0202 
0203     if (step_size == 512 && strength == 8)
0204         return ECC_PARITY_BCH8_512B;
0205 
0206     ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8);
0207     ecc_bytes = ALIGN(ecc_bytes, 2);
0208 
0209     return ecc_bytes;
0210 }
0211 
0212 NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps,
0213              meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60);
0214 NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps,
0215              meson_nand_calc_ecc_bytes, 1024, 8);
0216 
0217 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand)
0218 {
0219     return container_of(nand, struct meson_nfc_nand_chip, nand);
0220 }
0221 
0222 static void meson_nfc_select_chip(struct nand_chip *nand, int chip)
0223 {
0224     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0225     struct meson_nfc *nfc = nand_get_controller_data(nand);
0226     int ret, value;
0227 
0228     if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
0229         return;
0230 
0231     nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
0232     nfc->param.rb_select = nfc->param.chip_select;
0233     nfc->timing.twb = meson_chip->twb;
0234     nfc->timing.tadl = meson_chip->tadl;
0235     nfc->timing.tbers_max = meson_chip->tbers_max;
0236 
0237     if (nfc->clk_rate != meson_chip->clk_rate) {
0238         ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
0239         if (ret) {
0240             dev_err(nfc->dev, "failed to set clock rate\n");
0241             return;
0242         }
0243         nfc->clk_rate = meson_chip->clk_rate;
0244     }
0245     if (nfc->bus_timing != meson_chip->bus_timing) {
0246         value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
0247         writel(value, nfc->reg_base + NFC_REG_CFG);
0248         writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
0249         nfc->bus_timing =  meson_chip->bus_timing;
0250     }
0251 }
0252 
0253 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
0254 {
0255     writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
0256            nfc->reg_base + NFC_REG_CMD);
0257 }
0258 
0259 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
0260 {
0261     writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
0262            nfc->reg_base + NFC_REG_CMD);
0263 }
0264 
0265 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
0266                  int scrambler)
0267 {
0268     struct mtd_info *mtd = nand_to_mtd(nand);
0269     struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
0270     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0271     u32 bch = meson_chip->bch_mode, cmd;
0272     int len = mtd->writesize, pagesize, pages;
0273 
0274     pagesize = nand->ecc.size;
0275 
0276     if (raw) {
0277         len = mtd->writesize + mtd->oobsize;
0278         cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir);
0279         writel(cmd, nfc->reg_base + NFC_REG_CMD);
0280         return;
0281     }
0282 
0283     pages = len / nand->ecc.size;
0284 
0285     cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
0286                NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
0287 
0288     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0289 }
0290 
0291 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
0292 {
0293     /*
0294      * Insert two commands to make sure all valid commands are finished.
0295      *
0296      * The Nand flash controller is designed as two stages pipleline -
0297      *  a) fetch and b) excute.
0298      * There might be cases when the driver see command queue is empty,
0299      * but the Nand flash controller still has two commands buffered,
0300      * one is fetched into NFC request queue (ready to run), and another
0301      * is actively executing. So pushing 2 "IDLE" commands guarantees that
0302      * the pipeline is emptied.
0303      */
0304     meson_nfc_cmd_idle(nfc, 0);
0305     meson_nfc_cmd_idle(nfc, 0);
0306 }
0307 
0308 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
0309                      unsigned int timeout_ms)
0310 {
0311     u32 cmd_size = 0;
0312     int ret;
0313 
0314     /* wait cmd fifo is empty */
0315     ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
0316                      !NFC_CMD_GET_SIZE(cmd_size),
0317                      10, timeout_ms * 1000);
0318     if (ret)
0319         dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
0320 
0321     return ret;
0322 }
0323 
0324 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
0325 {
0326     meson_nfc_drain_cmd(nfc);
0327 
0328     return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
0329 }
0330 
0331 static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i)
0332 {
0333     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0334     int len;
0335 
0336     len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i;
0337 
0338     return meson_chip->data_buf + len;
0339 }
0340 
0341 static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i)
0342 {
0343     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0344     int len, temp;
0345 
0346     temp = nand->ecc.size + nand->ecc.bytes;
0347     len = (temp + 2) * i;
0348 
0349     return meson_chip->data_buf + len;
0350 }
0351 
0352 static void meson_nfc_get_data_oob(struct nand_chip *nand,
0353                    u8 *buf, u8 *oobbuf)
0354 {
0355     int i, oob_len = 0;
0356     u8 *dsrc, *osrc;
0357 
0358     oob_len = nand->ecc.bytes + 2;
0359     for (i = 0; i < nand->ecc.steps; i++) {
0360         if (buf) {
0361             dsrc = meson_nfc_data_ptr(nand, i);
0362             memcpy(buf, dsrc, nand->ecc.size);
0363             buf += nand->ecc.size;
0364         }
0365         osrc = meson_nfc_oob_ptr(nand, i);
0366         memcpy(oobbuf, osrc, oob_len);
0367         oobbuf += oob_len;
0368     }
0369 }
0370 
0371 static void meson_nfc_set_data_oob(struct nand_chip *nand,
0372                    const u8 *buf, u8 *oobbuf)
0373 {
0374     int i, oob_len = 0;
0375     u8 *dsrc, *osrc;
0376 
0377     oob_len = nand->ecc.bytes + 2;
0378     for (i = 0; i < nand->ecc.steps; i++) {
0379         if (buf) {
0380             dsrc = meson_nfc_data_ptr(nand, i);
0381             memcpy(dsrc, buf, nand->ecc.size);
0382             buf += nand->ecc.size;
0383         }
0384         osrc = meson_nfc_oob_ptr(nand, i);
0385         memcpy(osrc, oobbuf, oob_len);
0386         oobbuf += oob_len;
0387     }
0388 }
0389 
0390 static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
0391 {
0392     u32 cmd, cfg;
0393     int ret = 0;
0394 
0395     meson_nfc_cmd_idle(nfc, nfc->timing.twb);
0396     meson_nfc_drain_cmd(nfc);
0397     meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
0398 
0399     cfg = readl(nfc->reg_base + NFC_REG_CFG);
0400     cfg |= NFC_RB_IRQ_EN;
0401     writel(cfg, nfc->reg_base + NFC_REG_CFG);
0402 
0403     reinit_completion(&nfc->completion);
0404 
0405     /* use the max erase time as the maximum clock for waiting R/B */
0406     cmd = NFC_CMD_RB | NFC_CMD_RB_INT
0407         | nfc->param.chip_select | nfc->timing.tbers_max;
0408     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0409 
0410     ret = wait_for_completion_timeout(&nfc->completion,
0411                       msecs_to_jiffies(timeout_ms));
0412     if (ret == 0)
0413         ret = -1;
0414 
0415     return ret;
0416 }
0417 
0418 static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
0419 {
0420     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0421     __le64 *info;
0422     int i, count;
0423 
0424     for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
0425         info = &meson_chip->info_buf[i];
0426         *info |= oob_buf[count];
0427         *info |= oob_buf[count + 1] << 8;
0428     }
0429 }
0430 
0431 static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)
0432 {
0433     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0434     __le64 *info;
0435     int i, count;
0436 
0437     for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
0438         info = &meson_chip->info_buf[i];
0439         oob_buf[count] = *info;
0440         oob_buf[count + 1] = *info >> 8;
0441     }
0442 }
0443 
0444 static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
0445                  u64 *correct_bitmap)
0446 {
0447     struct mtd_info *mtd = nand_to_mtd(nand);
0448     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0449     __le64 *info;
0450     int ret = 0, i;
0451 
0452     for (i = 0; i < nand->ecc.steps; i++) {
0453         info = &meson_chip->info_buf[i];
0454         if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
0455             mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
0456             *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
0457             *correct_bitmap |= 1 >> i;
0458             continue;
0459         }
0460         if ((nand->options & NAND_NEED_SCRAMBLING) &&
0461             ECC_ZERO_CNT(*info) < nand->ecc.strength) {
0462             mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info);
0463             *bitflips = max_t(u32, *bitflips,
0464                       ECC_ZERO_CNT(*info));
0465             ret = ECC_CHECK_RETURN_FF;
0466         } else {
0467             ret = -EBADMSG;
0468         }
0469     }
0470     return ret;
0471 }
0472 
0473 static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf,
0474                       int datalen, void *infobuf, int infolen,
0475                       enum dma_data_direction dir)
0476 {
0477     struct meson_nfc *nfc = nand_get_controller_data(nand);
0478     u32 cmd;
0479     int ret = 0;
0480 
0481     nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
0482     ret = dma_mapping_error(nfc->dev, nfc->daddr);
0483     if (ret) {
0484         dev_err(nfc->dev, "DMA mapping error\n");
0485         return ret;
0486     }
0487     cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
0488     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0489 
0490     cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
0491     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0492 
0493     if (infobuf) {
0494         nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
0495         ret = dma_mapping_error(nfc->dev, nfc->iaddr);
0496         if (ret) {
0497             dev_err(nfc->dev, "DMA mapping error\n");
0498             dma_unmap_single(nfc->dev,
0499                      nfc->daddr, datalen, dir);
0500             return ret;
0501         }
0502         cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
0503         writel(cmd, nfc->reg_base + NFC_REG_CMD);
0504 
0505         cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
0506         writel(cmd, nfc->reg_base + NFC_REG_CMD);
0507     }
0508 
0509     return ret;
0510 }
0511 
0512 static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
0513                      int datalen, int infolen,
0514                      enum dma_data_direction dir)
0515 {
0516     struct meson_nfc *nfc = nand_get_controller_data(nand);
0517 
0518     dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
0519     if (infolen)
0520         dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
0521 }
0522 
0523 static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
0524 {
0525     struct meson_nfc *nfc = nand_get_controller_data(nand);
0526     int ret = 0;
0527     u32 cmd;
0528     u8 *info;
0529 
0530     info = kzalloc(PER_INFO_BYTE, GFP_KERNEL);
0531     if (!info)
0532         return -ENOMEM;
0533 
0534     ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
0535                      PER_INFO_BYTE, DMA_FROM_DEVICE);
0536     if (ret)
0537         goto out;
0538 
0539     cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
0540     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0541 
0542     meson_nfc_drain_cmd(nfc);
0543     meson_nfc_wait_cmd_finish(nfc, 1000);
0544     meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE);
0545 
0546 out:
0547     kfree(info);
0548 
0549     return ret;
0550 }
0551 
0552 static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
0553 {
0554     struct meson_nfc *nfc = nand_get_controller_data(nand);
0555     int ret = 0;
0556     u32 cmd;
0557 
0558     ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL,
0559                      0, DMA_TO_DEVICE);
0560     if (ret)
0561         return ret;
0562 
0563     cmd = NFC_CMD_M2N | (len & GENMASK(5, 0));
0564     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0565 
0566     meson_nfc_drain_cmd(nfc);
0567     meson_nfc_wait_cmd_finish(nfc, 1000);
0568     meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE);
0569 
0570     return ret;
0571 }
0572 
0573 static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
0574                         int page, bool in)
0575 {
0576     const struct nand_sdr_timings *sdr =
0577         nand_get_sdr_timings(nand_get_interface_config(nand));
0578     struct mtd_info *mtd = nand_to_mtd(nand);
0579     struct meson_nfc *nfc = nand_get_controller_data(nand);
0580     u32 *addrs = nfc->cmdfifo.rw.addrs;
0581     u32 cs = nfc->param.chip_select;
0582     u32 cmd0, cmd_num, row_start;
0583     int i;
0584 
0585     cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int);
0586 
0587     cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
0588     nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
0589 
0590     addrs[0] = cs | NFC_CMD_ALE | 0;
0591     if (mtd->writesize <= 512) {
0592         cmd_num--;
0593         row_start = 1;
0594     } else {
0595         addrs[1] = cs | NFC_CMD_ALE | 0;
0596         row_start = 2;
0597     }
0598 
0599     addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0);
0600     addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1);
0601 
0602     if (nand->options & NAND_ROW_ADDR_3)
0603         addrs[row_start + 2] =
0604             cs | NFC_CMD_ALE | ROW_ADDER(page, 2);
0605     else
0606         cmd_num--;
0607 
0608     /* subtract cmd1 */
0609     cmd_num--;
0610 
0611     for (i = 0; i < cmd_num; i++)
0612         writel_relaxed(nfc->cmdfifo.cmd[i],
0613                    nfc->reg_base + NFC_REG_CMD);
0614 
0615     if (in) {
0616         nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
0617         writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
0618         meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max));
0619     } else {
0620         meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
0621     }
0622 
0623     return 0;
0624 }
0625 
0626 static int meson_nfc_write_page_sub(struct nand_chip *nand,
0627                     int page, int raw)
0628 {
0629     const struct nand_sdr_timings *sdr =
0630         nand_get_sdr_timings(nand_get_interface_config(nand));
0631     struct mtd_info *mtd = nand_to_mtd(nand);
0632     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0633     struct meson_nfc *nfc = nand_get_controller_data(nand);
0634     int data_len, info_len;
0635     u32 cmd;
0636     int ret;
0637 
0638     meson_nfc_select_chip(nand, nand->cur_cs);
0639 
0640     data_len =  mtd->writesize + mtd->oobsize;
0641     info_len = nand->ecc.steps * PER_INFO_BYTE;
0642 
0643     ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE);
0644     if (ret)
0645         return ret;
0646 
0647     ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
0648                      data_len, meson_chip->info_buf,
0649                      info_len, DMA_TO_DEVICE);
0650     if (ret)
0651         return ret;
0652 
0653     if (nand->options & NAND_NEED_SCRAMBLING) {
0654         meson_nfc_cmd_seed(nfc, page);
0655         meson_nfc_cmd_access(nand, raw, DIRWRITE,
0656                      NFC_CMD_SCRAMBLER_ENABLE);
0657     } else {
0658         meson_nfc_cmd_access(nand, raw, DIRWRITE,
0659                      NFC_CMD_SCRAMBLER_DISABLE);
0660     }
0661 
0662     cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
0663     writel(cmd, nfc->reg_base + NFC_REG_CMD);
0664     meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max));
0665 
0666     meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE);
0667 
0668     return ret;
0669 }
0670 
0671 static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf,
0672                     int oob_required, int page)
0673 {
0674     u8 *oob_buf = nand->oob_poi;
0675 
0676     meson_nfc_set_data_oob(nand, buf, oob_buf);
0677 
0678     return meson_nfc_write_page_sub(nand, page, 1);
0679 }
0680 
0681 static int meson_nfc_write_page_hwecc(struct nand_chip *nand,
0682                       const u8 *buf, int oob_required, int page)
0683 {
0684     struct mtd_info *mtd = nand_to_mtd(nand);
0685     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0686     u8 *oob_buf = nand->oob_poi;
0687 
0688     memcpy(meson_chip->data_buf, buf, mtd->writesize);
0689     memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
0690     meson_nfc_set_user_byte(nand, oob_buf);
0691 
0692     return meson_nfc_write_page_sub(nand, page, 0);
0693 }
0694 
0695 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
0696                         struct nand_chip *nand, int raw)
0697 {
0698     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0699     __le64 *info;
0700     u32 neccpages;
0701     int ret;
0702 
0703     neccpages = raw ? 1 : nand->ecc.steps;
0704     info = &meson_chip->info_buf[neccpages - 1];
0705     do {
0706         usleep_range(10, 15);
0707         /* info is updated by nfc dma engine*/
0708         smp_rmb();
0709         ret = *info & ECC_COMPLETE;
0710     } while (!ret);
0711 }
0712 
0713 static int meson_nfc_read_page_sub(struct nand_chip *nand,
0714                    int page, int raw)
0715 {
0716     struct mtd_info *mtd = nand_to_mtd(nand);
0717     struct meson_nfc *nfc = nand_get_controller_data(nand);
0718     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0719     int data_len, info_len;
0720     int ret;
0721 
0722     meson_nfc_select_chip(nand, nand->cur_cs);
0723 
0724     data_len =  mtd->writesize + mtd->oobsize;
0725     info_len = nand->ecc.steps * PER_INFO_BYTE;
0726 
0727     ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD);
0728     if (ret)
0729         return ret;
0730 
0731     ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
0732                      data_len, meson_chip->info_buf,
0733                      info_len, DMA_FROM_DEVICE);
0734     if (ret)
0735         return ret;
0736 
0737     if (nand->options & NAND_NEED_SCRAMBLING) {
0738         meson_nfc_cmd_seed(nfc, page);
0739         meson_nfc_cmd_access(nand, raw, DIRREAD,
0740                      NFC_CMD_SCRAMBLER_ENABLE);
0741     } else {
0742         meson_nfc_cmd_access(nand, raw, DIRREAD,
0743                      NFC_CMD_SCRAMBLER_DISABLE);
0744     }
0745 
0746     ret = meson_nfc_wait_dma_finish(nfc);
0747     meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
0748 
0749     meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE);
0750 
0751     return ret;
0752 }
0753 
0754 static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf,
0755                    int oob_required, int page)
0756 {
0757     u8 *oob_buf = nand->oob_poi;
0758     int ret;
0759 
0760     ret = meson_nfc_read_page_sub(nand, page, 1);
0761     if (ret)
0762         return ret;
0763 
0764     meson_nfc_get_data_oob(nand, buf, oob_buf);
0765 
0766     return 0;
0767 }
0768 
0769 static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
0770                      int oob_required, int page)
0771 {
0772     struct mtd_info *mtd = nand_to_mtd(nand);
0773     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0774     struct nand_ecc_ctrl *ecc = &nand->ecc;
0775     u64 correct_bitmap = 0;
0776     u32 bitflips = 0;
0777     u8 *oob_buf = nand->oob_poi;
0778     int ret, i;
0779 
0780     ret = meson_nfc_read_page_sub(nand, page, 0);
0781     if (ret)
0782         return ret;
0783 
0784     meson_nfc_get_user_byte(nand, oob_buf);
0785     ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap);
0786     if (ret == ECC_CHECK_RETURN_FF) {
0787         if (buf)
0788             memset(buf, 0xff, mtd->writesize);
0789         memset(oob_buf, 0xff, mtd->oobsize);
0790     } else if (ret < 0) {
0791         if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) {
0792             mtd->ecc_stats.failed++;
0793             return bitflips;
0794         }
0795         ret  = meson_nfc_read_page_raw(nand, buf, 0, page);
0796         if (ret)
0797             return ret;
0798 
0799         for (i = 0; i < nand->ecc.steps ; i++) {
0800             u8 *data = buf + i * ecc->size;
0801             u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
0802 
0803             if (correct_bitmap & (1 << i))
0804                 continue;
0805             ret = nand_check_erased_ecc_chunk(data, ecc->size,
0806                               oob, ecc->bytes + 2,
0807                               NULL, 0,
0808                               ecc->strength);
0809             if (ret < 0) {
0810                 mtd->ecc_stats.failed++;
0811             } else {
0812                 mtd->ecc_stats.corrected += ret;
0813                 bitflips =  max_t(u32, bitflips, ret);
0814             }
0815         }
0816     } else if (buf && buf != meson_chip->data_buf) {
0817         memcpy(buf, meson_chip->data_buf, mtd->writesize);
0818     }
0819 
0820     return bitflips;
0821 }
0822 
0823 static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page)
0824 {
0825     return meson_nfc_read_page_raw(nand, NULL, 1, page);
0826 }
0827 
0828 static int meson_nfc_read_oob(struct nand_chip *nand, int page)
0829 {
0830     return meson_nfc_read_page_hwecc(nand, NULL, 1, page);
0831 }
0832 
0833 static bool meson_nfc_is_buffer_dma_safe(const void *buffer)
0834 {
0835     if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer)))
0836         return true;
0837     return false;
0838 }
0839 
0840 static void *
0841 meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr)
0842 {
0843     if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR))
0844         return NULL;
0845 
0846     if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in))
0847         return instr->ctx.data.buf.in;
0848 
0849     return kzalloc(instr->ctx.data.len, GFP_KERNEL);
0850 }
0851 
0852 static void
0853 meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr,
0854                      void *buf)
0855 {
0856     if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) ||
0857         WARN_ON(!buf))
0858         return;
0859 
0860     if (buf == instr->ctx.data.buf.in)
0861         return;
0862 
0863     memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len);
0864     kfree(buf);
0865 }
0866 
0867 static void *
0868 meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr)
0869 {
0870     if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR))
0871         return NULL;
0872 
0873     if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out))
0874         return (void *)instr->ctx.data.buf.out;
0875 
0876     return kmemdup(instr->ctx.data.buf.out,
0877                instr->ctx.data.len, GFP_KERNEL);
0878 }
0879 
0880 static void
0881 meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
0882                       const void *buf)
0883 {
0884     if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) ||
0885         WARN_ON(!buf))
0886         return;
0887 
0888     if (buf != instr->ctx.data.buf.out)
0889         kfree(buf);
0890 }
0891 
0892 static int meson_nfc_exec_op(struct nand_chip *nand,
0893                  const struct nand_operation *op, bool check_only)
0894 {
0895     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
0896     struct meson_nfc *nfc = nand_get_controller_data(nand);
0897     const struct nand_op_instr *instr = NULL;
0898     void *buf;
0899     u32 op_id, delay_idle, cmd;
0900     int i;
0901 
0902     if (check_only)
0903         return 0;
0904 
0905     meson_nfc_select_chip(nand, op->cs);
0906     for (op_id = 0; op_id < op->ninstrs; op_id++) {
0907         instr = &op->instrs[op_id];
0908         delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns),
0909                       meson_chip->level1_divider *
0910                       NFC_CLK_CYCLE);
0911         switch (instr->type) {
0912         case NAND_OP_CMD_INSTR:
0913             cmd = nfc->param.chip_select | NFC_CMD_CLE;
0914             cmd |= instr->ctx.cmd.opcode & 0xff;
0915             writel(cmd, nfc->reg_base + NFC_REG_CMD);
0916             meson_nfc_cmd_idle(nfc, delay_idle);
0917             break;
0918 
0919         case NAND_OP_ADDR_INSTR:
0920             for (i = 0; i < instr->ctx.addr.naddrs; i++) {
0921                 cmd = nfc->param.chip_select | NFC_CMD_ALE;
0922                 cmd |= instr->ctx.addr.addrs[i] & 0xff;
0923                 writel(cmd, nfc->reg_base + NFC_REG_CMD);
0924             }
0925             meson_nfc_cmd_idle(nfc, delay_idle);
0926             break;
0927 
0928         case NAND_OP_DATA_IN_INSTR:
0929             buf = meson_nand_op_get_dma_safe_input_buf(instr);
0930             if (!buf)
0931                 return -ENOMEM;
0932             meson_nfc_read_buf(nand, buf, instr->ctx.data.len);
0933             meson_nand_op_put_dma_safe_input_buf(instr, buf);
0934             break;
0935 
0936         case NAND_OP_DATA_OUT_INSTR:
0937             buf = meson_nand_op_get_dma_safe_output_buf(instr);
0938             if (!buf)
0939                 return -ENOMEM;
0940             meson_nfc_write_buf(nand, buf, instr->ctx.data.len);
0941             meson_nand_op_put_dma_safe_output_buf(instr, buf);
0942             break;
0943 
0944         case NAND_OP_WAITRDY_INSTR:
0945             meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms);
0946             if (instr->delay_ns)
0947                 meson_nfc_cmd_idle(nfc, delay_idle);
0948             break;
0949         }
0950     }
0951     meson_nfc_wait_cmd_finish(nfc, 1000);
0952     return 0;
0953 }
0954 
0955 static int meson_ooblayout_ecc(struct mtd_info *mtd, int section,
0956                    struct mtd_oob_region *oobregion)
0957 {
0958     struct nand_chip *nand = mtd_to_nand(mtd);
0959 
0960     if (section >= nand->ecc.steps)
0961         return -ERANGE;
0962 
0963     oobregion->offset =  2 + (section * (2 + nand->ecc.bytes));
0964     oobregion->length = nand->ecc.bytes;
0965 
0966     return 0;
0967 }
0968 
0969 static int meson_ooblayout_free(struct mtd_info *mtd, int section,
0970                 struct mtd_oob_region *oobregion)
0971 {
0972     struct nand_chip *nand = mtd_to_nand(mtd);
0973 
0974     if (section >= nand->ecc.steps)
0975         return -ERANGE;
0976 
0977     oobregion->offset = section * (2 + nand->ecc.bytes);
0978     oobregion->length = 2;
0979 
0980     return 0;
0981 }
0982 
0983 static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
0984     .ecc = meson_ooblayout_ecc,
0985     .free = meson_ooblayout_free,
0986 };
0987 
0988 static int meson_nfc_clk_init(struct meson_nfc *nfc)
0989 {
0990     int ret;
0991 
0992     /* request core clock */
0993     nfc->core_clk = devm_clk_get(nfc->dev, "core");
0994     if (IS_ERR(nfc->core_clk)) {
0995         dev_err(nfc->dev, "failed to get core clock\n");
0996         return PTR_ERR(nfc->core_clk);
0997     }
0998 
0999     nfc->device_clk = devm_clk_get(nfc->dev, "device");
1000     if (IS_ERR(nfc->device_clk)) {
1001         dev_err(nfc->dev, "failed to get device clock\n");
1002         return PTR_ERR(nfc->device_clk);
1003     }
1004 
1005     nfc->phase_tx = devm_clk_get(nfc->dev, "tx");
1006     if (IS_ERR(nfc->phase_tx)) {
1007         dev_err(nfc->dev, "failed to get TX clk\n");
1008         return PTR_ERR(nfc->phase_tx);
1009     }
1010 
1011     nfc->phase_rx = devm_clk_get(nfc->dev, "rx");
1012     if (IS_ERR(nfc->phase_rx)) {
1013         dev_err(nfc->dev, "failed to get RX clk\n");
1014         return PTR_ERR(nfc->phase_rx);
1015     }
1016 
1017     /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
1018     regmap_update_bits(nfc->reg_clk,
1019                0, CLK_SELECT_NAND, CLK_SELECT_NAND);
1020 
1021     ret = clk_prepare_enable(nfc->core_clk);
1022     if (ret) {
1023         dev_err(nfc->dev, "failed to enable core clock\n");
1024         return ret;
1025     }
1026 
1027     ret = clk_prepare_enable(nfc->device_clk);
1028     if (ret) {
1029         dev_err(nfc->dev, "failed to enable device clock\n");
1030         goto err_device_clk;
1031     }
1032 
1033     ret = clk_prepare_enable(nfc->phase_tx);
1034     if (ret) {
1035         dev_err(nfc->dev, "failed to enable TX clock\n");
1036         goto err_phase_tx;
1037     }
1038 
1039     ret = clk_prepare_enable(nfc->phase_rx);
1040     if (ret) {
1041         dev_err(nfc->dev, "failed to enable RX clock\n");
1042         goto err_phase_rx;
1043     }
1044 
1045     ret = clk_set_rate(nfc->device_clk, 24000000);
1046     if (ret)
1047         goto err_disable_rx;
1048 
1049     return 0;
1050 
1051 err_disable_rx:
1052     clk_disable_unprepare(nfc->phase_rx);
1053 err_phase_rx:
1054     clk_disable_unprepare(nfc->phase_tx);
1055 err_phase_tx:
1056     clk_disable_unprepare(nfc->device_clk);
1057 err_device_clk:
1058     clk_disable_unprepare(nfc->core_clk);
1059     return ret;
1060 }
1061 
1062 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1063 {
1064     clk_disable_unprepare(nfc->phase_rx);
1065     clk_disable_unprepare(nfc->phase_tx);
1066     clk_disable_unprepare(nfc->device_clk);
1067     clk_disable_unprepare(nfc->core_clk);
1068 }
1069 
1070 static void meson_nfc_free_buffer(struct nand_chip *nand)
1071 {
1072     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1073 
1074     kfree(meson_chip->info_buf);
1075     kfree(meson_chip->data_buf);
1076 }
1077 
1078 static int meson_chip_buffer_init(struct nand_chip *nand)
1079 {
1080     struct mtd_info *mtd = nand_to_mtd(nand);
1081     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1082     u32 page_bytes, info_bytes, nsectors;
1083 
1084     nsectors = mtd->writesize / nand->ecc.size;
1085 
1086     page_bytes =  mtd->writesize + mtd->oobsize;
1087     info_bytes = nsectors * PER_INFO_BYTE;
1088 
1089     meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
1090     if (!meson_chip->data_buf)
1091         return -ENOMEM;
1092 
1093     meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
1094     if (!meson_chip->info_buf) {
1095         kfree(meson_chip->data_buf);
1096         return -ENOMEM;
1097     }
1098 
1099     return 0;
1100 }
1101 
1102 static
1103 int meson_nfc_setup_interface(struct nand_chip *nand, int csline,
1104                   const struct nand_interface_config *conf)
1105 {
1106     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1107     const struct nand_sdr_timings *timings;
1108     u32 div, bt_min, bt_max, tbers_clocks;
1109 
1110     timings = nand_get_sdr_timings(conf);
1111     if (IS_ERR(timings))
1112         return -ENOTSUPP;
1113 
1114     if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1115         return 0;
1116 
1117     div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE);
1118     bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div;
1119     bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min +
1120           timings->tRC_min / 2) / div;
1121 
1122     meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
1123                        div * NFC_CLK_CYCLE);
1124     meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
1125                     div * NFC_CLK_CYCLE);
1126     tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
1127                     div * NFC_CLK_CYCLE);
1128     meson_chip->tbers_max = ilog2(tbers_clocks);
1129     if (!is_power_of_2(tbers_clocks))
1130         meson_chip->tbers_max++;
1131 
1132     bt_min = DIV_ROUND_UP(bt_min, 1000);
1133     bt_max = DIV_ROUND_UP(bt_max, 1000);
1134 
1135     if (bt_max < bt_min)
1136         return -EINVAL;
1137 
1138     meson_chip->level1_divider = div;
1139     meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
1140     meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
1141 
1142     return 0;
1143 }
1144 
1145 static int meson_nand_bch_mode(struct nand_chip *nand)
1146 {
1147     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1148     int i;
1149 
1150     if (nand->ecc.strength > 60 || nand->ecc.strength < 8)
1151         return -EINVAL;
1152 
1153     for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) {
1154         if (meson_ecc[i].strength == nand->ecc.strength) {
1155             meson_chip->bch_mode = meson_ecc[i].bch;
1156             return 0;
1157         }
1158     }
1159 
1160     return -EINVAL;
1161 }
1162 
1163 static void meson_nand_detach_chip(struct nand_chip *nand)
1164 {
1165     meson_nfc_free_buffer(nand);
1166 }
1167 
1168 static int meson_nand_attach_chip(struct nand_chip *nand)
1169 {
1170     struct meson_nfc *nfc = nand_get_controller_data(nand);
1171     struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1172     struct mtd_info *mtd = nand_to_mtd(nand);
1173     int nsectors = mtd->writesize / 1024;
1174     int ret;
1175 
1176     if (!mtd->name) {
1177         mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1178                        "%s:nand%d",
1179                        dev_name(nfc->dev),
1180                        meson_chip->sels[0]);
1181         if (!mtd->name)
1182             return -ENOMEM;
1183     }
1184 
1185     if (nand->bbt_options & NAND_BBT_USE_FLASH)
1186         nand->bbt_options |= NAND_BBT_NO_OOB;
1187 
1188     nand->options |= NAND_NO_SUBPAGE_WRITE;
1189 
1190     ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1191                    mtd->oobsize - 2 * nsectors);
1192     if (ret) {
1193         dev_err(nfc->dev, "failed to ECC init\n");
1194         return -EINVAL;
1195     }
1196 
1197     mtd_set_ooblayout(mtd, &meson_ooblayout_ops);
1198 
1199     ret = meson_nand_bch_mode(nand);
1200     if (ret)
1201         return -EINVAL;
1202 
1203     nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1204     nand->ecc.write_page_raw = meson_nfc_write_page_raw;
1205     nand->ecc.write_page = meson_nfc_write_page_hwecc;
1206     nand->ecc.write_oob_raw = nand_write_oob_std;
1207     nand->ecc.write_oob = nand_write_oob_std;
1208 
1209     nand->ecc.read_page_raw = meson_nfc_read_page_raw;
1210     nand->ecc.read_page = meson_nfc_read_page_hwecc;
1211     nand->ecc.read_oob_raw = meson_nfc_read_oob_raw;
1212     nand->ecc.read_oob = meson_nfc_read_oob;
1213 
1214     if (nand->options & NAND_BUSWIDTH_16) {
1215         dev_err(nfc->dev, "16bits bus width not supported");
1216         return -EINVAL;
1217     }
1218     ret = meson_chip_buffer_init(nand);
1219     if (ret)
1220         return -ENOMEM;
1221 
1222     return ret;
1223 }
1224 
1225 static const struct nand_controller_ops meson_nand_controller_ops = {
1226     .attach_chip = meson_nand_attach_chip,
1227     .detach_chip = meson_nand_detach_chip,
1228     .setup_interface = meson_nfc_setup_interface,
1229     .exec_op = meson_nfc_exec_op,
1230 };
1231 
1232 static int
1233 meson_nfc_nand_chip_init(struct device *dev,
1234              struct meson_nfc *nfc, struct device_node *np)
1235 {
1236     struct meson_nfc_nand_chip *meson_chip;
1237     struct nand_chip *nand;
1238     struct mtd_info *mtd;
1239     int ret, i;
1240     u32 tmp, nsels;
1241 
1242     nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
1243     if (!nsels || nsels > MAX_CE_NUM) {
1244         dev_err(dev, "invalid register property size\n");
1245         return -EINVAL;
1246     }
1247 
1248     meson_chip = devm_kzalloc(dev, struct_size(meson_chip, sels, nsels),
1249                   GFP_KERNEL);
1250     if (!meson_chip)
1251         return -ENOMEM;
1252 
1253     meson_chip->nsels = nsels;
1254 
1255     for (i = 0; i < nsels; i++) {
1256         ret = of_property_read_u32_index(np, "reg", i, &tmp);
1257         if (ret) {
1258             dev_err(dev, "could not retrieve register property: %d\n",
1259                 ret);
1260             return ret;
1261         }
1262 
1263         if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1264             dev_err(dev, "CS %d already assigned\n", tmp);
1265             return -EINVAL;
1266         }
1267     }
1268 
1269     nand = &meson_chip->nand;
1270     nand->controller = &nfc->controller;
1271     nand->controller->ops = &meson_nand_controller_ops;
1272     nand_set_flash_node(nand, np);
1273     nand_set_controller_data(nand, nfc);
1274 
1275     nand->options |= NAND_USES_DMA;
1276     mtd = nand_to_mtd(nand);
1277     mtd->owner = THIS_MODULE;
1278     mtd->dev.parent = dev;
1279 
1280     ret = nand_scan(nand, nsels);
1281     if (ret)
1282         return ret;
1283 
1284     ret = mtd_device_register(mtd, NULL, 0);
1285     if (ret) {
1286         dev_err(dev, "failed to register MTD device: %d\n", ret);
1287         nand_cleanup(nand);
1288         return ret;
1289     }
1290 
1291     list_add_tail(&meson_chip->node, &nfc->chips);
1292 
1293     return 0;
1294 }
1295 
1296 static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1297 {
1298     struct meson_nfc_nand_chip *meson_chip;
1299     struct mtd_info *mtd;
1300 
1301     while (!list_empty(&nfc->chips)) {
1302         meson_chip = list_first_entry(&nfc->chips,
1303                           struct meson_nfc_nand_chip, node);
1304         mtd = nand_to_mtd(&meson_chip->nand);
1305         WARN_ON(mtd_device_unregister(mtd));
1306 
1307         nand_cleanup(&meson_chip->nand);
1308         list_del(&meson_chip->node);
1309     }
1310 }
1311 
1312 static int meson_nfc_nand_chips_init(struct device *dev,
1313                      struct meson_nfc *nfc)
1314 {
1315     struct device_node *np = dev->of_node;
1316     struct device_node *nand_np;
1317     int ret;
1318 
1319     for_each_child_of_node(np, nand_np) {
1320         ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1321         if (ret) {
1322             meson_nfc_nand_chip_cleanup(nfc);
1323             of_node_put(nand_np);
1324             return ret;
1325         }
1326     }
1327 
1328     return 0;
1329 }
1330 
1331 static irqreturn_t meson_nfc_irq(int irq, void *id)
1332 {
1333     struct meson_nfc *nfc = id;
1334     u32 cfg;
1335 
1336     cfg = readl(nfc->reg_base + NFC_REG_CFG);
1337     if (!(cfg & NFC_RB_IRQ_EN))
1338         return IRQ_NONE;
1339 
1340     cfg &= ~(NFC_RB_IRQ_EN);
1341     writel(cfg, nfc->reg_base + NFC_REG_CFG);
1342 
1343     complete(&nfc->completion);
1344     return IRQ_HANDLED;
1345 }
1346 
1347 static const struct meson_nfc_data meson_gxl_data = {
1348     .ecc_caps = &meson_gxl_ecc_caps,
1349 };
1350 
1351 static const struct meson_nfc_data meson_axg_data = {
1352     .ecc_caps = &meson_axg_ecc_caps,
1353 };
1354 
1355 static const struct of_device_id meson_nfc_id_table[] = {
1356     {
1357         .compatible = "amlogic,meson-gxl-nfc",
1358         .data = &meson_gxl_data,
1359     }, {
1360         .compatible = "amlogic,meson-axg-nfc",
1361         .data = &meson_axg_data,
1362     },
1363     {}
1364 };
1365 MODULE_DEVICE_TABLE(of, meson_nfc_id_table);
1366 
1367 static int meson_nfc_probe(struct platform_device *pdev)
1368 {
1369     struct device *dev = &pdev->dev;
1370     struct meson_nfc *nfc;
1371     struct resource *res;
1372     int ret, irq;
1373 
1374     nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1375     if (!nfc)
1376         return -ENOMEM;
1377 
1378     nfc->data = of_device_get_match_data(&pdev->dev);
1379     if (!nfc->data)
1380         return -ENODEV;
1381 
1382     nand_controller_init(&nfc->controller);
1383     INIT_LIST_HEAD(&nfc->chips);
1384     init_completion(&nfc->completion);
1385 
1386     nfc->dev = dev;
1387 
1388     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389     nfc->reg_base = devm_ioremap_resource(dev, res);
1390     if (IS_ERR(nfc->reg_base))
1391         return PTR_ERR(nfc->reg_base);
1392 
1393     nfc->reg_clk =
1394         syscon_regmap_lookup_by_phandle(dev->of_node,
1395                         "amlogic,mmc-syscon");
1396     if (IS_ERR(nfc->reg_clk)) {
1397         dev_err(dev, "Failed to lookup clock base\n");
1398         return PTR_ERR(nfc->reg_clk);
1399     }
1400 
1401     irq = platform_get_irq(pdev, 0);
1402     if (irq < 0)
1403         return -EINVAL;
1404 
1405     ret = meson_nfc_clk_init(nfc);
1406     if (ret) {
1407         dev_err(dev, "failed to initialize NAND clock\n");
1408         return ret;
1409     }
1410 
1411     writel(0, nfc->reg_base + NFC_REG_CFG);
1412     ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1413     if (ret) {
1414         dev_err(dev, "failed to request NFC IRQ\n");
1415         ret = -EINVAL;
1416         goto err_clk;
1417     }
1418 
1419     ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1420     if (ret) {
1421         dev_err(dev, "failed to set DMA mask\n");
1422         goto err_clk;
1423     }
1424 
1425     platform_set_drvdata(pdev, nfc);
1426 
1427     ret = meson_nfc_nand_chips_init(dev, nfc);
1428     if (ret) {
1429         dev_err(dev, "failed to init NAND chips\n");
1430         goto err_clk;
1431     }
1432 
1433     return 0;
1434 err_clk:
1435     meson_nfc_disable_clk(nfc);
1436     return ret;
1437 }
1438 
1439 static int meson_nfc_remove(struct platform_device *pdev)
1440 {
1441     struct meson_nfc *nfc = platform_get_drvdata(pdev);
1442 
1443     meson_nfc_nand_chip_cleanup(nfc);
1444 
1445     meson_nfc_disable_clk(nfc);
1446 
1447     return 0;
1448 }
1449 
1450 static struct platform_driver meson_nfc_driver = {
1451     .probe  = meson_nfc_probe,
1452     .remove = meson_nfc_remove,
1453     .driver = {
1454         .name  = "meson-nand",
1455         .of_match_table = meson_nfc_id_table,
1456     },
1457 };
1458 module_platform_driver(meson_nfc_driver);
1459 
1460 MODULE_LICENSE("Dual MIT/GPL");
1461 MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>");
1462 MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver");
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