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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * NXP LPC32XX NAND SLC driver
0004  *
0005  * Authors:
0006  *    Kevin Wells <kevin.wells@nxp.com>
0007  *    Roland Stigge <stigge@antcom.de>
0008  *
0009  * Copyright © 2011 NXP Semiconductors
0010  * Copyright © 2012 Roland Stigge
0011  */
0012 
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/mtd/mtd.h>
0017 #include <linux/mtd/rawnand.h>
0018 #include <linux/mtd/partitions.h>
0019 #include <linux/clk.h>
0020 #include <linux/err.h>
0021 #include <linux/delay.h>
0022 #include <linux/io.h>
0023 #include <linux/mm.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/dmaengine.h>
0026 #include <linux/gpio.h>
0027 #include <linux/of.h>
0028 #include <linux/of_gpio.h>
0029 #include <linux/mtd/lpc32xx_slc.h>
0030 
0031 #define LPC32XX_MODNAME     "lpc32xx-nand"
0032 
0033 /**********************************************************************
0034 * SLC NAND controller register offsets
0035 **********************************************************************/
0036 
0037 #define SLC_DATA(x)     (x + 0x000)
0038 #define SLC_ADDR(x)     (x + 0x004)
0039 #define SLC_CMD(x)      (x + 0x008)
0040 #define SLC_STOP(x)     (x + 0x00C)
0041 #define SLC_CTRL(x)     (x + 0x010)
0042 #define SLC_CFG(x)      (x + 0x014)
0043 #define SLC_STAT(x)     (x + 0x018)
0044 #define SLC_INT_STAT(x)     (x + 0x01C)
0045 #define SLC_IEN(x)      (x + 0x020)
0046 #define SLC_ISR(x)      (x + 0x024)
0047 #define SLC_ICR(x)      (x + 0x028)
0048 #define SLC_TAC(x)      (x + 0x02C)
0049 #define SLC_TC(x)       (x + 0x030)
0050 #define SLC_ECC(x)      (x + 0x034)
0051 #define SLC_DMA_DATA(x)     (x + 0x038)
0052 
0053 /**********************************************************************
0054 * slc_ctrl register definitions
0055 **********************************************************************/
0056 #define SLCCTRL_SW_RESET    (1 << 2) /* Reset the NAND controller bit */
0057 #define SLCCTRL_ECC_CLEAR   (1 << 1) /* Reset ECC bit */
0058 #define SLCCTRL_DMA_START   (1 << 0) /* Start DMA channel bit */
0059 
0060 /**********************************************************************
0061 * slc_cfg register definitions
0062 **********************************************************************/
0063 #define SLCCFG_CE_LOW       (1 << 5) /* Force CE low bit */
0064 #define SLCCFG_DMA_ECC      (1 << 4) /* Enable DMA ECC bit */
0065 #define SLCCFG_ECC_EN       (1 << 3) /* ECC enable bit */
0066 #define SLCCFG_DMA_BURST    (1 << 2) /* DMA burst bit */
0067 #define SLCCFG_DMA_DIR      (1 << 1) /* DMA write(0)/read(1) bit */
0068 #define SLCCFG_WIDTH        (1 << 0) /* External device width, 0=8bit */
0069 
0070 /**********************************************************************
0071 * slc_stat register definitions
0072 **********************************************************************/
0073 #define SLCSTAT_DMA_FIFO    (1 << 2) /* DMA FIFO has data bit */
0074 #define SLCSTAT_SLC_FIFO    (1 << 1) /* SLC FIFO has data bit */
0075 #define SLCSTAT_NAND_READY  (1 << 0) /* NAND device is ready bit */
0076 
0077 /**********************************************************************
0078 * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
0079 **********************************************************************/
0080 #define SLCSTAT_INT_TC      (1 << 1) /* Transfer count bit */
0081 #define SLCSTAT_INT_RDY_EN  (1 << 0) /* Ready interrupt bit */
0082 
0083 /**********************************************************************
0084 * slc_tac register definitions
0085 **********************************************************************/
0086 /* Computation of clock cycles on basis of controller and device clock rates */
0087 #define SLCTAC_CLOCKS(c, n, s)  (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
0088 
0089 /* Clock setting for RDY write sample wait time in 2*n clocks */
0090 #define SLCTAC_WDR(n)       (((n) & 0xF) << 28)
0091 /* Write pulse width in clock cycles, 1 to 16 clocks */
0092 #define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24))
0093 /* Write hold time of control and data signals, 1 to 16 clocks */
0094 #define SLCTAC_WHOLD(c, n)  (SLCTAC_CLOCKS(c, n, 20))
0095 /* Write setup time of control and data signals, 1 to 16 clocks */
0096 #define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16))
0097 /* Clock setting for RDY read sample wait time in 2*n clocks */
0098 #define SLCTAC_RDR(n)       (((n) & 0xF) << 12)
0099 /* Read pulse width in clock cycles, 1 to 16 clocks */
0100 #define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8))
0101 /* Read hold time of control and data signals, 1 to 16 clocks */
0102 #define SLCTAC_RHOLD(c, n)  (SLCTAC_CLOCKS(c, n, 4))
0103 /* Read setup time of control and data signals, 1 to 16 clocks */
0104 #define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0))
0105 
0106 /**********************************************************************
0107 * slc_ecc register definitions
0108 **********************************************************************/
0109 /* ECC line party fetch macro */
0110 #define SLCECC_TO_LINEPAR(n)    (((n) >> 6) & 0x7FFF)
0111 #define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
0112 
0113 /*
0114  * DMA requires storage space for the DMA local buffer and the hardware ECC
0115  * storage area. The DMA local buffer is only used if DMA mapping fails
0116  * during runtime.
0117  */
0118 #define LPC32XX_DMA_DATA_SIZE       4096
0119 #define LPC32XX_ECC_SAVE_SIZE       ((4096 / 256) * 4)
0120 
0121 /* Number of bytes used for ECC stored in NAND per 256 bytes */
0122 #define LPC32XX_SLC_DEV_ECC_BYTES   3
0123 
0124 /*
0125  * If the NAND base clock frequency can't be fetched, this frequency will be
0126  * used instead as the base. This rate is used to setup the timing registers
0127  * used for NAND accesses.
0128  */
0129 #define LPC32XX_DEF_BUS_RATE        133250000
0130 
0131 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */
0132 #define LPC32XX_DMA_TIMEOUT     100
0133 
0134 /*
0135  * NAND ECC Layout for small page NAND devices
0136  * Note: For large and huge page devices, the default layouts are used
0137  */
0138 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
0139                  struct mtd_oob_region *oobregion)
0140 {
0141     if (section)
0142         return -ERANGE;
0143 
0144     oobregion->length = 6;
0145     oobregion->offset = 10;
0146 
0147     return 0;
0148 }
0149 
0150 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
0151                   struct mtd_oob_region *oobregion)
0152 {
0153     if (section > 1)
0154         return -ERANGE;
0155 
0156     if (!section) {
0157         oobregion->offset = 0;
0158         oobregion->length = 4;
0159     } else {
0160         oobregion->offset = 6;
0161         oobregion->length = 4;
0162     }
0163 
0164     return 0;
0165 }
0166 
0167 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
0168     .ecc = lpc32xx_ooblayout_ecc,
0169     .free = lpc32xx_ooblayout_free,
0170 };
0171 
0172 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
0173 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
0174 
0175 /*
0176  * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
0177  * Note: Large page devices used the default layout
0178  */
0179 static struct nand_bbt_descr bbt_smallpage_main_descr = {
0180     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0181         | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
0182     .offs = 0,
0183     .len = 4,
0184     .veroffs = 6,
0185     .maxblocks = 4,
0186     .pattern = bbt_pattern
0187 };
0188 
0189 static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
0190     .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
0191         | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
0192     .offs = 0,
0193     .len = 4,
0194     .veroffs = 6,
0195     .maxblocks = 4,
0196     .pattern = mirror_pattern
0197 };
0198 
0199 /*
0200  * NAND platform configuration structure
0201  */
0202 struct lpc32xx_nand_cfg_slc {
0203     uint32_t wdr_clks;
0204     uint32_t wwidth;
0205     uint32_t whold;
0206     uint32_t wsetup;
0207     uint32_t rdr_clks;
0208     uint32_t rwidth;
0209     uint32_t rhold;
0210     uint32_t rsetup;
0211     int wp_gpio;
0212     struct mtd_partition *parts;
0213     unsigned num_parts;
0214 };
0215 
0216 struct lpc32xx_nand_host {
0217     struct nand_chip    nand_chip;
0218     struct lpc32xx_slc_platform_data *pdata;
0219     struct clk      *clk;
0220     void __iomem        *io_base;
0221     struct lpc32xx_nand_cfg_slc *ncfg;
0222 
0223     struct completion   comp;
0224     struct dma_chan     *dma_chan;
0225     uint32_t        dma_buf_len;
0226     struct dma_slave_config dma_slave_config;
0227     struct scatterlist  sgl;
0228 
0229     /*
0230      * DMA and CPU addresses of ECC work area and data buffer
0231      */
0232     uint32_t        *ecc_buf;
0233     uint8_t         *data_buf;
0234     dma_addr_t      io_base_dma;
0235 };
0236 
0237 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
0238 {
0239     uint32_t clkrate, tmp;
0240 
0241     /* Reset SLC controller */
0242     writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
0243     udelay(1000);
0244 
0245     /* Basic setup */
0246     writel(0, SLC_CFG(host->io_base));
0247     writel(0, SLC_IEN(host->io_base));
0248     writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
0249         SLC_ICR(host->io_base));
0250 
0251     /* Get base clock for SLC block */
0252     clkrate = clk_get_rate(host->clk);
0253     if (clkrate == 0)
0254         clkrate = LPC32XX_DEF_BUS_RATE;
0255 
0256     /* Compute clock setup values */
0257     tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
0258         SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
0259         SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
0260         SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
0261         SLCTAC_RDR(host->ncfg->rdr_clks) |
0262         SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
0263         SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
0264         SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
0265     writel(tmp, SLC_TAC(host->io_base));
0266 }
0267 
0268 /*
0269  * Hardware specific access to control lines
0270  */
0271 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
0272                   unsigned int ctrl)
0273 {
0274     uint32_t tmp;
0275     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0276 
0277     /* Does CE state need to be changed? */
0278     tmp = readl(SLC_CFG(host->io_base));
0279     if (ctrl & NAND_NCE)
0280         tmp |= SLCCFG_CE_LOW;
0281     else
0282         tmp &= ~SLCCFG_CE_LOW;
0283     writel(tmp, SLC_CFG(host->io_base));
0284 
0285     if (cmd != NAND_CMD_NONE) {
0286         if (ctrl & NAND_CLE)
0287             writel(cmd, SLC_CMD(host->io_base));
0288         else
0289             writel(cmd, SLC_ADDR(host->io_base));
0290     }
0291 }
0292 
0293 /*
0294  * Read the Device Ready pin
0295  */
0296 static int lpc32xx_nand_device_ready(struct nand_chip *chip)
0297 {
0298     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0299     int rdy = 0;
0300 
0301     if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
0302         rdy = 1;
0303 
0304     return rdy;
0305 }
0306 
0307 /*
0308  * Enable NAND write protect
0309  */
0310 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
0311 {
0312     if (gpio_is_valid(host->ncfg->wp_gpio))
0313         gpio_set_value(host->ncfg->wp_gpio, 0);
0314 }
0315 
0316 /*
0317  * Disable NAND write protect
0318  */
0319 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
0320 {
0321     if (gpio_is_valid(host->ncfg->wp_gpio))
0322         gpio_set_value(host->ncfg->wp_gpio, 1);
0323 }
0324 
0325 /*
0326  * Prepares SLC for transfers with H/W ECC enabled
0327  */
0328 static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode)
0329 {
0330     /* Hardware ECC is enabled automatically in hardware as needed */
0331 }
0332 
0333 /*
0334  * Calculates the ECC for the data
0335  */
0336 static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip,
0337                       const unsigned char *buf,
0338                       unsigned char *code)
0339 {
0340     /*
0341      * ECC is calculated automatically in hardware during syndrome read
0342      * and write operations, so it doesn't need to be calculated here.
0343      */
0344     return 0;
0345 }
0346 
0347 /*
0348  * Read a single byte from NAND device
0349  */
0350 static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip)
0351 {
0352     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0353 
0354     return (uint8_t)readl(SLC_DATA(host->io_base));
0355 }
0356 
0357 /*
0358  * Simple device read without ECC
0359  */
0360 static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
0361 {
0362     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0363 
0364     /* Direct device read with no ECC */
0365     while (len-- > 0)
0366         *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
0367 }
0368 
0369 /*
0370  * Simple device write without ECC
0371  */
0372 static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf,
0373                    int len)
0374 {
0375     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0376 
0377     /* Direct device write with no ECC */
0378     while (len-- > 0)
0379         writel((uint32_t)*buf++, SLC_DATA(host->io_base));
0380 }
0381 
0382 /*
0383  * Read the OOB data from the device without ECC using FIFO method
0384  */
0385 static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page)
0386 {
0387     struct mtd_info *mtd = nand_to_mtd(chip);
0388 
0389     return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
0390 }
0391 
0392 /*
0393  * Write the OOB data to the device without ECC using FIFO method
0394  */
0395 static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page)
0396 {
0397     struct mtd_info *mtd = nand_to_mtd(chip);
0398 
0399     return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
0400                  mtd->oobsize);
0401 }
0402 
0403 /*
0404  * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
0405  */
0406 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
0407 {
0408     int i;
0409 
0410     for (i = 0; i < (count * 3); i += 3) {
0411         uint32_t ce = ecc[i / 3];
0412         ce = ~(ce << 2) & 0xFFFFFF;
0413         spare[i + 2] = (uint8_t)(ce & 0xFF);
0414         ce >>= 8;
0415         spare[i + 1] = (uint8_t)(ce & 0xFF);
0416         ce >>= 8;
0417         spare[i] = (uint8_t)(ce & 0xFF);
0418     }
0419 }
0420 
0421 static void lpc32xx_dma_complete_func(void *completion)
0422 {
0423     complete(completion);
0424 }
0425 
0426 static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
0427                 void *mem, int len, enum dma_transfer_direction dir)
0428 {
0429     struct nand_chip *chip = mtd_to_nand(mtd);
0430     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0431     struct dma_async_tx_descriptor *desc;
0432     int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
0433     int res;
0434 
0435     host->dma_slave_config.direction = dir;
0436     host->dma_slave_config.src_addr = dma;
0437     host->dma_slave_config.dst_addr = dma;
0438     host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0439     host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0440     host->dma_slave_config.src_maxburst = 4;
0441     host->dma_slave_config.dst_maxburst = 4;
0442     /* DMA controller does flow control: */
0443     host->dma_slave_config.device_fc = false;
0444     if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
0445         dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
0446         return -ENXIO;
0447     }
0448 
0449     sg_init_one(&host->sgl, mem, len);
0450 
0451     res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
0452              DMA_BIDIRECTIONAL);
0453     if (res != 1) {
0454         dev_err(mtd->dev.parent, "Failed to map sg list\n");
0455         return -ENXIO;
0456     }
0457     desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
0458                        flags);
0459     if (!desc) {
0460         dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
0461         goto out1;
0462     }
0463 
0464     init_completion(&host->comp);
0465     desc->callback = lpc32xx_dma_complete_func;
0466     desc->callback_param = &host->comp;
0467 
0468     dmaengine_submit(desc);
0469     dma_async_issue_pending(host->dma_chan);
0470 
0471     wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
0472 
0473     dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
0474              DMA_BIDIRECTIONAL);
0475 
0476     return 0;
0477 out1:
0478     dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
0479              DMA_BIDIRECTIONAL);
0480     return -ENXIO;
0481 }
0482 
0483 /*
0484  * DMA read/write transfers with ECC support
0485  */
0486 static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
0487             int read)
0488 {
0489     struct nand_chip *chip = mtd_to_nand(mtd);
0490     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0491     int i, status = 0;
0492     unsigned long timeout;
0493     int res;
0494     enum dma_transfer_direction dir =
0495         read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
0496     uint8_t *dma_buf;
0497     bool dma_mapped;
0498 
0499     if ((void *)buf <= high_memory) {
0500         dma_buf = buf;
0501         dma_mapped = true;
0502     } else {
0503         dma_buf = host->data_buf;
0504         dma_mapped = false;
0505         if (!read)
0506             memcpy(host->data_buf, buf, mtd->writesize);
0507     }
0508 
0509     if (read) {
0510         writel(readl(SLC_CFG(host->io_base)) |
0511                SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
0512                SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
0513     } else {
0514         writel((readl(SLC_CFG(host->io_base)) |
0515             SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
0516                ~SLCCFG_DMA_DIR,
0517             SLC_CFG(host->io_base));
0518     }
0519 
0520     /* Clear initial ECC */
0521     writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
0522 
0523     /* Transfer size is data area only */
0524     writel(mtd->writesize, SLC_TC(host->io_base));
0525 
0526     /* Start transfer in the NAND controller */
0527     writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
0528            SLC_CTRL(host->io_base));
0529 
0530     for (i = 0; i < chip->ecc.steps; i++) {
0531         /* Data */
0532         res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
0533                        dma_buf + i * chip->ecc.size,
0534                        mtd->writesize / chip->ecc.steps, dir);
0535         if (res)
0536             return res;
0537 
0538         /* Always _read_ ECC */
0539         if (i == chip->ecc.steps - 1)
0540             break;
0541         if (!read) /* ECC availability delayed on write */
0542             udelay(10);
0543         res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
0544                        &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
0545         if (res)
0546             return res;
0547     }
0548 
0549     /*
0550      * According to NXP, the DMA can be finished here, but the NAND
0551      * controller may still have buffered data. After porting to using the
0552      * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
0553      * appears to be always true, according to tests. Keeping the check for
0554      * safety reasons for now.
0555      */
0556     if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
0557         dev_warn(mtd->dev.parent, "FIFO not empty!\n");
0558         timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
0559         while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
0560                time_before(jiffies, timeout))
0561             cpu_relax();
0562         if (!time_before(jiffies, timeout)) {
0563             dev_err(mtd->dev.parent, "FIFO held data too long\n");
0564             status = -EIO;
0565         }
0566     }
0567 
0568     /* Read last calculated ECC value */
0569     if (!read)
0570         udelay(10);
0571     host->ecc_buf[chip->ecc.steps - 1] =
0572         readl(SLC_ECC(host->io_base));
0573 
0574     /* Flush DMA */
0575     dmaengine_terminate_all(host->dma_chan);
0576 
0577     if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
0578         readl(SLC_TC(host->io_base))) {
0579         /* Something is left in the FIFO, something is wrong */
0580         dev_err(mtd->dev.parent, "DMA FIFO failure\n");
0581         status = -EIO;
0582     }
0583 
0584     /* Stop DMA & HW ECC */
0585     writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
0586            SLC_CTRL(host->io_base));
0587     writel(readl(SLC_CFG(host->io_base)) &
0588            ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
0589          SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
0590 
0591     if (!dma_mapped && read)
0592         memcpy(buf, host->data_buf, mtd->writesize);
0593 
0594     return status;
0595 }
0596 
0597 /*
0598  * Read the data and OOB data from the device, use ECC correction with the
0599  * data, disable ECC for the OOB data
0600  */
0601 static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
0602                        int oob_required, int page)
0603 {
0604     struct mtd_info *mtd = nand_to_mtd(chip);
0605     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0606     struct mtd_oob_region oobregion = { };
0607     int stat, i, status, error;
0608     uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
0609 
0610     /* Issue read command */
0611     nand_read_page_op(chip, page, 0, NULL, 0);
0612 
0613     /* Read data and oob, calculate ECC */
0614     status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
0615 
0616     /* Get OOB data */
0617     chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
0618 
0619     /* Convert to stored ECC format */
0620     lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
0621 
0622     /* Pointer to ECC data retrieved from NAND spare area */
0623     error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
0624     if (error)
0625         return error;
0626 
0627     oobecc = chip->oob_poi + oobregion.offset;
0628 
0629     for (i = 0; i < chip->ecc.steps; i++) {
0630         stat = chip->ecc.correct(chip, buf, oobecc,
0631                      &tmpecc[i * chip->ecc.bytes]);
0632         if (stat < 0)
0633             mtd->ecc_stats.failed++;
0634         else
0635             mtd->ecc_stats.corrected += stat;
0636 
0637         buf += chip->ecc.size;
0638         oobecc += chip->ecc.bytes;
0639     }
0640 
0641     return status;
0642 }
0643 
0644 /*
0645  * Read the data and OOB data from the device, no ECC correction with the
0646  * data or OOB data
0647  */
0648 static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip,
0649                            uint8_t *buf, int oob_required,
0650                            int page)
0651 {
0652     struct mtd_info *mtd = nand_to_mtd(chip);
0653 
0654     /* Issue read command */
0655     nand_read_page_op(chip, page, 0, NULL, 0);
0656 
0657     /* Raw reads can just use the FIFO interface */
0658     chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);
0659     chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
0660 
0661     return 0;
0662 }
0663 
0664 /*
0665  * Write the data and OOB data to the device, use ECC with the data,
0666  * disable ECC for the OOB data
0667  */
0668 static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip,
0669                         const uint8_t *buf,
0670                         int oob_required, int page)
0671 {
0672     struct mtd_info *mtd = nand_to_mtd(chip);
0673     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0674     struct mtd_oob_region oobregion = { };
0675     uint8_t *pb;
0676     int error;
0677 
0678     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0679 
0680     /* Write data, calculate ECC on outbound data */
0681     error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
0682     if (error)
0683         return error;
0684 
0685     /*
0686      * The calculated ECC needs some manual work done to it before
0687      * committing it to NAND. Process the calculated ECC and place
0688      * the resultant values directly into the OOB buffer. */
0689     error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
0690     if (error)
0691         return error;
0692 
0693     pb = chip->oob_poi + oobregion.offset;
0694     lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
0695 
0696     /* Write ECC data to device */
0697     chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
0698 
0699     return nand_prog_page_end_op(chip);
0700 }
0701 
0702 /*
0703  * Write the data and OOB data to the device, no ECC correction with the
0704  * data or OOB data
0705  */
0706 static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip,
0707                         const uint8_t *buf,
0708                         int oob_required, int page)
0709 {
0710     struct mtd_info *mtd = nand_to_mtd(chip);
0711 
0712     /* Raw writes can just use the FIFO interface */
0713     nand_prog_page_begin_op(chip, page, 0, buf,
0714                 chip->ecc.size * chip->ecc.steps);
0715     chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
0716 
0717     return nand_prog_page_end_op(chip);
0718 }
0719 
0720 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
0721 {
0722     struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
0723     dma_cap_mask_t mask;
0724 
0725     if (!host->pdata || !host->pdata->dma_filter) {
0726         dev_err(mtd->dev.parent, "no DMA platform data\n");
0727         return -ENOENT;
0728     }
0729 
0730     dma_cap_zero(mask);
0731     dma_cap_set(DMA_SLAVE, mask);
0732     host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
0733                          "nand-slc");
0734     if (!host->dma_chan) {
0735         dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
0736         return -EBUSY;
0737     }
0738 
0739     return 0;
0740 }
0741 
0742 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
0743 {
0744     struct lpc32xx_nand_cfg_slc *ncfg;
0745     struct device_node *np = dev->of_node;
0746 
0747     ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
0748     if (!ncfg)
0749         return NULL;
0750 
0751     of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
0752     of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
0753     of_property_read_u32(np, "nxp,whold", &ncfg->whold);
0754     of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
0755     of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
0756     of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
0757     of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
0758     of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
0759 
0760     if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
0761         !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
0762         !ncfg->rhold || !ncfg->rsetup) {
0763         dev_err(dev, "chip parameters not specified correctly\n");
0764         return NULL;
0765     }
0766 
0767     ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
0768 
0769     return ncfg;
0770 }
0771 
0772 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
0773 {
0774     struct mtd_info *mtd = nand_to_mtd(chip);
0775     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0776 
0777     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0778         return 0;
0779 
0780     /* OOB and ECC CPU and DMA work areas */
0781     host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
0782 
0783     /*
0784      * Small page FLASH has a unique OOB layout, but large and huge
0785      * page FLASH use the standard layout. Small page FLASH uses a
0786      * custom BBT marker layout.
0787      */
0788     if (mtd->writesize <= 512)
0789         mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
0790 
0791     chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
0792     /* These sizes remain the same regardless of page size */
0793     chip->ecc.size = 256;
0794     chip->ecc.strength = 1;
0795     chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
0796     chip->ecc.prepad = 0;
0797     chip->ecc.postpad = 0;
0798     chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
0799     chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
0800     chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
0801     chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
0802     chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
0803     chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
0804     chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
0805     chip->ecc.correct = rawnand_sw_hamming_correct;
0806     chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
0807 
0808     /*
0809      * Use a custom BBT marker setup for small page FLASH that
0810      * won't interfere with the ECC layout. Large and huge page
0811      * FLASH use the standard layout.
0812      */
0813     if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
0814         mtd->writesize <= 512) {
0815         chip->bbt_td = &bbt_smallpage_main_descr;
0816         chip->bbt_md = &bbt_smallpage_mirror_descr;
0817     }
0818 
0819     return 0;
0820 }
0821 
0822 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
0823     .attach_chip = lpc32xx_nand_attach_chip,
0824 };
0825 
0826 /*
0827  * Probe for NAND controller
0828  */
0829 static int lpc32xx_nand_probe(struct platform_device *pdev)
0830 {
0831     struct lpc32xx_nand_host *host;
0832     struct mtd_info *mtd;
0833     struct nand_chip *chip;
0834     struct resource *rc;
0835     int res;
0836 
0837     /* Allocate memory for the device structure (and zero it) */
0838     host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
0839     if (!host)
0840         return -ENOMEM;
0841 
0842     rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0843     host->io_base = devm_ioremap_resource(&pdev->dev, rc);
0844     if (IS_ERR(host->io_base))
0845         return PTR_ERR(host->io_base);
0846 
0847     host->io_base_dma = rc->start;
0848     if (pdev->dev.of_node)
0849         host->ncfg = lpc32xx_parse_dt(&pdev->dev);
0850     if (!host->ncfg) {
0851         dev_err(&pdev->dev,
0852             "Missing or bad NAND config from device tree\n");
0853         return -ENOENT;
0854     }
0855     if (host->ncfg->wp_gpio == -EPROBE_DEFER)
0856         return -EPROBE_DEFER;
0857     if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
0858             host->ncfg->wp_gpio, "NAND WP")) {
0859         dev_err(&pdev->dev, "GPIO not available\n");
0860         return -EBUSY;
0861     }
0862     lpc32xx_wp_disable(host);
0863 
0864     host->pdata = dev_get_platdata(&pdev->dev);
0865 
0866     chip = &host->nand_chip;
0867     mtd = nand_to_mtd(chip);
0868     nand_set_controller_data(chip, host);
0869     nand_set_flash_node(chip, pdev->dev.of_node);
0870     mtd->owner = THIS_MODULE;
0871     mtd->dev.parent = &pdev->dev;
0872 
0873     /* Get NAND clock */
0874     host->clk = devm_clk_get(&pdev->dev, NULL);
0875     if (IS_ERR(host->clk)) {
0876         dev_err(&pdev->dev, "Clock failure\n");
0877         res = -ENOENT;
0878         goto enable_wp;
0879     }
0880     res = clk_prepare_enable(host->clk);
0881     if (res)
0882         goto enable_wp;
0883 
0884     /* Set NAND IO addresses and command/ready functions */
0885     chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
0886     chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
0887     chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
0888     chip->legacy.dev_ready = lpc32xx_nand_device_ready;
0889     chip->legacy.chip_delay = 20; /* 20us command delay time */
0890 
0891     /* Init NAND controller */
0892     lpc32xx_nand_setup(host);
0893 
0894     platform_set_drvdata(pdev, host);
0895 
0896     /* NAND callbacks for LPC32xx SLC hardware */
0897     chip->legacy.read_byte = lpc32xx_nand_read_byte;
0898     chip->legacy.read_buf = lpc32xx_nand_read_buf;
0899     chip->legacy.write_buf = lpc32xx_nand_write_buf;
0900 
0901     /*
0902      * Allocate a large enough buffer for a single huge page plus
0903      * extra space for the spare area and ECC storage area
0904      */
0905     host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
0906     host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
0907                       GFP_KERNEL);
0908     if (host->data_buf == NULL) {
0909         res = -ENOMEM;
0910         goto unprepare_clk;
0911     }
0912 
0913     res = lpc32xx_nand_dma_setup(host);
0914     if (res) {
0915         res = -EIO;
0916         goto unprepare_clk;
0917     }
0918 
0919     /* Find NAND device */
0920     chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
0921     res = nand_scan(chip, 1);
0922     if (res)
0923         goto release_dma;
0924 
0925     mtd->name = "nxp_lpc3220_slc";
0926     res = mtd_device_register(mtd, host->ncfg->parts,
0927                   host->ncfg->num_parts);
0928     if (res)
0929         goto cleanup_nand;
0930 
0931     return 0;
0932 
0933 cleanup_nand:
0934     nand_cleanup(chip);
0935 release_dma:
0936     dma_release_channel(host->dma_chan);
0937 unprepare_clk:
0938     clk_disable_unprepare(host->clk);
0939 enable_wp:
0940     lpc32xx_wp_enable(host);
0941 
0942     return res;
0943 }
0944 
0945 /*
0946  * Remove NAND device.
0947  */
0948 static int lpc32xx_nand_remove(struct platform_device *pdev)
0949 {
0950     uint32_t tmp;
0951     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0952     struct nand_chip *chip = &host->nand_chip;
0953     int ret;
0954 
0955     ret = mtd_device_unregister(nand_to_mtd(chip));
0956     WARN_ON(ret);
0957     nand_cleanup(chip);
0958     dma_release_channel(host->dma_chan);
0959 
0960     /* Force CE high */
0961     tmp = readl(SLC_CTRL(host->io_base));
0962     tmp &= ~SLCCFG_CE_LOW;
0963     writel(tmp, SLC_CTRL(host->io_base));
0964 
0965     clk_disable_unprepare(host->clk);
0966     lpc32xx_wp_enable(host);
0967 
0968     return 0;
0969 }
0970 
0971 #ifdef CONFIG_PM
0972 static int lpc32xx_nand_resume(struct platform_device *pdev)
0973 {
0974     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0975     int ret;
0976 
0977     /* Re-enable NAND clock */
0978     ret = clk_prepare_enable(host->clk);
0979     if (ret)
0980         return ret;
0981 
0982     /* Fresh init of NAND controller */
0983     lpc32xx_nand_setup(host);
0984 
0985     /* Disable write protect */
0986     lpc32xx_wp_disable(host);
0987 
0988     return 0;
0989 }
0990 
0991 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
0992 {
0993     uint32_t tmp;
0994     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0995 
0996     /* Force CE high */
0997     tmp = readl(SLC_CTRL(host->io_base));
0998     tmp &= ~SLCCFG_CE_LOW;
0999     writel(tmp, SLC_CTRL(host->io_base));
1000 
1001     /* Enable write protect for safety */
1002     lpc32xx_wp_enable(host);
1003 
1004     /* Disable clock */
1005     clk_disable_unprepare(host->clk);
1006 
1007     return 0;
1008 }
1009 
1010 #else
1011 #define lpc32xx_nand_resume NULL
1012 #define lpc32xx_nand_suspend NULL
1013 #endif
1014 
1015 static const struct of_device_id lpc32xx_nand_match[] = {
1016     { .compatible = "nxp,lpc3220-slc" },
1017     { /* sentinel */ },
1018 };
1019 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1020 
1021 static struct platform_driver lpc32xx_nand_driver = {
1022     .probe      = lpc32xx_nand_probe,
1023     .remove     = lpc32xx_nand_remove,
1024     .resume     = lpc32xx_nand_resume,
1025     .suspend    = lpc32xx_nand_suspend,
1026     .driver     = {
1027         .name   = LPC32XX_MODNAME,
1028         .of_match_table = lpc32xx_nand_match,
1029     },
1030 };
1031 
1032 module_platform_driver(lpc32xx_nand_driver);
1033 
1034 MODULE_LICENSE("GPL");
1035 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1036 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1037 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
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