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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for NAND MLC Controller in LPC32xx
0004  *
0005  * Author: Roland Stigge <stigge@antcom.de>
0006  *
0007  * Copyright © 2011 WORK Microwave GmbH
0008  * Copyright © 2011, 2012 Roland Stigge
0009  *
0010  * NAND Flash Controller Operation:
0011  * - Read: Auto Decode
0012  * - Write: Auto Encode
0013  * - Tested Page Sizes: 2048, 4096
0014  */
0015 
0016 #include <linux/slab.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/mtd/mtd.h>
0020 #include <linux/mtd/rawnand.h>
0021 #include <linux/mtd/partitions.h>
0022 #include <linux/clk.h>
0023 #include <linux/err.h>
0024 #include <linux/delay.h>
0025 #include <linux/completion.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/of.h>
0028 #include <linux/of_gpio.h>
0029 #include <linux/mtd/lpc32xx_mlc.h>
0030 #include <linux/io.h>
0031 #include <linux/mm.h>
0032 #include <linux/dma-mapping.h>
0033 #include <linux/dmaengine.h>
0034 
0035 #define DRV_NAME "lpc32xx_mlc"
0036 
0037 /**********************************************************************
0038 * MLC NAND controller register offsets
0039 **********************************************************************/
0040 
0041 #define MLC_BUFF(x)         (x + 0x00000)
0042 #define MLC_DATA(x)         (x + 0x08000)
0043 #define MLC_CMD(x)          (x + 0x10000)
0044 #define MLC_ADDR(x)         (x + 0x10004)
0045 #define MLC_ECC_ENC_REG(x)      (x + 0x10008)
0046 #define MLC_ECC_DEC_REG(x)      (x + 0x1000C)
0047 #define MLC_ECC_AUTO_ENC_REG(x)     (x + 0x10010)
0048 #define MLC_ECC_AUTO_DEC_REG(x)     (x + 0x10014)
0049 #define MLC_RPR(x)          (x + 0x10018)
0050 #define MLC_WPR(x)          (x + 0x1001C)
0051 #define MLC_RUBP(x)         (x + 0x10020)
0052 #define MLC_ROBP(x)         (x + 0x10024)
0053 #define MLC_SW_WP_ADD_LOW(x)        (x + 0x10028)
0054 #define MLC_SW_WP_ADD_HIG(x)        (x + 0x1002C)
0055 #define MLC_ICR(x)          (x + 0x10030)
0056 #define MLC_TIME_REG(x)         (x + 0x10034)
0057 #define MLC_IRQ_MR(x)           (x + 0x10038)
0058 #define MLC_IRQ_SR(x)           (x + 0x1003C)
0059 #define MLC_LOCK_PR(x)          (x + 0x10044)
0060 #define MLC_ISR(x)          (x + 0x10048)
0061 #define MLC_CEH(x)          (x + 0x1004C)
0062 
0063 /**********************************************************************
0064 * MLC_CMD bit definitions
0065 **********************************************************************/
0066 #define MLCCMD_RESET            0xFF
0067 
0068 /**********************************************************************
0069 * MLC_ICR bit definitions
0070 **********************************************************************/
0071 #define MLCICR_WPROT            (1 << 3)
0072 #define MLCICR_LARGEBLOCK       (1 << 2)
0073 #define MLCICR_LONGADDR         (1 << 1)
0074 #define MLCICR_16BIT            (1 << 0)  /* unsupported by LPC32x0! */
0075 
0076 /**********************************************************************
0077 * MLC_TIME_REG bit definitions
0078 **********************************************************************/
0079 #define MLCTIMEREG_TCEA_DELAY(n)    (((n) & 0x03) << 24)
0080 #define MLCTIMEREG_BUSY_DELAY(n)    (((n) & 0x1F) << 19)
0081 #define MLCTIMEREG_NAND_TA(n)       (((n) & 0x07) << 16)
0082 #define MLCTIMEREG_RD_HIGH(n)       (((n) & 0x0F) << 12)
0083 #define MLCTIMEREG_RD_LOW(n)        (((n) & 0x0F) << 8)
0084 #define MLCTIMEREG_WR_HIGH(n)       (((n) & 0x0F) << 4)
0085 #define MLCTIMEREG_WR_LOW(n)        (((n) & 0x0F) << 0)
0086 
0087 /**********************************************************************
0088 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
0089 **********************************************************************/
0090 #define MLCIRQ_NAND_READY       (1 << 5)
0091 #define MLCIRQ_CONTROLLER_READY     (1 << 4)
0092 #define MLCIRQ_DECODE_FAILURE       (1 << 3)
0093 #define MLCIRQ_DECODE_ERROR     (1 << 2)
0094 #define MLCIRQ_ECC_READY        (1 << 1)
0095 #define MLCIRQ_WRPROT_FAULT     (1 << 0)
0096 
0097 /**********************************************************************
0098 * MLC_LOCK_PR bit definitions
0099 **********************************************************************/
0100 #define MLCLOCKPR_MAGIC         0xA25E
0101 
0102 /**********************************************************************
0103 * MLC_ISR bit definitions
0104 **********************************************************************/
0105 #define MLCISR_DECODER_FAILURE      (1 << 6)
0106 #define MLCISR_ERRORS           ((1 << 4) | (1 << 5))
0107 #define MLCISR_ERRORS_DETECTED      (1 << 3)
0108 #define MLCISR_ECC_READY        (1 << 2)
0109 #define MLCISR_CONTROLLER_READY     (1 << 1)
0110 #define MLCISR_NAND_READY       (1 << 0)
0111 
0112 /**********************************************************************
0113 * MLC_CEH bit definitions
0114 **********************************************************************/
0115 #define MLCCEH_NORMAL           (1 << 0)
0116 
0117 struct lpc32xx_nand_cfg_mlc {
0118     uint32_t tcea_delay;
0119     uint32_t busy_delay;
0120     uint32_t nand_ta;
0121     uint32_t rd_high;
0122     uint32_t rd_low;
0123     uint32_t wr_high;
0124     uint32_t wr_low;
0125     int wp_gpio;
0126     struct mtd_partition *parts;
0127     unsigned num_parts;
0128 };
0129 
0130 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
0131                  struct mtd_oob_region *oobregion)
0132 {
0133     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0134 
0135     if (section >= nand_chip->ecc.steps)
0136         return -ERANGE;
0137 
0138     oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
0139     oobregion->length = nand_chip->ecc.bytes;
0140 
0141     return 0;
0142 }
0143 
0144 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
0145                   struct mtd_oob_region *oobregion)
0146 {
0147     struct nand_chip *nand_chip = mtd_to_nand(mtd);
0148 
0149     if (section >= nand_chip->ecc.steps)
0150         return -ERANGE;
0151 
0152     oobregion->offset = 16 * section;
0153     oobregion->length = 16 - nand_chip->ecc.bytes;
0154 
0155     return 0;
0156 }
0157 
0158 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
0159     .ecc = lpc32xx_ooblayout_ecc,
0160     .free = lpc32xx_ooblayout_free,
0161 };
0162 
0163 static struct nand_bbt_descr lpc32xx_nand_bbt = {
0164     .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
0165            NAND_BBT_WRITE,
0166     .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
0167 };
0168 
0169 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
0170     .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
0171            NAND_BBT_WRITE,
0172     .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
0173 };
0174 
0175 struct lpc32xx_nand_host {
0176     struct platform_device  *pdev;
0177     struct nand_chip    nand_chip;
0178     struct lpc32xx_mlc_platform_data *pdata;
0179     struct clk      *clk;
0180     void __iomem        *io_base;
0181     int         irq;
0182     struct lpc32xx_nand_cfg_mlc *ncfg;
0183     struct completion       comp_nand;
0184     struct completion       comp_controller;
0185     uint32_t llptr;
0186     /*
0187      * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
0188      */
0189     dma_addr_t      oob_buf_phy;
0190     /*
0191      * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
0192      */
0193     uint8_t         *oob_buf;
0194     /* Physical address of DMA base address */
0195     dma_addr_t      io_base_phy;
0196 
0197     struct completion   comp_dma;
0198     struct dma_chan     *dma_chan;
0199     struct dma_slave_config dma_slave_config;
0200     struct scatterlist  sgl;
0201     uint8_t         *dma_buf;
0202     uint8_t         *dummy_buf;
0203     int         mlcsubpages; /* number of 512bytes-subpages */
0204 };
0205 
0206 /*
0207  * Activate/Deactivate DMA Operation:
0208  *
0209  * Using the PL080 DMA Controller for transferring the 512 byte subpages
0210  * instead of doing readl() / writel() in a loop slows it down significantly.
0211  * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
0212  *
0213  * - readl() of 128 x 32 bits in a loop: ~20us
0214  * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
0215  * - DMA read of 512 bytes (32 bit, no bursts): ~100us
0216  *
0217  * This applies to the transfer itself. In the DMA case: only the
0218  * wait_for_completion() (DMA setup _not_ included).
0219  *
0220  * Note that the 512 bytes subpage transfer is done directly from/to a
0221  * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
0222  * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
0223  * controller transferring data between its internal buffer to/from the NAND
0224  * chip.)
0225  *
0226  * Therefore, using the PL080 DMA is disabled by default, for now.
0227  *
0228  */
0229 static int use_dma;
0230 
0231 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
0232 {
0233     uint32_t clkrate, tmp;
0234 
0235     /* Reset MLC controller */
0236     writel(MLCCMD_RESET, MLC_CMD(host->io_base));
0237     udelay(1000);
0238 
0239     /* Get base clock for MLC block */
0240     clkrate = clk_get_rate(host->clk);
0241     if (clkrate == 0)
0242         clkrate = 104000000;
0243 
0244     /* Unlock MLC_ICR
0245      * (among others, will be locked again automatically) */
0246     writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
0247 
0248     /* Configure MLC Controller: Large Block, 5 Byte Address */
0249     tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
0250     writel(tmp, MLC_ICR(host->io_base));
0251 
0252     /* Unlock MLC_TIME_REG
0253      * (among others, will be locked again automatically) */
0254     writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
0255 
0256     /* Compute clock setup values, see LPC and NAND manual */
0257     tmp = 0;
0258     tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
0259     tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
0260     tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
0261     tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
0262     tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
0263     tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
0264     tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
0265     writel(tmp, MLC_TIME_REG(host->io_base));
0266 
0267     /* Enable IRQ for CONTROLLER_READY and NAND_READY */
0268     writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
0269             MLC_IRQ_MR(host->io_base));
0270 
0271     /* Normal nCE operation: nCE controlled by controller */
0272     writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
0273 }
0274 
0275 /*
0276  * Hardware specific access to control lines
0277  */
0278 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
0279                   unsigned int ctrl)
0280 {
0281     struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
0282 
0283     if (cmd != NAND_CMD_NONE) {
0284         if (ctrl & NAND_CLE)
0285             writel(cmd, MLC_CMD(host->io_base));
0286         else
0287             writel(cmd, MLC_ADDR(host->io_base));
0288     }
0289 }
0290 
0291 /*
0292  * Read Device Ready (NAND device _and_ controller ready)
0293  */
0294 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
0295 {
0296     struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
0297 
0298     if ((readb(MLC_ISR(host->io_base)) &
0299          (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
0300         (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
0301         return  1;
0302 
0303     return 0;
0304 }
0305 
0306 static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
0307 {
0308     uint8_t sr;
0309 
0310     /* Clear interrupt flag by reading status */
0311     sr = readb(MLC_IRQ_SR(host->io_base));
0312     if (sr & MLCIRQ_NAND_READY)
0313         complete(&host->comp_nand);
0314     if (sr & MLCIRQ_CONTROLLER_READY)
0315         complete(&host->comp_controller);
0316 
0317     return IRQ_HANDLED;
0318 }
0319 
0320 static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
0321 {
0322     struct mtd_info *mtd = nand_to_mtd(chip);
0323     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0324 
0325     if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
0326         goto exit;
0327 
0328     wait_for_completion(&host->comp_nand);
0329 
0330     while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
0331         /* Seems to be delayed sometimes by controller */
0332         dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
0333         cpu_relax();
0334     }
0335 
0336 exit:
0337     return NAND_STATUS_READY;
0338 }
0339 
0340 static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
0341 {
0342     struct mtd_info *mtd = nand_to_mtd(chip);
0343     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0344 
0345     if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
0346         goto exit;
0347 
0348     wait_for_completion(&host->comp_controller);
0349 
0350     while (!(readb(MLC_ISR(host->io_base)) &
0351          MLCISR_CONTROLLER_READY)) {
0352         dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
0353         cpu_relax();
0354     }
0355 
0356 exit:
0357     return NAND_STATUS_READY;
0358 }
0359 
0360 static int lpc32xx_waitfunc(struct nand_chip *chip)
0361 {
0362     lpc32xx_waitfunc_nand(chip);
0363     lpc32xx_waitfunc_controller(chip);
0364 
0365     return NAND_STATUS_READY;
0366 }
0367 
0368 /*
0369  * Enable NAND write protect
0370  */
0371 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
0372 {
0373     if (gpio_is_valid(host->ncfg->wp_gpio))
0374         gpio_set_value(host->ncfg->wp_gpio, 0);
0375 }
0376 
0377 /*
0378  * Disable NAND write protect
0379  */
0380 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
0381 {
0382     if (gpio_is_valid(host->ncfg->wp_gpio))
0383         gpio_set_value(host->ncfg->wp_gpio, 1);
0384 }
0385 
0386 static void lpc32xx_dma_complete_func(void *completion)
0387 {
0388     complete(completion);
0389 }
0390 
0391 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
0392                 enum dma_transfer_direction dir)
0393 {
0394     struct nand_chip *chip = mtd_to_nand(mtd);
0395     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0396     struct dma_async_tx_descriptor *desc;
0397     int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
0398     int res;
0399 
0400     sg_init_one(&host->sgl, mem, len);
0401 
0402     res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
0403              DMA_BIDIRECTIONAL);
0404     if (res != 1) {
0405         dev_err(mtd->dev.parent, "Failed to map sg list\n");
0406         return -ENXIO;
0407     }
0408     desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
0409                        flags);
0410     if (!desc) {
0411         dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
0412         goto out1;
0413     }
0414 
0415     init_completion(&host->comp_dma);
0416     desc->callback = lpc32xx_dma_complete_func;
0417     desc->callback_param = &host->comp_dma;
0418 
0419     dmaengine_submit(desc);
0420     dma_async_issue_pending(host->dma_chan);
0421 
0422     wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
0423 
0424     dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
0425              DMA_BIDIRECTIONAL);
0426     return 0;
0427 out1:
0428     dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
0429              DMA_BIDIRECTIONAL);
0430     return -ENXIO;
0431 }
0432 
0433 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
0434                  int oob_required, int page)
0435 {
0436     struct mtd_info *mtd = nand_to_mtd(chip);
0437     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0438     int i, j;
0439     uint8_t *oobbuf = chip->oob_poi;
0440     uint32_t mlc_isr;
0441     int res;
0442     uint8_t *dma_buf;
0443     bool dma_mapped;
0444 
0445     if ((void *)buf <= high_memory) {
0446         dma_buf = buf;
0447         dma_mapped = true;
0448     } else {
0449         dma_buf = host->dma_buf;
0450         dma_mapped = false;
0451     }
0452 
0453     /* Writing Command and Address */
0454     nand_read_page_op(chip, page, 0, NULL, 0);
0455 
0456     /* For all sub-pages */
0457     for (i = 0; i < host->mlcsubpages; i++) {
0458         /* Start Auto Decode Command */
0459         writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
0460 
0461         /* Wait for Controller Ready */
0462         lpc32xx_waitfunc_controller(chip);
0463 
0464         /* Check ECC Error status */
0465         mlc_isr = readl(MLC_ISR(host->io_base));
0466         if (mlc_isr & MLCISR_DECODER_FAILURE) {
0467             mtd->ecc_stats.failed++;
0468             dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
0469         } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
0470             mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
0471         }
0472 
0473         /* Read 512 + 16 Bytes */
0474         if (use_dma) {
0475             res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
0476                            DMA_DEV_TO_MEM);
0477             if (res)
0478                 return res;
0479         } else {
0480             for (j = 0; j < (512 >> 2); j++) {
0481                 *((uint32_t *)(buf)) =
0482                     readl(MLC_BUFF(host->io_base));
0483                 buf += 4;
0484             }
0485         }
0486         for (j = 0; j < (16 >> 2); j++) {
0487             *((uint32_t *)(oobbuf)) =
0488                 readl(MLC_BUFF(host->io_base));
0489             oobbuf += 4;
0490         }
0491     }
0492 
0493     if (use_dma && !dma_mapped)
0494         memcpy(buf, dma_buf, mtd->writesize);
0495 
0496     return 0;
0497 }
0498 
0499 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
0500                        const uint8_t *buf, int oob_required,
0501                        int page)
0502 {
0503     struct mtd_info *mtd = nand_to_mtd(chip);
0504     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0505     const uint8_t *oobbuf = chip->oob_poi;
0506     uint8_t *dma_buf = (uint8_t *)buf;
0507     int res;
0508     int i, j;
0509 
0510     if (use_dma && (void *)buf >= high_memory) {
0511         dma_buf = host->dma_buf;
0512         memcpy(dma_buf, buf, mtd->writesize);
0513     }
0514 
0515     nand_prog_page_begin_op(chip, page, 0, NULL, 0);
0516 
0517     for (i = 0; i < host->mlcsubpages; i++) {
0518         /* Start Encode */
0519         writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
0520 
0521         /* Write 512 + 6 Bytes to Buffer */
0522         if (use_dma) {
0523             res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
0524                            DMA_MEM_TO_DEV);
0525             if (res)
0526                 return res;
0527         } else {
0528             for (j = 0; j < (512 >> 2); j++) {
0529                 writel(*((uint32_t *)(buf)),
0530                        MLC_BUFF(host->io_base));
0531                 buf += 4;
0532             }
0533         }
0534         writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
0535         oobbuf += 4;
0536         writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
0537         oobbuf += 12;
0538 
0539         /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
0540         writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
0541 
0542         /* Wait for Controller Ready */
0543         lpc32xx_waitfunc_controller(chip);
0544     }
0545 
0546     return nand_prog_page_end_op(chip);
0547 }
0548 
0549 static int lpc32xx_read_oob(struct nand_chip *chip, int page)
0550 {
0551     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0552 
0553     /* Read whole page - necessary with MLC controller! */
0554     lpc32xx_read_page(chip, host->dummy_buf, 1, page);
0555 
0556     return 0;
0557 }
0558 
0559 static int lpc32xx_write_oob(struct nand_chip *chip, int page)
0560 {
0561     /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
0562     return 0;
0563 }
0564 
0565 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
0566 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
0567 {
0568     /* Always enabled! */
0569 }
0570 
0571 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
0572 {
0573     struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
0574     dma_cap_mask_t mask;
0575 
0576     if (!host->pdata || !host->pdata->dma_filter) {
0577         dev_err(mtd->dev.parent, "no DMA platform data\n");
0578         return -ENOENT;
0579     }
0580 
0581     dma_cap_zero(mask);
0582     dma_cap_set(DMA_SLAVE, mask);
0583     host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
0584                          "nand-mlc");
0585     if (!host->dma_chan) {
0586         dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
0587         return -EBUSY;
0588     }
0589 
0590     /*
0591      * Set direction to a sensible value even if the dmaengine driver
0592      * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
0593      * driver criticizes it as "alien transfer direction".
0594      */
0595     host->dma_slave_config.direction = DMA_DEV_TO_MEM;
0596     host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0597     host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0598     host->dma_slave_config.src_maxburst = 128;
0599     host->dma_slave_config.dst_maxburst = 128;
0600     /* DMA controller does flow control: */
0601     host->dma_slave_config.device_fc = false;
0602     host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
0603     host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
0604     if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
0605         dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
0606         goto out1;
0607     }
0608 
0609     return 0;
0610 out1:
0611     dma_release_channel(host->dma_chan);
0612     return -ENXIO;
0613 }
0614 
0615 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
0616 {
0617     struct lpc32xx_nand_cfg_mlc *ncfg;
0618     struct device_node *np = dev->of_node;
0619 
0620     ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
0621     if (!ncfg)
0622         return NULL;
0623 
0624     of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
0625     of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
0626     of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
0627     of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
0628     of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
0629     of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
0630     of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
0631 
0632     if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
0633         !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
0634         !ncfg->wr_low) {
0635         dev_err(dev, "chip parameters not specified correctly\n");
0636         return NULL;
0637     }
0638 
0639     ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
0640 
0641     return ncfg;
0642 }
0643 
0644 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
0645 {
0646     struct mtd_info *mtd = nand_to_mtd(chip);
0647     struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
0648     struct device *dev = &host->pdev->dev;
0649 
0650     if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
0651         return 0;
0652 
0653     host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
0654     if (!host->dma_buf)
0655         return -ENOMEM;
0656 
0657     host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
0658     if (!host->dummy_buf)
0659         return -ENOMEM;
0660 
0661     chip->ecc.size = 512;
0662     chip->ecc.hwctl = lpc32xx_ecc_enable;
0663     chip->ecc.read_page_raw = lpc32xx_read_page;
0664     chip->ecc.read_page = lpc32xx_read_page;
0665     chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
0666     chip->ecc.write_page = lpc32xx_write_page_lowlevel;
0667     chip->ecc.write_oob = lpc32xx_write_oob;
0668     chip->ecc.read_oob = lpc32xx_read_oob;
0669     chip->ecc.strength = 4;
0670     chip->ecc.bytes = 10;
0671 
0672     mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
0673     host->mlcsubpages = mtd->writesize / 512;
0674 
0675     return 0;
0676 }
0677 
0678 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
0679     .attach_chip = lpc32xx_nand_attach_chip,
0680 };
0681 
0682 /*
0683  * Probe for NAND controller
0684  */
0685 static int lpc32xx_nand_probe(struct platform_device *pdev)
0686 {
0687     struct lpc32xx_nand_host *host;
0688     struct mtd_info *mtd;
0689     struct nand_chip *nand_chip;
0690     struct resource *rc;
0691     int res;
0692 
0693     /* Allocate memory for the device structure (and zero it) */
0694     host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
0695     if (!host)
0696         return -ENOMEM;
0697 
0698     host->pdev = pdev;
0699 
0700     rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0701     host->io_base = devm_ioremap_resource(&pdev->dev, rc);
0702     if (IS_ERR(host->io_base))
0703         return PTR_ERR(host->io_base);
0704 
0705     host->io_base_phy = rc->start;
0706 
0707     nand_chip = &host->nand_chip;
0708     mtd = nand_to_mtd(nand_chip);
0709     if (pdev->dev.of_node)
0710         host->ncfg = lpc32xx_parse_dt(&pdev->dev);
0711     if (!host->ncfg) {
0712         dev_err(&pdev->dev,
0713             "Missing or bad NAND config from device tree\n");
0714         return -ENOENT;
0715     }
0716     if (host->ncfg->wp_gpio == -EPROBE_DEFER)
0717         return -EPROBE_DEFER;
0718     if (gpio_is_valid(host->ncfg->wp_gpio) &&
0719             gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
0720         dev_err(&pdev->dev, "GPIO not available\n");
0721         return -EBUSY;
0722     }
0723     lpc32xx_wp_disable(host);
0724 
0725     host->pdata = dev_get_platdata(&pdev->dev);
0726 
0727     /* link the private data structures */
0728     nand_set_controller_data(nand_chip, host);
0729     nand_set_flash_node(nand_chip, pdev->dev.of_node);
0730     mtd->dev.parent = &pdev->dev;
0731 
0732     /* Get NAND clock */
0733     host->clk = clk_get(&pdev->dev, NULL);
0734     if (IS_ERR(host->clk)) {
0735         dev_err(&pdev->dev, "Clock initialization failure\n");
0736         res = -ENOENT;
0737         goto free_gpio;
0738     }
0739     res = clk_prepare_enable(host->clk);
0740     if (res)
0741         goto put_clk;
0742 
0743     nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
0744     nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
0745     nand_chip->legacy.chip_delay = 25; /* us */
0746     nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
0747     nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
0748 
0749     /* Init NAND controller */
0750     lpc32xx_nand_setup(host);
0751 
0752     platform_set_drvdata(pdev, host);
0753 
0754     /* Initialize function pointers */
0755     nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
0756 
0757     nand_chip->options = NAND_NO_SUBPAGE_WRITE;
0758     nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
0759     nand_chip->bbt_td = &lpc32xx_nand_bbt;
0760     nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
0761 
0762     if (use_dma) {
0763         res = lpc32xx_dma_setup(host);
0764         if (res) {
0765             res = -EIO;
0766             goto unprepare_clk;
0767         }
0768     }
0769 
0770     /* initially clear interrupt status */
0771     readb(MLC_IRQ_SR(host->io_base));
0772 
0773     init_completion(&host->comp_nand);
0774     init_completion(&host->comp_controller);
0775 
0776     host->irq = platform_get_irq(pdev, 0);
0777     if (host->irq < 0) {
0778         res = -EINVAL;
0779         goto release_dma_chan;
0780     }
0781 
0782     if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
0783             IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
0784         dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
0785         res = -ENXIO;
0786         goto release_dma_chan;
0787     }
0788 
0789     /*
0790      * Scan to find existence of the device and get the type of NAND device:
0791      * SMALL block or LARGE block.
0792      */
0793     nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
0794     res = nand_scan(nand_chip, 1);
0795     if (res)
0796         goto free_irq;
0797 
0798     mtd->name = DRV_NAME;
0799 
0800     res = mtd_device_register(mtd, host->ncfg->parts,
0801                   host->ncfg->num_parts);
0802     if (res)
0803         goto cleanup_nand;
0804 
0805     return 0;
0806 
0807 cleanup_nand:
0808     nand_cleanup(nand_chip);
0809 free_irq:
0810     free_irq(host->irq, host);
0811 release_dma_chan:
0812     if (use_dma)
0813         dma_release_channel(host->dma_chan);
0814 unprepare_clk:
0815     clk_disable_unprepare(host->clk);
0816 put_clk:
0817     clk_put(host->clk);
0818 free_gpio:
0819     lpc32xx_wp_enable(host);
0820     gpio_free(host->ncfg->wp_gpio);
0821 
0822     return res;
0823 }
0824 
0825 /*
0826  * Remove NAND device
0827  */
0828 static int lpc32xx_nand_remove(struct platform_device *pdev)
0829 {
0830     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0831     struct nand_chip *chip = &host->nand_chip;
0832     int ret;
0833 
0834     ret = mtd_device_unregister(nand_to_mtd(chip));
0835     WARN_ON(ret);
0836     nand_cleanup(chip);
0837 
0838     free_irq(host->irq, host);
0839     if (use_dma)
0840         dma_release_channel(host->dma_chan);
0841 
0842     clk_disable_unprepare(host->clk);
0843     clk_put(host->clk);
0844 
0845     lpc32xx_wp_enable(host);
0846     gpio_free(host->ncfg->wp_gpio);
0847 
0848     return 0;
0849 }
0850 
0851 #ifdef CONFIG_PM
0852 static int lpc32xx_nand_resume(struct platform_device *pdev)
0853 {
0854     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0855     int ret;
0856 
0857     /* Re-enable NAND clock */
0858     ret = clk_prepare_enable(host->clk);
0859     if (ret)
0860         return ret;
0861 
0862     /* Fresh init of NAND controller */
0863     lpc32xx_nand_setup(host);
0864 
0865     /* Disable write protect */
0866     lpc32xx_wp_disable(host);
0867 
0868     return 0;
0869 }
0870 
0871 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
0872 {
0873     struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
0874 
0875     /* Enable write protect for safety */
0876     lpc32xx_wp_enable(host);
0877 
0878     /* Disable clock */
0879     clk_disable_unprepare(host->clk);
0880     return 0;
0881 }
0882 
0883 #else
0884 #define lpc32xx_nand_resume NULL
0885 #define lpc32xx_nand_suspend NULL
0886 #endif
0887 
0888 static const struct of_device_id lpc32xx_nand_match[] = {
0889     { .compatible = "nxp,lpc3220-mlc" },
0890     { /* sentinel */ },
0891 };
0892 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
0893 
0894 static struct platform_driver lpc32xx_nand_driver = {
0895     .probe      = lpc32xx_nand_probe,
0896     .remove     = lpc32xx_nand_remove,
0897     .resume     = lpc32xx_nand_resume,
0898     .suspend    = lpc32xx_nand_suspend,
0899     .driver     = {
0900         .name   = DRV_NAME,
0901         .of_match_table = lpc32xx_nand_match,
0902     },
0903 };
0904 
0905 module_platform_driver(lpc32xx_nand_driver);
0906 
0907 MODULE_LICENSE("GPL");
0908 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
0909 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
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