0001
0002
0003
0004 #include <linux/clk.h>
0005 #include <linux/completion.h>
0006 #include <linux/dmaengine.h>
0007 #include <linux/dma-direction.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/err.h>
0010 #include <linux/init.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/rawnand.h>
0017 #include <linux/mtd/nand.h>
0018
0019 #include <linux/platform_device.h>
0020 #include <linux/sched.h>
0021 #include <linux/slab.h>
0022 #include <linux/types.h>
0023 #include <linux/units.h>
0024 #include <asm/unaligned.h>
0025
0026 #define EBU_CLC 0x000
0027 #define EBU_CLC_RST 0x00000000u
0028
0029 #define EBU_ADDR_SEL(n) (0x020 + (n) * 4)
0030
0031 #define EBU_ADDR_MASK(x) ((x) << 4)
0032 #define EBU_ADDR_SEL_REGEN 0x1
0033
0034 #define EBU_BUSCON(n) (0x060 + (n) * 4)
0035 #define EBU_BUSCON_CMULT_V4 0x1
0036 #define EBU_BUSCON_RECOVC(n) ((n) << 2)
0037 #define EBU_BUSCON_HOLDC(n) ((n) << 4)
0038 #define EBU_BUSCON_WAITRDC(n) ((n) << 6)
0039 #define EBU_BUSCON_WAITWRC(n) ((n) << 8)
0040 #define EBU_BUSCON_BCGEN_CS 0x0
0041 #define EBU_BUSCON_SETUP_EN BIT(22)
0042 #define EBU_BUSCON_ALEC 0xC000
0043
0044 #define EBU_CON 0x0B0
0045 #define EBU_CON_NANDM_EN BIT(0)
0046 #define EBU_CON_NANDM_DIS 0x0
0047 #define EBU_CON_CSMUX_E_EN BIT(1)
0048 #define EBU_CON_ALE_P_LOW BIT(2)
0049 #define EBU_CON_CLE_P_LOW BIT(3)
0050 #define EBU_CON_CS_P_LOW BIT(4)
0051 #define EBU_CON_SE_P_LOW BIT(5)
0052 #define EBU_CON_WP_P_LOW BIT(6)
0053 #define EBU_CON_PRE_P_LOW BIT(7)
0054 #define EBU_CON_IN_CS_S(n) ((n) << 8)
0055 #define EBU_CON_OUT_CS_S(n) ((n) << 10)
0056 #define EBU_CON_LAT_EN_CS_P ((0x3D) << 18)
0057
0058 #define EBU_WAIT 0x0B4
0059 #define EBU_WAIT_RDBY BIT(0)
0060 #define EBU_WAIT_WR_C BIT(3)
0061
0062 #define HSNAND_CTL1 0x110
0063 #define HSNAND_CTL1_ADDR_SHIFT 24
0064
0065 #define HSNAND_CTL2 0x114
0066 #define HSNAND_CTL2_ADDR_SHIFT 8
0067 #define HSNAND_CTL2_CYC_N_V5 (0x2 << 16)
0068
0069 #define HSNAND_INT_MSK_CTL 0x124
0070 #define HSNAND_INT_MSK_CTL_WR_C BIT(4)
0071
0072 #define HSNAND_INT_STA 0x128
0073 #define HSNAND_INT_STA_WR_C BIT(4)
0074
0075 #define HSNAND_CTL 0x130
0076 #define HSNAND_CTL_ENABLE_ECC BIT(0)
0077 #define HSNAND_CTL_GO BIT(2)
0078 #define HSNAND_CTL_CE_SEL_CS(n) BIT(3 + (n))
0079 #define HSNAND_CTL_RW_READ 0x0
0080 #define HSNAND_CTL_RW_WRITE BIT(10)
0081 #define HSNAND_CTL_ECC_OFF_V8TH BIT(11)
0082 #define HSNAND_CTL_CKFF_EN 0x0
0083 #define HSNAND_CTL_MSG_EN BIT(17)
0084
0085 #define HSNAND_PARA0 0x13c
0086 #define HSNAND_PARA0_PAGE_V8192 0x3
0087 #define HSNAND_PARA0_PIB_V256 (0x3 << 4)
0088 #define HSNAND_PARA0_BYP_EN_NP 0x0
0089 #define HSNAND_PARA0_BYP_DEC_NP 0x0
0090 #define HSNAND_PARA0_TYPE_ONFI BIT(18)
0091 #define HSNAND_PARA0_ADEP_EN BIT(21)
0092
0093 #define HSNAND_CMSG_0 0x150
0094 #define HSNAND_CMSG_1 0x154
0095
0096 #define HSNAND_ALE_OFFS BIT(2)
0097 #define HSNAND_CLE_OFFS BIT(3)
0098 #define HSNAND_CS_OFFS BIT(4)
0099
0100 #define HSNAND_ECC_OFFSET 0x008
0101
0102 #define NAND_DATA_IFACE_CHECK_ONLY -1
0103
0104 #define MAX_CS 2
0105
0106 #define USEC_PER_SEC 1000000L
0107
0108 struct ebu_nand_cs {
0109 void __iomem *chipaddr;
0110 dma_addr_t nand_pa;
0111 u32 addr_sel;
0112 };
0113
0114 struct ebu_nand_controller {
0115 struct nand_controller controller;
0116 struct nand_chip chip;
0117 struct device *dev;
0118 void __iomem *ebu;
0119 void __iomem *hsnand;
0120 struct dma_chan *dma_tx;
0121 struct dma_chan *dma_rx;
0122 struct completion dma_access_complete;
0123 unsigned long clk_rate;
0124 struct clk *clk;
0125 u32 nd_para0;
0126 u8 cs_num;
0127 struct ebu_nand_cs cs[MAX_CS];
0128 };
0129
0130 static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip)
0131 {
0132 return container_of(chip, struct ebu_nand_controller, chip);
0133 }
0134
0135 static int ebu_nand_waitrdy(struct nand_chip *chip, int timeout_ms)
0136 {
0137 struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
0138 u32 status;
0139
0140 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status,
0141 (status & EBU_WAIT_RDBY) ||
0142 (status & EBU_WAIT_WR_C), 20, timeout_ms);
0143 }
0144
0145 static u8 ebu_nand_readb(struct nand_chip *chip)
0146 {
0147 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0148 u8 cs_num = ebu_host->cs_num;
0149 u8 val;
0150
0151 val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS);
0152 ebu_nand_waitrdy(chip, 1000);
0153 return val;
0154 }
0155
0156 static void ebu_nand_writeb(struct nand_chip *chip, u32 offset, u8 value)
0157 {
0158 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0159 u8 cs_num = ebu_host->cs_num;
0160
0161 writeb(value, ebu_host->cs[cs_num].chipaddr + offset);
0162 ebu_nand_waitrdy(chip, 1000);
0163 }
0164
0165 static void ebu_read_buf(struct nand_chip *chip, u_char *buf, unsigned int len)
0166 {
0167 int i;
0168
0169 for (i = 0; i < len; i++)
0170 buf[i] = ebu_nand_readb(chip);
0171 }
0172
0173 static void ebu_write_buf(struct nand_chip *chip, const u_char *buf, int len)
0174 {
0175 int i;
0176
0177 for (i = 0; i < len; i++)
0178 ebu_nand_writeb(chip, HSNAND_CS_OFFS, buf[i]);
0179 }
0180
0181 static void ebu_nand_disable(struct nand_chip *chip)
0182 {
0183 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0184
0185 writel(0, ebu_host->ebu + EBU_CON);
0186 }
0187
0188 static void ebu_select_chip(struct nand_chip *chip)
0189 {
0190 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0191 void __iomem *nand_con = ebu_host->ebu + EBU_CON;
0192 u32 cs = ebu_host->cs_num;
0193
0194 writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW |
0195 EBU_CON_SE_P_LOW | EBU_CON_WP_P_LOW | EBU_CON_PRE_P_LOW |
0196 EBU_CON_IN_CS_S(cs) | EBU_CON_OUT_CS_S(cs) |
0197 EBU_CON_LAT_EN_CS_P, nand_con);
0198 }
0199
0200 static int ebu_nand_set_timings(struct nand_chip *chip, int csline,
0201 const struct nand_interface_config *conf)
0202 {
0203 struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
0204 unsigned int rate = clk_get_rate(ctrl->clk) / HZ_PER_MHZ;
0205 unsigned int period = DIV_ROUND_UP(USEC_PER_SEC, rate);
0206 const struct nand_sdr_timings *timings;
0207 u32 trecov, thold, twrwait, trdwait;
0208 u32 reg = 0;
0209
0210 timings = nand_get_sdr_timings(conf);
0211 if (IS_ERR(timings))
0212 return PTR_ERR(timings);
0213
0214 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
0215 return 0;
0216
0217 trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min),
0218 period);
0219 reg |= EBU_BUSCON_RECOVC(trecov);
0220
0221 thold = DIV_ROUND_UP(max(timings->tDH_min, timings->tDS_min), period);
0222 reg |= EBU_BUSCON_HOLDC(thold);
0223
0224 trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min),
0225 period);
0226 reg |= EBU_BUSCON_WAITRDC(trdwait);
0227
0228 twrwait = DIV_ROUND_UP(max(timings->tWC_min, timings->tWH_min), period);
0229 reg |= EBU_BUSCON_WAITWRC(twrwait);
0230
0231 reg |= EBU_BUSCON_CMULT_V4 | EBU_BUSCON_BCGEN_CS | EBU_BUSCON_ALEC |
0232 EBU_BUSCON_SETUP_EN;
0233
0234 writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num));
0235
0236 return 0;
0237 }
0238
0239 static int ebu_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
0240 struct mtd_oob_region *oobregion)
0241 {
0242 struct nand_chip *chip = mtd_to_nand(mtd);
0243
0244 if (section)
0245 return -ERANGE;
0246
0247 oobregion->offset = HSNAND_ECC_OFFSET;
0248 oobregion->length = chip->ecc.total;
0249
0250 return 0;
0251 }
0252
0253 static int ebu_nand_ooblayout_free(struct mtd_info *mtd, int section,
0254 struct mtd_oob_region *oobregion)
0255 {
0256 struct nand_chip *chip = mtd_to_nand(mtd);
0257
0258 if (section)
0259 return -ERANGE;
0260
0261 oobregion->offset = chip->ecc.total + HSNAND_ECC_OFFSET;
0262 oobregion->length = mtd->oobsize - oobregion->offset;
0263
0264 return 0;
0265 }
0266
0267 static const struct mtd_ooblayout_ops ebu_nand_ooblayout_ops = {
0268 .ecc = ebu_nand_ooblayout_ecc,
0269 .free = ebu_nand_ooblayout_free,
0270 };
0271
0272 static void ebu_dma_rx_callback(void *cookie)
0273 {
0274 struct ebu_nand_controller *ebu_host = cookie;
0275
0276 dmaengine_terminate_async(ebu_host->dma_rx);
0277
0278 complete(&ebu_host->dma_access_complete);
0279 }
0280
0281 static void ebu_dma_tx_callback(void *cookie)
0282 {
0283 struct ebu_nand_controller *ebu_host = cookie;
0284
0285 dmaengine_terminate_async(ebu_host->dma_tx);
0286
0287 complete(&ebu_host->dma_access_complete);
0288 }
0289
0290 static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
0291 const u8 *buf, u32 len)
0292 {
0293 struct dma_async_tx_descriptor *tx;
0294 struct completion *dma_completion;
0295 dma_async_tx_callback callback;
0296 struct dma_chan *chan;
0297 dma_cookie_t cookie;
0298 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
0299 dma_addr_t buf_dma;
0300 int ret;
0301 u32 timeout;
0302
0303 if (dir == DMA_DEV_TO_MEM) {
0304 chan = ebu_host->dma_rx;
0305 dma_completion = &ebu_host->dma_access_complete;
0306 callback = ebu_dma_rx_callback;
0307 } else {
0308 chan = ebu_host->dma_tx;
0309 dma_completion = &ebu_host->dma_access_complete;
0310 callback = ebu_dma_tx_callback;
0311 }
0312
0313 buf_dma = dma_map_single(chan->device->dev, (void *)buf, len, dir);
0314 if (dma_mapping_error(chan->device->dev, buf_dma)) {
0315 dev_err(ebu_host->dev, "Failed to map DMA buffer\n");
0316 ret = -EIO;
0317 goto err_unmap;
0318 }
0319
0320 tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
0321 if (!tx) {
0322 ret = -ENXIO;
0323 goto err_unmap;
0324 }
0325
0326 tx->callback = callback;
0327 tx->callback_param = ebu_host;
0328 cookie = tx->tx_submit(tx);
0329
0330 ret = dma_submit_error(cookie);
0331 if (ret) {
0332 dev_err(ebu_host->dev, "dma_submit_error %d\n", cookie);
0333 ret = -EIO;
0334 goto err_unmap;
0335 }
0336
0337 init_completion(dma_completion);
0338 dma_async_issue_pending(chan);
0339
0340
0341 timeout = wait_for_completion_timeout(dma_completion, msecs_to_jiffies(1000));
0342 if (!timeout) {
0343 dev_err(ebu_host->dev, "I/O Error in DMA RX (status %d)\n",
0344 dmaengine_tx_status(chan, cookie, NULL));
0345 dmaengine_terminate_sync(chan);
0346 ret = -ETIMEDOUT;
0347 goto err_unmap;
0348 }
0349
0350 return 0;
0351
0352 err_unmap:
0353 dma_unmap_single(ebu_host->dev, buf_dma, len, dir);
0354
0355 return ret;
0356 }
0357
0358 static void ebu_nand_trigger(struct ebu_nand_controller *ebu_host,
0359 int page, u32 cmd)
0360 {
0361 unsigned int val;
0362
0363 val = cmd | (page & 0xFF) << HSNAND_CTL1_ADDR_SHIFT;
0364 writel(val, ebu_host->hsnand + HSNAND_CTL1);
0365 val = (page & 0xFFFF00) >> 8 | HSNAND_CTL2_CYC_N_V5;
0366 writel(val, ebu_host->hsnand + HSNAND_CTL2);
0367
0368 writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0);
0369
0370
0371 writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0);
0372 writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1);
0373
0374 writel(HSNAND_INT_MSK_CTL_WR_C,
0375 ebu_host->hsnand + HSNAND_INT_MSK_CTL);
0376
0377 if (!cmd)
0378 val = HSNAND_CTL_RW_READ;
0379 else
0380 val = HSNAND_CTL_RW_WRITE;
0381
0382 writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN |
0383 HSNAND_CTL_ECC_OFF_V8TH | HSNAND_CTL_CE_SEL_CS(ebu_host->cs_num) |
0384 HSNAND_CTL_ENABLE_ECC | HSNAND_CTL_GO | val,
0385 ebu_host->hsnand + HSNAND_CTL);
0386 }
0387
0388 static int ebu_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
0389 int oob_required, int page)
0390 {
0391 struct mtd_info *mtd = nand_to_mtd(chip);
0392 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0393 int ret, reg_data;
0394
0395 ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0);
0396
0397 ret = ebu_dma_start(ebu_host, DMA_DEV_TO_MEM, buf, mtd->writesize);
0398 if (ret)
0399 return ret;
0400
0401 if (oob_required)
0402 chip->ecc.read_oob(chip, page);
0403
0404 reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
0405 reg_data &= ~HSNAND_CTL_GO;
0406 writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
0407
0408 return 0;
0409 }
0410
0411 static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
0412 int oob_required, int page)
0413 {
0414 struct mtd_info *mtd = nand_to_mtd(chip);
0415 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0416 void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA;
0417 int reg_data, ret, val;
0418 u32 reg;
0419
0420 ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
0421
0422 ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize);
0423 if (ret)
0424 return ret;
0425
0426 if (oob_required) {
0427 reg = get_unaligned_le32(chip->oob_poi);
0428 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
0429
0430 reg = get_unaligned_le32(chip->oob_poi + 4);
0431 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
0432 }
0433
0434 ret = readl_poll_timeout_atomic(int_sta, val, !(val & HSNAND_INT_STA_WR_C),
0435 10, 1000);
0436 if (ret)
0437 return ret;
0438
0439 reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
0440 reg_data &= ~HSNAND_CTL_GO;
0441 writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
0442
0443 return 0;
0444 }
0445
0446 static const u8 ecc_strength[] = { 1, 1, 4, 8, 24, 32, 40, 60, };
0447
0448 static int ebu_nand_attach_chip(struct nand_chip *chip)
0449 {
0450 struct mtd_info *mtd = nand_to_mtd(chip);
0451 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
0452 u32 ecc_steps, ecc_bytes, ecc_total, pagesize, pg_per_blk;
0453 u32 ecc_strength_ds = chip->ecc.strength;
0454 u32 ecc_size = chip->ecc.size;
0455 u32 writesize = mtd->writesize;
0456 u32 blocksize = mtd->erasesize;
0457 int bch_algo, start, val;
0458
0459
0460 if (!chip->ecc.size)
0461 chip->ecc.size = 512;
0462
0463 switch (ecc_size) {
0464 case 512:
0465 start = 1;
0466 if (!ecc_strength_ds)
0467 ecc_strength_ds = 4;
0468 break;
0469 case 1024:
0470 start = 4;
0471 if (!ecc_strength_ds)
0472 ecc_strength_ds = 32;
0473 break;
0474 default:
0475 return -EINVAL;
0476 }
0477
0478
0479 bch_algo = round_up(start + 1, 4);
0480 for (val = start; val < bch_algo; val++) {
0481 if (ecc_strength_ds == ecc_strength[val])
0482 break;
0483 }
0484 if (val == bch_algo)
0485 return -EINVAL;
0486
0487 if (ecc_strength_ds == 8)
0488 ecc_bytes = 14;
0489 else
0490 ecc_bytes = DIV_ROUND_UP(ecc_strength_ds * fls(8 * ecc_size), 8);
0491
0492 ecc_steps = writesize / ecc_size;
0493 ecc_total = ecc_steps * ecc_bytes;
0494 if ((ecc_total + 8) > mtd->oobsize)
0495 return -ERANGE;
0496
0497 chip->ecc.total = ecc_total;
0498 pagesize = fls(writesize >> 11);
0499 if (pagesize > HSNAND_PARA0_PAGE_V8192)
0500 return -ERANGE;
0501
0502 pg_per_blk = fls((blocksize / writesize) >> 6) / 8;
0503 if (pg_per_blk > HSNAND_PARA0_PIB_V256)
0504 return -ERANGE;
0505
0506 ebu_host->nd_para0 = pagesize | pg_per_blk | HSNAND_PARA0_BYP_EN_NP |
0507 HSNAND_PARA0_BYP_DEC_NP | HSNAND_PARA0_ADEP_EN |
0508 HSNAND_PARA0_TYPE_ONFI | (val << 29);
0509
0510 mtd_set_ooblayout(mtd, &ebu_nand_ooblayout_ops);
0511 chip->ecc.read_page = ebu_nand_read_page_hwecc;
0512 chip->ecc.write_page = ebu_nand_write_page_hwecc;
0513
0514 return 0;
0515 }
0516
0517 static int ebu_nand_exec_op(struct nand_chip *chip,
0518 const struct nand_operation *op, bool check_only)
0519 {
0520 const struct nand_op_instr *instr = NULL;
0521 unsigned int op_id;
0522 int i, timeout_ms, ret = 0;
0523
0524 if (check_only)
0525 return 0;
0526
0527 ebu_select_chip(chip);
0528 for (op_id = 0; op_id < op->ninstrs; op_id++) {
0529 instr = &op->instrs[op_id];
0530
0531 switch (instr->type) {
0532 case NAND_OP_CMD_INSTR:
0533 ebu_nand_writeb(chip, HSNAND_CLE_OFFS | HSNAND_CS_OFFS,
0534 instr->ctx.cmd.opcode);
0535 break;
0536
0537 case NAND_OP_ADDR_INSTR:
0538 for (i = 0; i < instr->ctx.addr.naddrs; i++)
0539 ebu_nand_writeb(chip,
0540 HSNAND_ALE_OFFS | HSNAND_CS_OFFS,
0541 instr->ctx.addr.addrs[i]);
0542 break;
0543
0544 case NAND_OP_DATA_IN_INSTR:
0545 ebu_read_buf(chip, instr->ctx.data.buf.in,
0546 instr->ctx.data.len);
0547 break;
0548
0549 case NAND_OP_DATA_OUT_INSTR:
0550 ebu_write_buf(chip, instr->ctx.data.buf.out,
0551 instr->ctx.data.len);
0552 break;
0553
0554 case NAND_OP_WAITRDY_INSTR:
0555 timeout_ms = instr->ctx.waitrdy.timeout_ms * 1000;
0556 ret = ebu_nand_waitrdy(chip, timeout_ms);
0557 break;
0558 }
0559 }
0560
0561 return ret;
0562 }
0563
0564 static const struct nand_controller_ops ebu_nand_controller_ops = {
0565 .attach_chip = ebu_nand_attach_chip,
0566 .setup_interface = ebu_nand_set_timings,
0567 .exec_op = ebu_nand_exec_op,
0568 };
0569
0570 static void ebu_dma_cleanup(struct ebu_nand_controller *ebu_host)
0571 {
0572 if (ebu_host->dma_rx)
0573 dma_release_channel(ebu_host->dma_rx);
0574
0575 if (ebu_host->dma_tx)
0576 dma_release_channel(ebu_host->dma_tx);
0577 }
0578
0579 static int ebu_nand_probe(struct platform_device *pdev)
0580 {
0581 struct device *dev = &pdev->dev;
0582 struct ebu_nand_controller *ebu_host;
0583 struct nand_chip *nand;
0584 struct mtd_info *mtd;
0585 struct resource *res;
0586 char *resname;
0587 int ret;
0588 u32 cs;
0589
0590 ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
0591 if (!ebu_host)
0592 return -ENOMEM;
0593
0594 ebu_host->dev = dev;
0595 nand_controller_init(&ebu_host->controller);
0596
0597 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand");
0598 ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res);
0599 if (IS_ERR(ebu_host->ebu))
0600 return PTR_ERR(ebu_host->ebu);
0601
0602 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand");
0603 ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res);
0604 if (IS_ERR(ebu_host->hsnand))
0605 return PTR_ERR(ebu_host->hsnand);
0606
0607 ret = device_property_read_u32(dev, "reg", &cs);
0608 if (ret) {
0609 dev_err(dev, "failed to get chip select: %d\n", ret);
0610 return ret;
0611 }
0612 if (cs >= MAX_CS) {
0613 dev_err(dev, "got invalid chip select: %d\n", cs);
0614 return -EINVAL;
0615 }
0616
0617 ebu_host->cs_num = cs;
0618
0619 resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", cs);
0620 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname);
0621 ebu_host->cs[cs].chipaddr = devm_ioremap_resource(dev, res);
0622 if (IS_ERR(ebu_host->cs[cs].chipaddr))
0623 return PTR_ERR(ebu_host->cs[cs].chipaddr);
0624 ebu_host->cs[cs].nand_pa = res->start;
0625
0626 ebu_host->clk = devm_clk_get(dev, NULL);
0627 if (IS_ERR(ebu_host->clk))
0628 return dev_err_probe(dev, PTR_ERR(ebu_host->clk),
0629 "failed to get clock\n");
0630
0631 ret = clk_prepare_enable(ebu_host->clk);
0632 if (ret) {
0633 dev_err(dev, "failed to enable clock: %d\n", ret);
0634 return ret;
0635 }
0636 ebu_host->clk_rate = clk_get_rate(ebu_host->clk);
0637
0638 ebu_host->dma_tx = dma_request_chan(dev, "tx");
0639 if (IS_ERR(ebu_host->dma_tx)) {
0640 ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_tx),
0641 "failed to request DMA tx chan!.\n");
0642 goto err_disable_unprepare_clk;
0643 }
0644
0645 ebu_host->dma_rx = dma_request_chan(dev, "rx");
0646 if (IS_ERR(ebu_host->dma_rx)) {
0647 ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_rx),
0648 "failed to request DMA rx chan!.\n");
0649 ebu_host->dma_rx = NULL;
0650 goto err_cleanup_dma;
0651 }
0652
0653 resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", cs);
0654 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname);
0655 if (!res) {
0656 ret = -EINVAL;
0657 goto err_cleanup_dma;
0658 }
0659 ebu_host->cs[cs].addr_sel = res->start;
0660 writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN,
0661 ebu_host->ebu + EBU_ADDR_SEL(cs));
0662
0663 nand_set_flash_node(&ebu_host->chip, dev->of_node);
0664
0665 mtd = nand_to_mtd(&ebu_host->chip);
0666 if (!mtd->name) {
0667 dev_err(ebu_host->dev, "NAND label property is mandatory\n");
0668 ret = -EINVAL;
0669 goto err_cleanup_dma;
0670 }
0671
0672 mtd->dev.parent = dev;
0673 ebu_host->dev = dev;
0674
0675 platform_set_drvdata(pdev, ebu_host);
0676 nand_set_controller_data(&ebu_host->chip, ebu_host);
0677
0678 nand = &ebu_host->chip;
0679 nand->controller = &ebu_host->controller;
0680 nand->controller->ops = &ebu_nand_controller_ops;
0681
0682
0683 ret = nand_scan(&ebu_host->chip, 1);
0684 if (ret)
0685 goto err_cleanup_dma;
0686
0687 ret = mtd_device_register(mtd, NULL, 0);
0688 if (ret)
0689 goto err_clean_nand;
0690
0691 return 0;
0692
0693 err_clean_nand:
0694 nand_cleanup(&ebu_host->chip);
0695 err_cleanup_dma:
0696 ebu_dma_cleanup(ebu_host);
0697 err_disable_unprepare_clk:
0698 clk_disable_unprepare(ebu_host->clk);
0699
0700 return ret;
0701 }
0702
0703 static int ebu_nand_remove(struct platform_device *pdev)
0704 {
0705 struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev);
0706 int ret;
0707
0708 ret = mtd_device_unregister(nand_to_mtd(&ebu_host->chip));
0709 WARN_ON(ret);
0710 nand_cleanup(&ebu_host->chip);
0711 ebu_nand_disable(&ebu_host->chip);
0712 ebu_dma_cleanup(ebu_host);
0713 clk_disable_unprepare(ebu_host->clk);
0714
0715 return 0;
0716 }
0717
0718 static const struct of_device_id ebu_nand_match[] = {
0719 { .compatible = "intel,nand-controller" },
0720 { .compatible = "intel,lgm-ebunand" },
0721 {}
0722 };
0723 MODULE_DEVICE_TABLE(of, ebu_nand_match);
0724
0725 static struct platform_driver ebu_nand_driver = {
0726 .probe = ebu_nand_probe,
0727 .remove = ebu_nand_remove,
0728 .driver = {
0729 .name = "intel-nand-controller",
0730 .of_match_table = ebu_nand_match,
0731 },
0732
0733 };
0734 module_platform_driver(ebu_nand_driver);
0735
0736 MODULE_LICENSE("GPL v2");
0737 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
0738 MODULE_DESCRIPTION("Intel's LGM External Bus NAND Controller driver");
