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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Hisilicon NAND Flash controller driver
0004  *
0005  * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
0006  *              http://www.hisilicon.com
0007  *
0008  * Author: Zhou Wang <wangzhou.bry@gmail.com>
0009  * The initial developer of the original code is Zhiyong Cai
0010  * <caizhiyong@huawei.com>
0011  */
0012 #include <linux/of.h>
0013 #include <linux/mtd/mtd.h>
0014 #include <linux/sizes.h>
0015 #include <linux/clk.h>
0016 #include <linux/slab.h>
0017 #include <linux/module.h>
0018 #include <linux/delay.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/mtd/rawnand.h>
0021 #include <linux/dma-mapping.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/mtd/partitions.h>
0024 
0025 #define HINFC504_MAX_CHIP                               (4)
0026 #define HINFC504_W_LATCH                                (5)
0027 #define HINFC504_R_LATCH                                (7)
0028 #define HINFC504_RW_LATCH                               (3)
0029 
0030 #define HINFC504_NFC_TIMEOUT                (2 * HZ)
0031 #define HINFC504_NFC_PM_TIMEOUT             (1 * HZ)
0032 #define HINFC504_NFC_DMA_TIMEOUT            (5 * HZ)
0033 #define HINFC504_CHIP_DELAY             (25)
0034 
0035 #define HINFC504_REG_BASE_ADDRESS_LEN           (0x100)
0036 #define HINFC504_BUFFER_BASE_ADDRESS_LEN        (2048 + 128)
0037 
0038 #define HINFC504_ADDR_CYCLE_MASK            0x4
0039 
0040 #define HINFC504_CON                    0x00
0041 #define HINFC504_CON_OP_MODE_NORMAL         BIT(0)
0042 #define HINFC504_CON_PAGEISZE_SHIFT         (1)
0043 #define HINFC504_CON_PAGESIZE_MASK          (0x07)
0044 #define HINFC504_CON_BUS_WIDTH              BIT(4)
0045 #define HINFC504_CON_READY_BUSY_SEL         BIT(8)
0046 #define HINFC504_CON_ECCTYPE_SHIFT          (9)
0047 #define HINFC504_CON_ECCTYPE_MASK           (0x07)
0048 
0049 #define HINFC504_PWIDTH                 0x04
0050 #define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
0051     ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
0052 
0053 #define HINFC504_CMD                    0x0C
0054 #define HINFC504_ADDRL                  0x10
0055 #define HINFC504_ADDRH                  0x14
0056 #define HINFC504_DATA_NUM               0x18
0057 
0058 #define HINFC504_OP                 0x1C
0059 #define HINFC504_OP_READ_DATA_EN            BIT(1)
0060 #define HINFC504_OP_WAIT_READY_EN           BIT(2)
0061 #define HINFC504_OP_CMD2_EN             BIT(3)
0062 #define HINFC504_OP_WRITE_DATA_EN           BIT(4)
0063 #define HINFC504_OP_ADDR_EN             BIT(5)
0064 #define HINFC504_OP_CMD1_EN             BIT(6)
0065 #define HINFC504_OP_NF_CS_SHIFT                         (7)
0066 #define HINFC504_OP_NF_CS_MASK              (3)
0067 #define HINFC504_OP_ADDR_CYCLE_SHIFT            (9)
0068 #define HINFC504_OP_ADDR_CYCLE_MASK         (7)
0069 
0070 #define HINFC504_STATUS                                 0x20
0071 #define HINFC504_READY                  BIT(0)
0072 
0073 #define HINFC504_INTEN                  0x24
0074 #define HINFC504_INTEN_DMA              BIT(9)
0075 #define HINFC504_INTEN_UE               BIT(6)
0076 #define HINFC504_INTEN_CE               BIT(5)
0077 
0078 #define HINFC504_INTS                   0x28
0079 #define HINFC504_INTS_DMA               BIT(9)
0080 #define HINFC504_INTS_UE                BIT(6)
0081 #define HINFC504_INTS_CE                BIT(5)
0082 
0083 #define HINFC504_INTCLR                                 0x2C
0084 #define HINFC504_INTCLR_DMA             BIT(9)
0085 #define HINFC504_INTCLR_UE              BIT(6)
0086 #define HINFC504_INTCLR_CE              BIT(5)
0087 
0088 #define HINFC504_ECC_STATUS                             0x5C
0089 #define HINFC504_ECC_16_BIT_SHIFT                       12
0090 
0091 #define HINFC504_DMA_CTRL               0x60
0092 #define HINFC504_DMA_CTRL_DMA_START         BIT(0)
0093 #define HINFC504_DMA_CTRL_WE                BIT(1)
0094 #define HINFC504_DMA_CTRL_DATA_AREA_EN          BIT(2)
0095 #define HINFC504_DMA_CTRL_OOB_AREA_EN           BIT(3)
0096 #define HINFC504_DMA_CTRL_BURST4_EN         BIT(4)
0097 #define HINFC504_DMA_CTRL_BURST8_EN         BIT(5)
0098 #define HINFC504_DMA_CTRL_BURST16_EN            BIT(6)
0099 #define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT        (7)
0100 #define HINFC504_DMA_CTRL_ADDR_NUM_MASK                 (1)
0101 #define HINFC504_DMA_CTRL_CS_SHIFT          (8)
0102 #define HINFC504_DMA_CTRL_CS_MASK           (0x03)
0103 
0104 #define HINFC504_DMA_ADDR_DATA              0x64
0105 #define HINFC504_DMA_ADDR_OOB               0x68
0106 
0107 #define HINFC504_DMA_LEN                0x6C
0108 #define HINFC504_DMA_LEN_OOB_SHIFT          (16)
0109 #define HINFC504_DMA_LEN_OOB_MASK           (0xFFF)
0110 
0111 #define HINFC504_DMA_PARA               0x70
0112 #define HINFC504_DMA_PARA_DATA_RW_EN            BIT(0)
0113 #define HINFC504_DMA_PARA_OOB_RW_EN         BIT(1)
0114 #define HINFC504_DMA_PARA_DATA_EDC_EN           BIT(2)
0115 #define HINFC504_DMA_PARA_OOB_EDC_EN            BIT(3)
0116 #define HINFC504_DMA_PARA_DATA_ECC_EN           BIT(4)
0117 #define HINFC504_DMA_PARA_OOB_ECC_EN            BIT(5)
0118 
0119 #define HINFC_VERSION                                   0x74
0120 #define HINFC504_LOG_READ_ADDR              0x7C
0121 #define HINFC504_LOG_READ_LEN               0x80
0122 
0123 #define HINFC504_NANDINFO_LEN               0x10
0124 
0125 struct hinfc_host {
0126     struct nand_chip    chip;
0127     struct device       *dev;
0128     void __iomem        *iobase;
0129     void __iomem        *mmio;
0130     struct completion       cmd_complete;
0131     unsigned int        offset;
0132     unsigned int        command;
0133     int         chipselect;
0134     unsigned int        addr_cycle;
0135     u32                     addr_value[2];
0136     u32                     cache_addr_value[2];
0137     char            *buffer;
0138     dma_addr_t      dma_buffer;
0139     dma_addr_t      dma_oob;
0140     int         version;
0141     unsigned int            irq_status; /* interrupt status */
0142 };
0143 
0144 static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
0145 {
0146     return readl(host->iobase + reg);
0147 }
0148 
0149 static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
0150                    unsigned int reg)
0151 {
0152     writel(value, host->iobase + reg);
0153 }
0154 
0155 static void wait_controller_finished(struct hinfc_host *host)
0156 {
0157     unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
0158     int val;
0159 
0160     while (time_before(jiffies, timeout)) {
0161         val = hinfc_read(host, HINFC504_STATUS);
0162         if (host->command == NAND_CMD_ERASE2) {
0163             /* nfc is ready */
0164             while (!(val & HINFC504_READY)) {
0165                 usleep_range(500, 1000);
0166                 val = hinfc_read(host, HINFC504_STATUS);
0167             }
0168             return;
0169         }
0170 
0171         if (val & HINFC504_READY)
0172             return;
0173     }
0174 
0175     /* wait cmd timeout */
0176     dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
0177 }
0178 
0179 static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
0180 {
0181     struct nand_chip *chip = &host->chip;
0182     struct mtd_info *mtd = nand_to_mtd(chip);
0183     unsigned long val;
0184     int ret;
0185 
0186     hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
0187     hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
0188 
0189     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_NONE) {
0190         hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
0191             << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
0192 
0193         hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
0194             | HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
0195     } else {
0196         if (host->command == NAND_CMD_READOOB)
0197             hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
0198             | HINFC504_DMA_PARA_OOB_EDC_EN
0199             | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
0200         else
0201             hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
0202             | HINFC504_DMA_PARA_OOB_RW_EN
0203             | HINFC504_DMA_PARA_DATA_EDC_EN
0204             | HINFC504_DMA_PARA_OOB_EDC_EN
0205             | HINFC504_DMA_PARA_DATA_ECC_EN
0206             | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
0207 
0208     }
0209 
0210     val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
0211         | HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
0212         | HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
0213         | ((host->addr_cycle == 4 ? 1 : 0)
0214             << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
0215         | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
0216             << HINFC504_DMA_CTRL_CS_SHIFT));
0217 
0218     if (todev)
0219         val |= HINFC504_DMA_CTRL_WE;
0220 
0221     init_completion(&host->cmd_complete);
0222 
0223     hinfc_write(host, val, HINFC504_DMA_CTRL);
0224     ret = wait_for_completion_timeout(&host->cmd_complete,
0225             HINFC504_NFC_DMA_TIMEOUT);
0226 
0227     if (!ret) {
0228         dev_err(host->dev, "DMA operation(irq) timeout!\n");
0229         /* sanity check */
0230         val = hinfc_read(host, HINFC504_DMA_CTRL);
0231         if (!(val & HINFC504_DMA_CTRL_DMA_START))
0232             dev_err(host->dev, "DMA is already done but without irq ACK!\n");
0233         else
0234             dev_err(host->dev, "DMA is really timeout!\n");
0235     }
0236 }
0237 
0238 static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
0239 {
0240     host->addr_value[0] &= 0xffff0000;
0241 
0242     hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
0243     hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
0244     hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
0245             HINFC504_CMD);
0246 
0247     hisi_nfc_dma_transfer(host, 1);
0248 
0249     return 0;
0250 }
0251 
0252 static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
0253 {
0254     struct mtd_info *mtd = nand_to_mtd(&host->chip);
0255 
0256     if ((host->addr_value[0] == host->cache_addr_value[0]) &&
0257         (host->addr_value[1] == host->cache_addr_value[1]))
0258         return 0;
0259 
0260     host->addr_value[0] &= 0xffff0000;
0261 
0262     hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
0263     hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
0264     hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
0265             HINFC504_CMD);
0266 
0267     hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
0268     hinfc_write(host, mtd->writesize + mtd->oobsize,
0269             HINFC504_LOG_READ_LEN);
0270 
0271     hisi_nfc_dma_transfer(host, 0);
0272 
0273     host->cache_addr_value[0] = host->addr_value[0];
0274     host->cache_addr_value[1] = host->addr_value[1];
0275 
0276     return 0;
0277 }
0278 
0279 static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
0280 {
0281     hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
0282     hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
0283             HINFC504_CMD);
0284 
0285     hinfc_write(host, HINFC504_OP_WAIT_READY_EN
0286         | HINFC504_OP_CMD2_EN
0287         | HINFC504_OP_CMD1_EN
0288         | HINFC504_OP_ADDR_EN
0289         | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
0290             << HINFC504_OP_NF_CS_SHIFT)
0291         | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
0292             << HINFC504_OP_ADDR_CYCLE_SHIFT),
0293         HINFC504_OP);
0294 
0295     wait_controller_finished(host);
0296 
0297     return 0;
0298 }
0299 
0300 static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
0301 {
0302     hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
0303     hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
0304     hinfc_write(host, 0, HINFC504_ADDRL);
0305 
0306     hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
0307         | HINFC504_OP_READ_DATA_EN
0308         | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
0309             << HINFC504_OP_NF_CS_SHIFT)
0310         | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
0311 
0312     wait_controller_finished(host);
0313 
0314     return 0;
0315 }
0316 
0317 static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
0318 {
0319     hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
0320     hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
0321     hinfc_write(host, HINFC504_OP_CMD1_EN
0322         | HINFC504_OP_READ_DATA_EN
0323         | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
0324             << HINFC504_OP_NF_CS_SHIFT),
0325         HINFC504_OP);
0326 
0327     wait_controller_finished(host);
0328 
0329     return 0;
0330 }
0331 
0332 static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
0333 {
0334     hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
0335 
0336     hinfc_write(host, HINFC504_OP_CMD1_EN
0337         | ((chipselect & HINFC504_OP_NF_CS_MASK)
0338             << HINFC504_OP_NF_CS_SHIFT)
0339         | HINFC504_OP_WAIT_READY_EN,
0340         HINFC504_OP);
0341 
0342     wait_controller_finished(host);
0343 
0344     return 0;
0345 }
0346 
0347 static void hisi_nfc_select_chip(struct nand_chip *chip, int chipselect)
0348 {
0349     struct hinfc_host *host = nand_get_controller_data(chip);
0350 
0351     if (chipselect < 0)
0352         return;
0353 
0354     host->chipselect = chipselect;
0355 }
0356 
0357 static uint8_t hisi_nfc_read_byte(struct nand_chip *chip)
0358 {
0359     struct hinfc_host *host = nand_get_controller_data(chip);
0360 
0361     if (host->command == NAND_CMD_STATUS)
0362         return *(uint8_t *)(host->mmio);
0363 
0364     host->offset++;
0365 
0366     if (host->command == NAND_CMD_READID)
0367         return *(uint8_t *)(host->mmio + host->offset - 1);
0368 
0369     return *(uint8_t *)(host->buffer + host->offset - 1);
0370 }
0371 
0372 static void
0373 hisi_nfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
0374 {
0375     struct hinfc_host *host = nand_get_controller_data(chip);
0376 
0377     memcpy(host->buffer + host->offset, buf, len);
0378     host->offset += len;
0379 }
0380 
0381 static void hisi_nfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
0382 {
0383     struct hinfc_host *host = nand_get_controller_data(chip);
0384 
0385     memcpy(buf, host->buffer + host->offset, len);
0386     host->offset += len;
0387 }
0388 
0389 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
0390 {
0391     struct nand_chip *chip = mtd_to_nand(mtd);
0392     struct hinfc_host *host = nand_get_controller_data(chip);
0393     unsigned int command = host->command;
0394 
0395     host->addr_cycle    = 0;
0396     host->addr_value[0] = 0;
0397     host->addr_value[1] = 0;
0398 
0399     /* Serially input address */
0400     if (column != -1) {
0401         /* Adjust columns for 16 bit buswidth */
0402         if (chip->options & NAND_BUSWIDTH_16 &&
0403                 !nand_opcode_8bits(command))
0404             column >>= 1;
0405 
0406         host->addr_value[0] = column & 0xffff;
0407         host->addr_cycle    = 2;
0408     }
0409     if (page_addr != -1) {
0410         host->addr_value[0] |= (page_addr & 0xffff)
0411             << (host->addr_cycle * 8);
0412         host->addr_cycle    += 2;
0413         if (chip->options & NAND_ROW_ADDR_3) {
0414             host->addr_cycle += 1;
0415             if (host->command == NAND_CMD_ERASE1)
0416                 host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
0417             else
0418                 host->addr_value[1] |= ((page_addr >> 16) & 0xff);
0419         }
0420     }
0421 }
0422 
0423 static void hisi_nfc_cmdfunc(struct nand_chip *chip, unsigned command,
0424                  int column, int page_addr)
0425 {
0426     struct mtd_info *mtd = nand_to_mtd(chip);
0427     struct hinfc_host *host = nand_get_controller_data(chip);
0428     int is_cache_invalid = 1;
0429     unsigned int flag = 0;
0430 
0431     host->command =  command;
0432 
0433     switch (command) {
0434     case NAND_CMD_READ0:
0435     case NAND_CMD_READOOB:
0436         if (command == NAND_CMD_READ0)
0437             host->offset = column;
0438         else
0439             host->offset = column + mtd->writesize;
0440 
0441         is_cache_invalid = 0;
0442         set_addr(mtd, column, page_addr);
0443         hisi_nfc_send_cmd_readstart(host);
0444         break;
0445 
0446     case NAND_CMD_SEQIN:
0447         host->offset = column;
0448         set_addr(mtd, column, page_addr);
0449         break;
0450 
0451     case NAND_CMD_ERASE1:
0452         set_addr(mtd, column, page_addr);
0453         break;
0454 
0455     case NAND_CMD_PAGEPROG:
0456         hisi_nfc_send_cmd_pageprog(host);
0457         break;
0458 
0459     case NAND_CMD_ERASE2:
0460         hisi_nfc_send_cmd_erase(host);
0461         break;
0462 
0463     case NAND_CMD_READID:
0464         host->offset = column;
0465         memset(host->mmio, 0, 0x10);
0466         hisi_nfc_send_cmd_readid(host);
0467         break;
0468 
0469     case NAND_CMD_STATUS:
0470         flag = hinfc_read(host, HINFC504_CON);
0471         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
0472             hinfc_write(host,
0473                     flag & ~(HINFC504_CON_ECCTYPE_MASK <<
0474                     HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
0475 
0476         host->offset = 0;
0477         memset(host->mmio, 0, 0x10);
0478         hisi_nfc_send_cmd_status(host);
0479         hinfc_write(host, flag, HINFC504_CON);
0480         break;
0481 
0482     case NAND_CMD_RESET:
0483         hisi_nfc_send_cmd_reset(host, host->chipselect);
0484         break;
0485 
0486     default:
0487         dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
0488             command, column, page_addr);
0489     }
0490 
0491     if (is_cache_invalid) {
0492         host->cache_addr_value[0] = ~0;
0493         host->cache_addr_value[1] = ~0;
0494     }
0495 }
0496 
0497 static irqreturn_t hinfc_irq_handle(int irq, void *devid)
0498 {
0499     struct hinfc_host *host = devid;
0500     unsigned int flag;
0501 
0502     flag = hinfc_read(host, HINFC504_INTS);
0503     /* store interrupts state */
0504     host->irq_status |= flag;
0505 
0506     if (flag & HINFC504_INTS_DMA) {
0507         hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
0508         complete(&host->cmd_complete);
0509     } else if (flag & HINFC504_INTS_CE) {
0510         hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
0511     } else if (flag & HINFC504_INTS_UE) {
0512         hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
0513     }
0514 
0515     return IRQ_HANDLED;
0516 }
0517 
0518 static int hisi_nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
0519                      int oob_required, int page)
0520 {
0521     struct mtd_info *mtd = nand_to_mtd(chip);
0522     struct hinfc_host *host = nand_get_controller_data(chip);
0523     int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
0524     int stat_1, stat_2;
0525 
0526     nand_read_page_op(chip, page, 0, buf, mtd->writesize);
0527     chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
0528 
0529     /* errors which can not be corrected by ECC */
0530     if (host->irq_status & HINFC504_INTS_UE) {
0531         mtd->ecc_stats.failed++;
0532     } else if (host->irq_status & HINFC504_INTS_CE) {
0533         /* TODO: need add other ECC modes! */
0534         switch (chip->ecc.strength) {
0535         case 16:
0536             status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
0537                     HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
0538             stat_2 = status_ecc & 0x3f;
0539             stat_1 = status_ecc >> 6 & 0x3f;
0540             stat = stat_1 + stat_2;
0541             stat_max = max_t(int, stat_1, stat_2);
0542         }
0543         mtd->ecc_stats.corrected += stat;
0544         max_bitflips = max_t(int, max_bitflips, stat_max);
0545     }
0546     host->irq_status = 0;
0547 
0548     return max_bitflips;
0549 }
0550 
0551 static int hisi_nand_read_oob(struct nand_chip *chip, int page)
0552 {
0553     struct mtd_info *mtd = nand_to_mtd(chip);
0554     struct hinfc_host *host = nand_get_controller_data(chip);
0555 
0556     nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
0557 
0558     if (host->irq_status & HINFC504_INTS_UE) {
0559         host->irq_status = 0;
0560         return -EBADMSG;
0561     }
0562 
0563     host->irq_status = 0;
0564     return 0;
0565 }
0566 
0567 static int hisi_nand_write_page_hwecc(struct nand_chip *chip,
0568                       const uint8_t *buf, int oob_required,
0569                       int page)
0570 {
0571     struct mtd_info *mtd = nand_to_mtd(chip);
0572 
0573     nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
0574     if (oob_required)
0575         chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
0576 
0577     return nand_prog_page_end_op(chip);
0578 }
0579 
0580 static void hisi_nfc_host_init(struct hinfc_host *host)
0581 {
0582     struct nand_chip *chip = &host->chip;
0583     unsigned int flag = 0;
0584 
0585     host->version = hinfc_read(host, HINFC_VERSION);
0586     host->addr_cycle        = 0;
0587     host->addr_value[0]     = 0;
0588     host->addr_value[1]     = 0;
0589     host->cache_addr_value[0]   = ~0;
0590     host->cache_addr_value[1]   = ~0;
0591     host->chipselect        = 0;
0592 
0593     /* default page size: 2K, ecc_none. need modify */
0594     flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
0595         | ((0x001 & HINFC504_CON_PAGESIZE_MASK)
0596             << HINFC504_CON_PAGEISZE_SHIFT)
0597         | ((0x0 & HINFC504_CON_ECCTYPE_MASK)
0598             << HINFC504_CON_ECCTYPE_SHIFT)
0599         | ((chip->options & NAND_BUSWIDTH_16) ?
0600             HINFC504_CON_BUS_WIDTH : 0);
0601     hinfc_write(host, flag, HINFC504_CON);
0602 
0603     memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
0604 
0605     hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
0606             HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
0607 
0608     /* enable DMA irq */
0609     hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
0610 }
0611 
0612 static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section,
0613                   struct mtd_oob_region *oobregion)
0614 {
0615     /* FIXME: add ECC bytes position */
0616     return -ENOTSUPP;
0617 }
0618 
0619 static int hisi_ooblayout_free(struct mtd_info *mtd, int section,
0620                    struct mtd_oob_region *oobregion)
0621 {
0622     if (section)
0623         return -ERANGE;
0624 
0625     oobregion->offset = 2;
0626     oobregion->length = 6;
0627 
0628     return 0;
0629 }
0630 
0631 static const struct mtd_ooblayout_ops hisi_ooblayout_ops = {
0632     .ecc = hisi_ooblayout_ecc,
0633     .free = hisi_ooblayout_free,
0634 };
0635 
0636 static int hisi_nfc_ecc_probe(struct hinfc_host *host)
0637 {
0638     unsigned int flag;
0639     int size, strength, ecc_bits;
0640     struct device *dev = host->dev;
0641     struct nand_chip *chip = &host->chip;
0642     struct mtd_info *mtd = nand_to_mtd(chip);
0643 
0644     size = chip->ecc.size;
0645     strength = chip->ecc.strength;
0646     if (size != 1024) {
0647         dev_err(dev, "error ecc size: %d\n", size);
0648         return -EINVAL;
0649     }
0650 
0651     if ((size == 1024) && ((strength != 8) && (strength != 16) &&
0652                 (strength != 24) && (strength != 40))) {
0653         dev_err(dev, "ecc size and strength do not match\n");
0654         return -EINVAL;
0655     }
0656 
0657     chip->ecc.size = size;
0658     chip->ecc.strength = strength;
0659 
0660     chip->ecc.read_page = hisi_nand_read_page_hwecc;
0661     chip->ecc.read_oob = hisi_nand_read_oob;
0662     chip->ecc.write_page = hisi_nand_write_page_hwecc;
0663 
0664     switch (chip->ecc.strength) {
0665     case 16:
0666         ecc_bits = 6;
0667         if (mtd->writesize == 2048)
0668             mtd_set_ooblayout(mtd, &hisi_ooblayout_ops);
0669 
0670         /* TODO: add more page size support */
0671         break;
0672 
0673     /* TODO: add more ecc strength support */
0674     default:
0675         dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
0676         return -EINVAL;
0677     }
0678 
0679     flag = hinfc_read(host, HINFC504_CON);
0680     /* add ecc type configure */
0681     flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
0682                         << HINFC504_CON_ECCTYPE_SHIFT);
0683     hinfc_write(host, flag, HINFC504_CON);
0684 
0685     /* enable ecc irq */
0686     flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
0687     hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
0688             HINFC504_INTEN);
0689 
0690     return 0;
0691 }
0692 
0693 static int hisi_nfc_attach_chip(struct nand_chip *chip)
0694 {
0695     struct mtd_info *mtd = nand_to_mtd(chip);
0696     struct hinfc_host *host = nand_get_controller_data(chip);
0697     int flag;
0698 
0699     host->buffer = dmam_alloc_coherent(host->dev,
0700                        mtd->writesize + mtd->oobsize,
0701                        &host->dma_buffer, GFP_KERNEL);
0702     if (!host->buffer)
0703         return -ENOMEM;
0704 
0705     host->dma_oob = host->dma_buffer + mtd->writesize;
0706     memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
0707 
0708     flag = hinfc_read(host, HINFC504_CON);
0709     flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
0710     switch (mtd->writesize) {
0711     case 2048:
0712         flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT);
0713         break;
0714     /*
0715      * TODO: add more pagesize support,
0716      * default pagesize has been set in hisi_nfc_host_init
0717      */
0718     default:
0719         dev_err(host->dev, "NON-2KB page size nand flash\n");
0720         return -EINVAL;
0721     }
0722     hinfc_write(host, flag, HINFC504_CON);
0723 
0724     if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
0725         hisi_nfc_ecc_probe(host);
0726 
0727     return 0;
0728 }
0729 
0730 static const struct nand_controller_ops hisi_nfc_controller_ops = {
0731     .attach_chip = hisi_nfc_attach_chip,
0732 };
0733 
0734 static int hisi_nfc_probe(struct platform_device *pdev)
0735 {
0736     int ret = 0, irq, max_chips = HINFC504_MAX_CHIP;
0737     struct device *dev = &pdev->dev;
0738     struct hinfc_host *host;
0739     struct nand_chip  *chip;
0740     struct mtd_info   *mtd;
0741     struct device_node *np = dev->of_node;
0742 
0743     host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
0744     if (!host)
0745         return -ENOMEM;
0746     host->dev = dev;
0747 
0748     platform_set_drvdata(pdev, host);
0749     chip = &host->chip;
0750     mtd  = nand_to_mtd(chip);
0751 
0752     irq = platform_get_irq(pdev, 0);
0753     if (irq < 0)
0754         return -ENXIO;
0755 
0756     host->iobase = devm_platform_ioremap_resource(pdev, 0);
0757     if (IS_ERR(host->iobase))
0758         return PTR_ERR(host->iobase);
0759 
0760     host->mmio = devm_platform_ioremap_resource(pdev, 1);
0761     if (IS_ERR(host->mmio))
0762         return PTR_ERR(host->mmio);
0763 
0764     mtd->name       = "hisi_nand";
0765     mtd->dev.parent         = &pdev->dev;
0766 
0767     nand_set_controller_data(chip, host);
0768     nand_set_flash_node(chip, np);
0769     chip->legacy.cmdfunc    = hisi_nfc_cmdfunc;
0770     chip->legacy.select_chip    = hisi_nfc_select_chip;
0771     chip->legacy.read_byte  = hisi_nfc_read_byte;
0772     chip->legacy.write_buf  = hisi_nfc_write_buf;
0773     chip->legacy.read_buf   = hisi_nfc_read_buf;
0774     chip->legacy.chip_delay = HINFC504_CHIP_DELAY;
0775     chip->legacy.set_features   = nand_get_set_features_notsupp;
0776     chip->legacy.get_features   = nand_get_set_features_notsupp;
0777 
0778     hisi_nfc_host_init(host);
0779 
0780     ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
0781     if (ret) {
0782         dev_err(dev, "failed to request IRQ\n");
0783         return ret;
0784     }
0785 
0786     chip->legacy.dummy_controller.ops = &hisi_nfc_controller_ops;
0787     ret = nand_scan(chip, max_chips);
0788     if (ret)
0789         return ret;
0790 
0791     ret = mtd_device_register(mtd, NULL, 0);
0792     if (ret) {
0793         dev_err(dev, "Err MTD partition=%d\n", ret);
0794         nand_cleanup(chip);
0795         return ret;
0796     }
0797 
0798     return 0;
0799 }
0800 
0801 static int hisi_nfc_remove(struct platform_device *pdev)
0802 {
0803     struct hinfc_host *host = platform_get_drvdata(pdev);
0804     struct nand_chip *chip = &host->chip;
0805     int ret;
0806 
0807     ret = mtd_device_unregister(nand_to_mtd(chip));
0808     WARN_ON(ret);
0809     nand_cleanup(chip);
0810 
0811     return 0;
0812 }
0813 
0814 #ifdef CONFIG_PM_SLEEP
0815 static int hisi_nfc_suspend(struct device *dev)
0816 {
0817     struct hinfc_host *host = dev_get_drvdata(dev);
0818     unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
0819 
0820     while (time_before(jiffies, timeout)) {
0821         if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
0822             (hinfc_read(host, HINFC504_DMA_CTRL) &
0823              HINFC504_DMA_CTRL_DMA_START)) {
0824             cond_resched();
0825             return 0;
0826         }
0827     }
0828 
0829     dev_err(host->dev, "nand controller suspend timeout.\n");
0830 
0831     return -EAGAIN;
0832 }
0833 
0834 static int hisi_nfc_resume(struct device *dev)
0835 {
0836     int cs;
0837     struct hinfc_host *host = dev_get_drvdata(dev);
0838     struct nand_chip *chip = &host->chip;
0839 
0840     for (cs = 0; cs < nanddev_ntargets(&chip->base); cs++)
0841         hisi_nfc_send_cmd_reset(host, cs);
0842     hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
0843             HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
0844 
0845     return 0;
0846 }
0847 #endif
0848 static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
0849 
0850 static const struct of_device_id nfc_id_table[] = {
0851     { .compatible = "hisilicon,504-nfc" },
0852     {}
0853 };
0854 MODULE_DEVICE_TABLE(of, nfc_id_table);
0855 
0856 static struct platform_driver hisi_nfc_driver = {
0857     .driver = {
0858         .name  = "hisi_nand",
0859         .of_match_table = nfc_id_table,
0860         .pm = &hisi_nfc_pm_ops,
0861     },
0862     .probe      = hisi_nfc_probe,
0863     .remove     = hisi_nfc_remove,
0864 };
0865 
0866 module_platform_driver(hisi_nfc_driver);
0867 
0868 MODULE_LICENSE("GPL");
0869 MODULE_AUTHOR("Zhou Wang");
0870 MODULE_AUTHOR("Zhiyong Cai");
0871 MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");
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